KR20030068029A - Memory device utilizing carbon nano tube and Fabricating method thereof - Google Patents

Abstract

PURPOSE: A memory device using a carbon nano tube and a method for manufacturing the same are provided to be capable of preventing the increase of resistance due to the downsized memory device and reducing heat loss, power dissipation, and the leakage of electric charge. CONSTITUTION: A memory device is provided with a silicon substrate(11), a source and drain electrode(15,17) formed and spaced apart from each other on the upper portion of the silicon substrate, a carbon nano tube(21) formed between the source and drain electrode for being used as an electron transfer channel, a memory cell(23) located at the upper portion of the carbon nano tube for storing electrons flowed from the carbon nano tube, and a gate electrode(19) located on the upper portion of the memory cell for controlling the quantity of electric charge stored in the memory cell.

Description

Memory device utilizing carbon nanotubes and method for manufacturing the same

The present invention relates to a memory device and a method of manufacturing the same, and more particularly, to a memory device having a carbon nanotube as a charge transfer channel and a method of manufacturing the same.

BACKGROUND OF THE INVENTION A memory device using a semiconductor has basic components of a transistor serving as a switch for securing a passage of current when writing or reading information into a capacitor, and a capacitor serving to preserve stored charges.

In order to allow a large amount of current to flow through the transistor, the transistor must have a high transconductance (gm) characteristic, and accordingly, there is a tendency to use a metal oxide field effect transistor (MOSFET) having a high transconductance characteristic as a switching device of a semiconductor memory device. .

A MOSFET is a transistor having as its basic components a gate electrode formed of doped polycrystalline silicon and a source and drain electrode formed of doped crystalline silicon.

The transconductance of the MOSFET is inversely proportional to the length of the channel, the thickness of the gate oxide, etc. under the same voltage conditions, and is proportional to the surface mobility, the dielectric constant of the gate oxide, and the width of the channel. Among them, the surface mobility and the dielectric constant of the oxide film are values that are already determined by the material, that is, the silicon wafer and silicon oxide film having the directivity, so that the ratio of the width and the length of the channel to the high transconductance (W / L ratio) is used. The thickness of the oxide film should be increased or thinned.

However, in order to fabricate a highly integrated memory device, the physical dimensions of the MOSFET must be reduced, and thus the size of the gate, source, and drain electrodes must be reduced, which causes various problems.

For example, if the size of the gate electrode is reduced, the cross-sectional area of the gate electrode is reduced, causing a large electrical resistance in the transistor. Reducing the size of the source and drain electrodes causes a reduction in thickness, ie junction depths, resulting in greater electrical resistance, or by reducing the distance between the source and drain, causing the source and drain depletion layers to contact each other. It causes a punch through phenomenon, making current regulation impossible. In addition, the reduction of the size of the memory device as described above reduces the width of the channel, which is the passage of current, to 70 nm or less, thereby preventing the smooth flow of current, thereby causing the memory device to malfunction.

That is, in general, a MOSFET-based memory device has a disadvantage in that it is difficult to implement a high-density memory due to problems such as heat loss, power consumption, electrical characteristic variation, and charge leakage.

Accordingly, the technical problem to be achieved by the present invention is to improve the above-described problems of the prior art, and there is no increase in resistance due to the miniaturization of a memory device, and high speed and high integration with low heat loss, power consumption, electrical characteristic variation, and charge leakage. A memory device and a method of manufacturing the same are provided.

1 is a perspective view of a memory device according to an embodiment of the present invention;

2 is a cross-sectional view of a first memory cell employed in a memory device according to an embodiment of the present invention;

3A is a cross-sectional view of a second memory cell employed in a memory device according to an embodiment of the present invention;

3B is a cross-sectional view of a third memory cell employed in a memory device according to an embodiment of the present invention;

4 is a SEM photograph of a second memory cell employed in a memory device according to an embodiment of the present invention;

5A and 5B are SEM photographs of a memory device according to an embodiment of the present invention;

6A to 6I are a process diagram of a memory device according to an embodiment of the present invention employing a first memory cell;

7A to 7E are process diagrams of a second memory cell employed in a memory device according to an embodiment of the present invention;

8A is a plan view showing the structure of a memory device according to an embodiment of the present invention;

FIG. 8B illustrates a carbon nanotube channel between the source and drain electrodes of FIG. 8A;

9 is a graph illustrating a change in source-drain current Isd with respect to a change in source-drain voltage Vsd in a memory device according to an embodiment of the present invention;

FIG. 10 is a graph illustrating a change in source-drain current Isd with respect to a change in gate voltage Vg in a memory device according to an embodiment of the present invention;

FIG. 11A is a graph illustrating a change in source-drain current Isd with respect to a change in gate voltage Vg of a P-type memory device according to an embodiment of the present invention; FIG.

FIG. 11B is a graph illustrating a change in the source-drain current Isd with respect to the change in the gate voltage Vg of the N-type memory device according to the embodiment of the present invention; FIG.

12 is a graph illustrating a change in source-drain current Isd with respect to a change in gate voltage Vg at a predetermined source-drain voltage in an N-type memory device according to an embodiment of the present invention;

FIG. 13 is a graph illustrating a change in threshold voltage Vth with respect to a change in gate voltage Vg when the drain current Id is 50nA in the memory device according to the embodiment of the present invention;

14 is a graph of the electric field between the carbon nanotubes and the gate electrode in the memory device according to an embodiment of the present invention, and the surface charge density (σ) induced at the gate surface per unit distance in the memory device according to the embodiment of the present invention; ,

FIG. 15 is a graph illustrating a change in drain current Id for 100 seconds in a memory device according to an embodiment of the present invention. FIG.

<Code Description of Main Parts of Drawing>

11; Silicon substrate 13; Silicon oxide insulation layer

15; Source electrode 17; Drain electrode

19; Gate electrode 20; First insulating film

21; Carbon nanotubes 22; Storage membrane

23; First memory cell 24; Second insulating film

25; Second memory cells 26 and 36; Porous membrane

27, 37; Nanodots 29; Third insulating film

34; Fourth insulating film 34 '; Fifth insulating film

35; Third memory cell

The present invention to achieve the above technical problem,

Substrate; and

A source electrode spaced apart from the substrate at a predetermined interval and applied with a voltage; And a drain electrode; and

A carbon nanotube connecting the source electrode and the drain electrode to become a channel for electron transfer; and

A memory cell positioned on an upper portion of the carbon nanotubes and storing charges flowing from the carbon nanotubes; And

And a gate electrode in contact with an upper portion of the memory cell, the gate electrode controlling an amount of charge flowing into the memory cell from the carbon nanotubes.

The substrate is a silicon substrate, and a silicon oxide film is stacked on the substrate.

The memory cell,

A first insulating layer formed on the carbon nanotubes to be in contact with the carbon nanotubes, and a charge storage layer deposited on the first insulating layer and storing charges; And a second insulating layer formed on the charge storage layer and in contact with the gate electrode.

The first insulating layer may have a thickness similar to that of the charge storage layer, and the second insulating layer may have a thickness twice that of the charge storage layer.

The first and second insulating layers may be formed of a silicon oxide layer, and the charge storage layer may be formed of a silicon layer or a silicon nitride layer.

The charge storage layer preferably has a thickness of 15 nm or less.

The charge storage layer may be formed as a porous layer in which a plurality of nano dots filled with a charge storage material are disposed.

Alternatively, the memory cell,

A third insulating layer formed under the gate electrode and in contact with the gate electrode; And a porous film formed under the third insulating film and in contact with the carbon nanotubes and having a plurality of nanodots filled with a charge storage material.

The third insulating layer may have a thickness twice that of the porous layer or may have a similar thickness.

The third insulating layer is a silicon oxide layer, and the charge storage material is silicon or silicon nitride.

The porous film is formed of an aluminum oxide film.

The nano dot preferably has a diameter of 15 nm or less.

The present invention also to achieve the above technical problem,

Growing a carbon nanotube on a substrate, and then forming a source electrode and a drain electrode having the carbon nanotube as a charge transfer channel to contact the carbon nanotube; and

A first insulating film, a charge storage film, and a second insulating film are sequentially deposited on the carbon nanotubes, the source electrode, and the drain electrode, and then patterned by a photo process to form a memory cell in contact with the carbon nanotubes. A second step of doing; And

And depositing a metal layer on the second insulating layer, and then patterning the same by using a photo process to form a gate electrode for controlling the amount of charge flowing from the carbon nanotubes into the charge storage layer. It provides a carbon nanotube memory device manufacturing method.

In the first step, an insulating layer is formed on the upper surface of the substrate, and carbon nanotubes are grown on the upper surface of the insulating layer.

The substrate is silicon and the insulating layer is formed of silicon oxide.

In the first step, the source electrode and the drain electrode are formed by electron beam lithography.

In the second step, the first insulating film and the storage film are deposited to a similar thickness, and the second insulating film is preferably deposited to be twice as thick as the storage film.

The first and second insulating layers are formed of silicon oxide, and the charge storage layer is formed of silicon or silicon nitride.

The charge storage layer is preferably formed to a thickness of less than 15nm.

The present invention, in order to achieve the above technical problem,

Growing carbon nanotubes on a substrate, and then forming a source electrode and a drain electrode having the carbon nanotubes as charge transfer channels to contact the carbon nanotubes;

A second step of forming a porous film having a plurality of nano dots formed by oxidizing and depositing a first insulating layer on the carbon nanotubes and the source and drain electrodes, anodizing, and etching the first insulating layer;

Depositing a charge storage material on the porous film and then etching to fill the nano dot with the charge storage material;

Depositing a second insulating film on the porous film, and then patterning the first insulating film, the porous film, and the second insulating film using a photo process to form a memory cell; And

And depositing a metal layer on the second insulating layer, and then patterning the same by using a photo process to form a gate electrode for controlling the amount of charge flowing from the carbon nanotubes into the porous layer. A method of manufacturing a carbon nanotube memory device is provided.

In the first step, an insulating layer is formed on the upper surface of the substrate, and carbon nanotubes are grown on the upper surface of the insulating layer. Here, the substrate is formed of silicon and the oxide layer is formed of silicon oxide.

In the first step, the source electrode and the drain electrode may be formed by electron beam lithography.

In the second step, the thickness of the first insulating film and the porous film is similarly deposited, and the second insulating film is preferably deposited to be twice the thickness of the storage film.

The first and second insulating layers are formed of silicon oxide.

The charge storage material is formed of silicon or silicon nitride.

The charge storage layer is preferably formed to a thickness of less than 15nm.

In the first step, all of the first insulating film is oxidized to form a porous film having a plurality of nano dots.

Since the present invention uses carbon nanotubes as charge transfer channels, it does not require a doping process for semiconductor memory devices and uses carbon nanotubes having high electrical and thermal conductivity, thereby increasing resistance or malfunction due to high integration of memory devices. The problem is solved. In addition, since a memory device including a memory cell having a charge storage film or a porous film in which nano dots are formed is formed, a high efficiency memory device can be realized.

Hereinafter, a memory device and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a perspective view illustrating a memory device according to an exemplary embodiment of the present invention.

Reference numeral 21 is a carbon nanotube. The memory device according to the embodiment of the present invention includes the carbon nanotubes 21 as channels for electron movement.

Referring to FIG. 1, a memory device according to an exemplary embodiment of the present invention may include a substrate 11, an insulating layer 13 stacked on the substrate 11, and a predetermined interval apart from the insulating layer 13. And the source electrode 15 and the drain electrode 17 made of a metal, the carbon nanotube 21 to connect the source electrode 15 and the drain electrode 17, and become an electron transfer channel, and the carbon A memory cell 23 positioned to be in contact with the nanotube 21 and storing electrons in which charge is introduced from the carbon nanotube 21, and a gate that is in contact with the memory cell 23 and controls the movement of the electron; An electrode 19 is provided.

Although the source and drain electrodes 15 and 17 are positioned on the substrate 11 in the drawing, the source drain electrodes 15 and 17 may be located inside the substrate 11. In this case, the carbon nanotubes 21 may be located inside or in contact with the surface of the substrate 11.

The substrate 11 is a silicon substrate, and the insulating layer 13 stacked thereon is generally formed of silicon oxide.

The source and drain electrodes 15 and 17 may be made of a metal such as titanium (Ti) or gold (Au), and the gate electrode 19 may be formed of a metal such as polysilicon. In addition, the transistor structure is formed by a known semiconductor process such as photolithography, e-beam lithography, etching, oxidation, thin film deposition.

The carbon nanotube 21 is an allotrope of carbon, in which a hexagonal honeycomb is formed by combining each carbon atom with another carbon atom, and a graphite sheet formed by combining a plurality of carbon atoms is rolled round to a nano size diameter. To achieve. The carbon nanotubes 21 exhibit the characteristics of metals or semiconductors according to the angle and structure of the graphite surface being curled, and research using the characteristics of the carbon nanotubes has been actively conducted in high-tech industries, particularly nanotechnology industries.

Carbon nanotubes are divided into two types of carbon nanotubes according to their electrical properties. That is, it can be divided into metallic carbon nanotubes having a linear relationship with the current voltage characteristics regardless of the gate voltage, and carbon nanotubes having semiconductor characteristics with the current voltage characteristics being largely influenced by the gate voltage.

The carbon nanotubes 21 used in the memory device according to the exemplary embodiment of the present invention are carbon nanotubes having semiconductor characteristics, and are characterized by electrons moving through the carbon nanotubes 21 according to a voltage applied to the gate electrode 19. The flow, i.e. the current, is controlled.

The carbon nanotubes 21 include arc discharge, laser vapor deposition, plasma enhanced chemical vapor deposition (PECVD), thermal chemical vapor deposition (PCVD), and vapor phase synthesis (Vapor). phase growth) and the like.

The first memory cell, the second memory cell and the third memory cell used in the memory device according to the embodiment of the present invention are shown in Figs. 2, 3A and 3B, respectively.

2 is a cross-sectional view of a first memory cell used in a memory device according to an embodiment of the present invention.

Referring to FIG. 2, the first memory cell 23 used in the memory device according to the embodiment of the present invention includes first and second insulating films 20 and 24 and a charge storage film 22. The charge storage layer 24 stores charge, that is, electrons and holes, and is formed between the first and second insulating layers 20 and 24. The first and second insulating layers 20 and 24 are formed of silicon oxide (SiO ₂ ), and the charge storage layer 22 is formed of silicon (Si) or silicon nitride (Si ₃ N ₄ ). In particular, Si ₃ N ₄ thin films provide low potential trap sites that can store multiple charges.

The total thickness of the first memory cell 23 is approximately 60 nm and the thickness of the charge storage film 22 is preferably about 15 nm or less. It has been confirmed that the silicon film or silicon nitride film used as the charge storage film 22 has a function of storing electrons at a thickness of 100 nm or less. Here, the first insulating film 20 is preferably formed to have a thin thickness to facilitate the tunneling of the charge injected from the carbon nanotubes 21 shown in Figure 1, the second insulating film 24 is It is preferable to form thick so that charge injection from the gate electrode 19 can be suppressed and the charge stored in the charge storage film 22 can be retained for a long time. For example, the first insulating layer 20 may be formed of a 7 nm oxide thin film, the charge storage layer 22 may be formed of a 7 nm Si ₃ N ₄ thin film, and the second insulating layer 24 may be formed of a 14 nm oxide thin film. . That is, the thickness ratio of the first insulating film 20, the charge storage film 22, and the second insulating film 24 is formed to be 1: 1: 2 so that charges transferred from the carbon nanotubes are transferred to the charge storage film 22 for a long time. I can hold it stably.

3A is a cross-sectional view of a second memory cell used in a memory device according to an embodiment of the present invention.

As shown, the second memory cell 25 used in the memory device according to the embodiment of the present invention includes a third insulating film 29 formed to contact the gate electrode 19 and the third insulating film ( 29 includes a porous film 26 deposited under the 29 and having a plurality of nanodots 27 filled with the charge storage material 28.

The third insulating layer 29 may be made of silicon oxide, and the charge storage material 28 may be made of silicon or silicon nitride. Preferably, the thickness of the third insulating layer 29 is thicker than the thickness of the porous layer 26 to stably store the charge storage material 28 of the nano-dots 27.

3B is a cross-sectional view illustrating a third memory cell 35 used in a memory device according to an embodiment of the present invention.

The third memory cell 35 used in the memory device according to the embodiment of the present invention has a structure in which an insulating film is further stacked below the porous film 26 of the second memory cell 25. ), A porous film 36 on which the plurality of nanodots 37 filled with the electron storage material 38 are located, and a fifth insulating film 34 '. The fourth insulating film 34 is preferably formed thick so as to suppress charge injection from the gate electrode 19 shown in FIG. 1 and to maintain the charge retained in the charge storage material 38 for a long time. 34 ') is preferably formed thin so that electrons or holes can easily tunnel from the carbon nanotubes 21 and move to the porous film 36.

FIG. 4 is a fourth insulating film 34 formed of SiO ₂ in the third memory cell 35 used in the memory device according to the embodiment of the present invention illustrated in FIG. 3B, and the porous film 36 and the third insulating film are formed as shown in FIG. (34 ') is formed of Al ₂ O ₃ , and the SEM (Scanning Electron Microscopy) photograph of the electron storage material 38 formed of Si (or Si ₃ N ₄ ) is shown.

5A and 5B are SEM images showing the carbon nanotubes 21 connecting the source electrode 15 and the drain electrode 17 in the memory device according to the embodiment of the present invention. The produced carbon nanotubes 21 were measured to have a diameter of about 3 mm as measured using nuclear microscopy.

6A to 6I are flowcharts illustrating a method of manufacturing a memory device according to an exemplary embodiment of the present invention including a first memory cell 23.

First, as shown in FIG. 6A, the insulating layer 13 is deposited on the upper surface of the substrate 11, and then the carbon nanotubes 21 are grown on the upper surface thereof. The CNT powder produced by CVD (Chemical Vapor Deposition) technology is dispersed in a chloroform solution and then applied at various points on the silicon substrate 11 and dried. In the figure, only a single carbon nanotube 21 formed on one region is shown.

Next, as shown in FIG. 6B, a conductive material layer 14 for forming source and drain electrodes, for example, a material layer 14 made of a metal layer such as Au or Ti, is deposited, and then a mask 12a is formed. Is positioned on top of the conductive material layer 14 and patterned by electron beam lithography. It is desirable to thermally anneal the source and drain electrodes 15, 17 formed after patterning to reduce contact resistance. For example, rapid annealing may be performed at a temperature of 600 ° C. for about 30 seconds in a vacuum environment. Source and drain electrodes 15, 17 formed in this manner are shown in FIG. 6C.

6D to 6F illustrate a process of depositing the first memory cell 23.

Referring to FIG. 6D, the upper and insulating layers of the carbon nanotubes 21 connecting the positive and negative electrodes 15 and 17 between the source and drain electrodes 15 and 17 and the source and drain electrodes 15 and 17. The first insulating film 20a, the charge storage film 22a, and the second insulating film 24a are sequentially deposited on the surface of (13) to form a memory cell 23a. Next, as shown in FIG. 6E, the mask 12b is positioned on the top, exposed and developed, and then contacted with the source and drain electrodes 15 and 17 and the top of the carbon nanotube 21 as shown in FIG. 6F. The memory cell 23 is formed. The memory cell 23 includes a first insulating film 20 made of oxide, a charge storage film 22 made of Si or Si ₃ N ₄ , and a second insulating film 24 made of oxide. In order to form an oxide film, SiH ₄ and O ₂ gases are mixed to use a CVD method, and to form a Si ₃ N ₄ film, SiH ₂ Cl ₂ and NH ₃ gases are used.

6G to 6I illustrate a process of forming a gate electrode.

Referring to FIG. 6G, the metal layer 18 for forming the gate electrode is deposited on the surface of the insulating layer 13 to deposit the source and drain electrodes 15 and 17, the carbon nanotubes 21, and the memory cells 23. Apply. As shown in FIG. 6H, when the mask 12c is positioned, exposed, developed and etched on the metal layer 18, the gate electrode 19 is patterned as shown in FIG. 6I.

7A to 7E are process diagrams of the third memory cell 35 employed in the memory device according to the embodiment of the present invention.

First, as shown in FIG. 7A, when the fifth insulating layer 34 ′ is oxidized, an oxide layer 36 ′ of the fifth insulating layer 34 ′ is formed on the upper portion. As shown, a porous membrane 36 in which a plurality of nanodots 37 are formed is manufactured. For example, when aluminum is used as the fifth insulating layer 34 ′, it is oxidized by applying electricity to a sulfuric acid solution or a phosphoric acid solution to form a plurality of nanodots 37 as shown. This oxidation is called anodization. When oxidized, aluminum is formed into alumina and becomes slightly bulky.

Next, as shown in FIG. 7C, the chemical vapor deposition (CVD), sputtering, and the like of silicon or silicon nitride used as a material forming the charge storage layer 22 in the plurality of nanodots 37 is performed. After filling, and dry etching as shown in FIG. 7D, a porous film 36 capable of collecting charges is formed. When the fourth insulating layer 34 is deposited on the upper surface, the third memory cell 35 is completed. In the method of manufacturing the memory device including the third memory cell 35, the carbon nanotubes 21 and the source and drain electrodes 15 and 17 are formed as shown in FIGS. 6A to 6C. The third memory cell 35 may be formed on the carbon nanotubes 21, and after the third memory cell 35 is formed, the gate electrode 19 may be formed using a process as shown in FIGS. 6G to 6I. Can be formed.

The second memory cell 25 may be formed in a similar manner. In the process of forming the third memory cell 35, the fifth insulating layer 34 ′ is completely oxidized to form a porous layer 26 having a plurality of nano dots 27, and a charge storage material on the nano dots 27. After filling and etching 28, the third insulating layer 24 is deposited on the second memory cell 25 as illustrated in FIG. 3B.

In the memory device according to the embodiment of the present invention, when the source electrode 15 is grounded and a positive voltage is applied to the drain electrode 17, electrons move to the carbon nanotubes 21 so that a current flows. At this time, when a predetermined gate voltage higher than the drain voltage applied to the drain electrode 17 is applied to the gate electrode 19, electrons move from the carbon nanotube 21 to the memory cell 23 and the first insulating film 20 or The fifth insulating layer 34 ′ is tunneled to move to the charge storage layer 22 or the nanodots 27 and 37. By appropriately adjusting the gate voltage and the drain voltage, electrons may be stored, erased, and leaked in the charge storage film 22 and the nanodots 27 and 37 to record, remove, and reproduce information.

FIG. 8A is a plan view of a memory device including a single upper gate electrode, a plurality of source and drain electrodes disposed below, and carbon nanotubes.

FIG. 8B shows a picture in which carbon nanotubes are connected between the source electrode S and the drain electrode D of FIG. 8A.

Memory device according to an embodiment of the present invention is appropriately adjusted to the material and thickness of the storage film constituting the memory cell, the diameter and length of the plurality of nano-dots disposed in the porous film, the material of the material filling the nanotube channel and gate Voltage and source-drain voltages can be adjusted appropriately to allow operation in volatile or nonvolatile memory.

9 is a graph illustrating a relationship between a voltage between the source and drain electrodes and a current between the source and drain electrodes when the gate voltage varies from 0V to 10V in the memory device according to the exemplary embodiment of the present invention.

f ₁ shows that the source-drain current I _sd becomes 0 when the gate electrode is 0V regardless of the change of the source-drain voltage V _sd .

f ₂ shows that the source-drain current (I _sd ) increases from 0A to about 1000nA when the source and drain voltage (Vsd) increases with a positive value when the gate electrode is 10V, and the source-drain voltage is negative. When it decreases with the value of, it decreases from 0A to about -1000nA.

If the gate voltage is 0 at a constant source-drain voltage, there is no electron movement between the source and the drain, so information cannot be recorded. If the gate voltage is greater than 0, the source-drain current starts to flow and the gate voltage is increased by a predetermined number. It can capture the former and store the information.

FIG. 10 is a graph showing a change in current between source and drain electrodes Isd with respect to a change in gate voltage in a field effect transistor (CNT FET) having a charge storage film made of a 28 nm ONO thin film.

The current-to-drain current Isd increases as the negative gate electrode increases and decreases to several femto amps (fA) at the positive gate electrode, showing the current-voltage (IV) characteristics of the p-type CNT FET. . The on-state current Ion ratio (Ion / Ioff) to the off-state current Ioff appears to exceed 10 ⁵ when Vsd = 1V when the gate electrode changes from -4V to 4V. The off-state current remained below a few pA for the duration of the measurement. This is believed to be due to the structure in which the gate electrode of the memory element is located and the high breakdown voltage of the ONO thin film. In flash memory, the higher the Ion / Ioff ratio, the higher the threshold voltage, which improves performance.

FIG. 11A shows the current-voltage (IV) characteristics of a P-type CNT memory device having a 7 nm thick memory cell (SiO ₂ / Si ₃ N ₄ / SiO ₂ ), and FIG. 11B shows a 30 nm thick memory cell (SiO _2). / Si ₃ N ₄ / SiO ₂ ) shows the current-voltage (IV) characteristics of the N-type CNT memory device.

Referring to FIG. 11A, in the P-type CNT memory device, Isd varies slightly depending on the height of Vsd. However, when the gate voltage Vg is about 2.5V, the source-drain current Isd decreases rapidly. see.

Referring to FIG. 11B, in the N-type CNT memory device, the drain current Id exhibits a clear hysteresis phenomenon when the gate voltage becomes 4V or more when Vsd = 3V.

FIG. 12 is a graph illustrating a change in drain current Id as the gate voltage Vg changes from 0V to 1V when different Vsds are applied to an N-type CNT memory device.

Referring to the drawings, n1 is when Vsd is 0V, n2 is when Vsd is -5V, n3 is when Vsd is -5.5V, n4 is when Vsd is -6V, n5 is when Vsd is -6.5V It shows the change of Id for Vg. From n1 to n5 it can be seen that Id increases as Vg increases and saturates at about 0.6V.

When h is the thickness of the memory cell, that is, the ONO film, and L and r are the length and radius of the carbon nanotubes, respectively, the carbon nanotube capacitance per unit length for the gate electrode is expressed by Equation 1 below.

If the effective dielectric constant of the ONO film is -3, h = 30 nm, r = 1.5 nm, L = 1 μm, and the missing gate voltage (Vgd) = 2V, the hole density (P) is 580 μm. You get ^-1 . At this time, the hole mobility (μ _h ) is represented by Equation 2.

This value is higher than the hole mobility of MWNT (Multi wall nanotube) reported by Single Wall Nanotube (SWNT) and Matter.

FIG. 13 is a graph illustrating a change in threshold voltage according to a change in Vg when Id = 50nA in the same memory device.

The positive gate voltage applied raises the threshold voltage, which means that holes are injected from the carbon nanotubes into the ONO thin film and the trap site is filled with holes. When the gate voltage Vg increases from 0V to 7V, the threshold voltage increases about 60mV, indicating that it is quasi-quantized.

FIG. 14 shows a simplified diagram of the electric field between the carbon nanotubes and the gate electrode and a graph of the surface charge density σ induced at the gate surface per unit distance.

Referring to FIG. 14, the gate voltage forms a high electric field around the surface of the carbon nanotubes (CNT). Considering the gate electrode as a perfect conductor and assuming that the carbon nanotube diameter is 3 nm, the ONO thin film between the carbon nanotube and the gate electrode can be assumed to be a single layer having an effective dielectric constant of 3 so that the electric field near the carbon nanotube can be calculated. have. If the gate voltage is 5V, the calculated electric field is 970V / μm, which is enough to create a Fowller Nodheim-type tunneling. Furthermore, when tunneled charge flows along the electric field line, it is trapped in the nitride film in proportion to the strength of the electric field calculated by the induced charge distribution. In the calculation, 70% of the total tunneled charges correspond to the full width half maximum (FWHM) of the charge density peak and can be injected into the 14 nm thick nitride film of the ONO thin film. It is known that charge at room temperature quantizes the quantum dots to 10 nm or less. Referring to the graph, the induced charge density (σ) increases as the carbon nanotube (CNT) approaches.

15 is a graph showing a change in the drain current Id for 100 seconds.

The localized charge distribution can be induced in the nitride film due to the high electric field distribution of the localized carbon nanotubes, and the charge trapped in the local region can diffuse into the region where the charge is not stored, but the total current is time as shown. Even after this, it remains constant. From this, it can be seen that the trap site for storing charge in the ONO thin film of the carbon nanotube memory device acts as a quantum dot of the flash memory.

The present invention is a nonvolatile memory using a CNT-FET and an ONO thin film, in which charge is stored at a trap site of the ONO thin film. The stored charge has a quantized voltage increase of about 60mV. This indicates that the ONO thin film has a quasi-quantized energy state. The quantized state is associated with localized high fields associated with nanoscale carbon nanotube channels and shows that carbon nanotube memory devices can operate as ultra-high-density large-capacity flash memories.

The memory device according to the embodiment of the present invention has a charge storage film or a porous film having a nano-dot to replace the doping required to move the electrons between the source and drain in the conventional semiconductor device using carbon nanotubes and stores charge It does not require a separate capacitor.

In addition, since a small transistor can be manufactured using carbon nanotubes having characteristics of high electron conductivity and thermal conductivity as an electron transfer channel, a highly integrated and highly efficient memory device can be realized.

While many details are set forth in the foregoing description, they should be construed as illustrative of preferred embodiments, rather than to limit the scope of the invention.

For example, those skilled in the art to which the present invention pertains may use other materials having excellent characteristics of trapping electrons as a charge storage film or a charge storage material according to the technical idea of the present invention. Therefore, the scope of the present invention should not be defined by the described embodiments, but should be determined by the technical spirit described in the claims.

As described above, an advantage of the memory device according to the present invention is that it is possible to implement a highly efficient highly integrated memory device having a small transistor using high-conductivity carbon nanotubes and a memory cell for storing electrons.

Claims (36)

Board; A source electrode spaced apart from the substrate at a predetermined interval and applied with a voltage; And a drain electrode; A carbon nanotube connecting the source electrode and the drain electrode to become a channel for electron transfer; A memory cell positioned on an upper portion of the carbon nanotubes and storing charges flowing from the carbon nanotubes; And And a gate electrode in contact with an upper portion of the memory cell, the gate electrode controlling an amount of charge flowing from the carbon nanotubes to the memory cell. The method of claim 1, The substrate is a carbon nanotube memory device, characterized in that the silicon substrate. The method of claim 2, Carbon nanotube memory device, characterized in that the silicon oxide film is stacked on top of the substrate. The method of claim 1, wherein the memory cell, A first insulating layer formed on the carbon nanotubes to contact the carbon nanotubes; A charge storage layer deposited on the first insulating layer and storing charge; And And a second insulating layer formed on the charge storage layer and in contact with the gate electrode. The method of claim 4, wherein And the first insulating layer has a thickness similar to that of the charge storage layer. The method of claim 4, wherein And the second insulating layer has a thickness twice that of the charge storage layer. The method of claim 4, wherein The first and second insulating film is a carbon nanotube memory device, characterized in that the silicon oxide film. The method of claim 4, wherein The charge storage film is a carbon nanotube memory device, characterized in that the silicon film or silicon nitride film. The method of claim 4, wherein The charge storage layer is carbon nanotube memory device, characterized in that having a thickness of less than 15nm. The method of claim 4, wherein The charge storage film is a carbon nanotube memory device, characterized in that the porous film is arranged with a plurality of nano dots filled with a charge storage material. The method of claim 1, wherein the memory cell, A third insulating layer formed under the gate electrode and in contact with the gate electrode; And And a porous film formed under the third insulating film and in contact with the carbon nanotubes and having a plurality of nanodots filled with a charge storage material. The method of claim 11, The third insulating film has a carbon nanotube memory device, characterized in that twice as thick as the porous film. The method of claim 11, And the third insulating film has a thickness similar to that of the porous film. The method of claim 11, The third insulating film is a carbon nanotube memory device, characterized in that the silicon oxide film. The method of claim 10 or 11, The charge storage material is carbon nanotube memory device, characterized in that the silicon or silicon nitride. The method of claim 10 or 11, The porous film is a carbon nanotube memory device, characterized in that the aluminum oxide film. The method of claim 10 or 11, The nano dot has a carbon nanotube memory device, characterized in that having a diameter of 15nm or less. Growing carbon nanotubes on a substrate, and then forming a source electrode and a drain electrode having the carbon nanotubes as charge transfer channels to contact the carbon nanotubes; A first insulating film, a charge storage film, and a second insulating film are sequentially deposited on the carbon nanotubes, the source electrode, and the drain electrode, and then patterned by a photo process to form a memory cell in contact with the carbon nanotubes. A second step of doing; And And depositing a metal layer on the second insulating layer and then patterning the photo layer using a photo process to form a gate electrode for controlling the amount of charge flowing from the carbon nanotubes into the charge storage layer. Carbon nanotube memory device manufacturing method. The method of claim 18, In the first step, the carbon nanotube memory device manufacturing method characterized in that the insulating layer is formed on the upper surface of the substrate and the carbon nanotubes are grown on the upper surface of the insulating layer. The method of claim 19, The substrate is silicon and the insulating layer is a carbon nanotube memory device manufacturing method characterized in that the silicon oxide. The method of claim 18 or 19, In the first step, the carbon nanotube memory device manufacturing method, characterized in that for forming the source electrode and the drain electrode by electron beam lithography. The method of claim 18, The carbon nanotube memory device manufacturing method of claim 2, wherein the first insulating layer and the storage layer are deposited to a similar thickness. The method of claim 18, In the second step, the second insulating film is a carbon nanotube memory device manufacturing method characterized in that the deposition to be twice the thickness of the storage film. The method of claim 18, And the first and second insulating layers are formed of silicon oxide. The method of claim 18, The charge storage layer is a carbon nanotube memory device manufacturing method, characterized in that formed of silicon or silicon nitride. The method of claim 18, The charge storage film is a carbon nanotube memory device manufacturing method, characterized in that formed to a thickness of less than 15nm. Growing carbon nanotubes on a substrate, and then forming a source electrode and a drain electrode having the carbon nanotubes as charge transfer channels to contact the carbon nanotubes; A second step of forming a porous film having a plurality of nano dots formed by oxidizing and depositing a first insulating layer on the carbon nanotubes and the source and drain electrodes, anodizing, and etching the first insulating layer; Depositing a charge storage material on the porous film and then etching to fill the nano dot with the charge storage material; Depositing a second insulating film on the porous film, and then patterning the first insulating film, the porous film, and the second insulating film using a photo process to form a memory cell; And And depositing a metal layer on the second insulating layer, and then patterning the same by using a photo process to form a gate electrode for controlling the amount of charge flowing from the carbon nanotubes into the porous layer. Carbon nanotube memory device manufacturing method. The method of claim 27, In the first step, the carbon nanotube memory device manufacturing method characterized in that the insulating layer is formed on the upper surface of the substrate and the carbon nanotubes are grown on the upper surface of the insulating layer. The method of claim 28, The method of claim 1, wherein the substrate is formed of silicon and the insulating layer is formed of silicon oxide. The method of claim 27 or 28, In the first step, the carbon nanotube memory device manufacturing method, characterized in that for forming the source electrode and the drain electrode by electron beam lithography. The method of claim 27, In the second step, the carbon nanotube memory device manufacturing method, characterized in that for depositing a similar thickness of the first insulating film and the porous film. The method of claim 27, In the second step, the second insulating film is a carbon nanotube memory device manufacturing method characterized in that the deposition to be twice the thickness of the storage film. The method of claim 27, And the first and second insulating layers are formed of silicon oxide. The method of claim 27, And the charge storage material is formed of silicon or silicon nitride. The method of claim 27, The charge storage film is a carbon nanotube memory device manufacturing method characterized in that formed to a thickness of less than 100nm. The method of claim 27, The carbon nanotube memory device manufacturing method of claim 1, wherein the first insulating film is oxidized to form a porous film having a plurality of nano dots.