KR20030060012A - Semiconductor device having layout for reducing chip size - Google Patents

Semiconductor device having layout for reducing chip size Download PDF

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Publication number
KR20030060012A
KR20030060012A KR1020020000608A KR20020000608A KR20030060012A KR 20030060012 A KR20030060012 A KR 20030060012A KR 1020020000608 A KR1020020000608 A KR 1020020000608A KR 20020000608 A KR20020000608 A KR 20020000608A KR 20030060012 A KR20030060012 A KR 20030060012A
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esd
pad
guard ring
doped
semiconductor device
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KR1020020000608A
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Korean (ko)
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이송자
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삼성전자주식회사
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Publication of KR20030060012A publication Critical patent/KR20030060012A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: A semiconductor device having layout for reducing chip size is provided to be capable of reducing the total surface involved by partially overlaying between a pad and an ESD(Electro-Static Discharge) structure. CONSTITUTION: An ESD structure(40) is provided with an ESD part(46) located at the center portion of the ESD structure, the first guard ring(41) doped with P+ type dopants installed for surrounding the ESD part, the second guard ring(42) doped with N+ type dopants installed and spaced apart from the first guard ring, and an N-well(44) installed for including the second guard ring. At this time, a pad(50) is located and partially overlaid with the ESD structure. Preferably, the pad is capable of covering the entire region of the ESD structure.

Description

소요 면적 감소를 위한 요소 배치를 가지는 반도체 장치{Semiconductor device having layout for reducing chip size}Semiconductor device having layout for reducing required area {Semiconductor device having layout for reducing chip size}

본 발명은 소요 면적을 줄이기 위한 요소 배치를 가지는 반도체 장치에 관한 것으로, 보다 상세하게는 최종 단계에서 형성되는 패드와 주변 회로 형성 단계에서 형성되는 ESD(Electrostatic Discharge) 구조 사이에 칩 크기를 줄일 수 있는 배열을 가지는 반도체 장치에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an element arrangement for reducing a required area, and more particularly, to reduce a chip size between a pad formed in a final step and an electrostatic discharge (ESD) structure formed in a peripheral circuit forming step. A semiconductor device having an arrangement.

반도체 장치의 소자 고집적화에 따라 반도체 장치에 집적되는 소자 수가 증가하면서 단위 소자가 차지하는 면적과 함께 소자와 소자 사이의 거리 및 연결 배선의 폭도 줄어든다. 특히 메모리 장치에서 셀 어레이 영역은 반복 패턴이 고밀도로 형성되도록 설계되며, 거의 여유 공간을 남기지 않게 된다. 한편, 셀 구동을 위한 주변 회로 영역도 점차 고집적화되나, 상대적으로 소자 밀도가 높지 않은 영역을 이루게 된다.As device integration of semiconductor devices increases, the number of devices integrated in a semiconductor device increases, so that the area occupied by a unit device decreases as well as the distance between the device and the width of the connection wiring. In particular, in the memory device, the cell array region is designed to have a high density of repeating patterns, and leaves little free space. On the other hand, the peripheral circuit region for driving the cell is also gradually integrated, but the region is relatively low in device density.

그런데, 반도체 장치의 안전성을 위해 주변 회로 영역에서 형성되는 ESD(Electrostatic Discharge) 구조와 반도체 형성 후 외부와의 전기 접속을 위해 형성되는 패드부는 특성상 반도체 칩에서 상당한 면적을 차지하게 된다. 특히, 다중 입출력 (Multi Input/Output) 구조의 반도체 장치에서 입출력 패드 및 ESD 구조가 차지하는 면적 비중은 매우 크게 된다.However, for the safety of the semiconductor device, an electrostatic discharge (ESD) structure formed in the peripheral circuit region and a pad portion formed for electrical connection with the outside after semiconductor formation occupy a considerable area in the semiconductor chip. In particular, the area ratio occupied by the input / output pad and the ESD structure becomes very large in a semiconductor device having a multi input / output structure.

도1은 기존의 반도체 장치의 입출력 패드(10) 및 주변 회로(12)의 전기적 연결을 개념적으로 표시한 설명도이다. 이 설명도에서 ESD 회로(11)는 간략하게 표시되어 두 개의 다이오드가 연속된 것으로 나타나고 있다. 이 설명도에 따르면, ESD 회로(11)는 회로 배치의 관점에서 패드(10)와 칩 내의 주변 회로(12) 사이의 연결 과정에 있어서 칩 내의 주변 회로(12)들을 정전기로부터 보호하게 된다. 따라서, ESD 회로(11)가 항상 패드(10)와 가깝게 위치하게 된다.1 is an explanatory diagram conceptually showing electrical connection between an input / output pad 10 and a peripheral circuit 12 of a conventional semiconductor device. In this explanatory diagram, the ESD circuit 11 is briefly shown to show that two diodes are continuous. According to this explanatory diagram, the ESD circuit 11 protects the peripheral circuits 12 in the chip from static electricity in the connection process between the pad 10 and the peripheral circuit 12 in the chip in terms of circuit arrangement. Thus, the ESD circuit 11 is always located close to the pad 10.

그러나, 한편, 패드는 종래부터 장치 검사 단계 등에서 프루브 검사와 관련 하부 회로와 단락 등의 문제를 염려하여 셀이나 다른 주변 회로에 겹치지 않도록 형성되는 것이 통례이다. 따라서, ESD 구조는 도2와 같이 패드(23) 옆에 별도로 형성된다. 도2에서 도1의 다이오드는 불순물 종류 및 농도를 달리하는 영역들 사이의 실제적 접속(Junction) 구조로 나타나고 있다. ESD 장치(20)는 P+형 불순물로도핑된 가드 링(21)으로 둘러싸이고, 그 외각에는 다시 N+형 불순물로 도핑된 가드 링(22)이 ESD 장치(20)와 P+형 불순물로 도핑된 가드 링(21)을 둘러싸고 있다. N+형 불순물로 도핑된 가드 링(22)은 또한 N웰(nwell:24)에 내포되어 있다.On the other hand, the pad is conventionally formed so as not to overlap the cell or other peripheral circuits in the device inspection step or the like due to concerns about problems such as probe inspection and related lower circuits and short circuits. Thus, the ESD structure is formed separately beside the pad 23 as shown in FIG. In FIG. 2, the diode of FIG. 1 is shown as an actual junction structure between regions having different impurity types and concentrations. The ESD device 20 is surrounded by a guard ring 21 doped with a P + type impurity, and on the outside thereof, a guard ring 22 doped with an N + type impurity is again doped with an ESD device 20 and a P + type impurity. It surrounds the ring 21. The guard ring 22 doped with N + type impurities is also contained in the Nwell 24.

상대적으로 넓은 면적을 차지하는 패드와 ESD 구조 사이의 이런 제약은 반도체 칩 형성에 있어 소요 면적을 줄이기 어렵게 하는 요인이 된다.This constraint between the relatively large area pad and the ESD structure makes it difficult to reduce the area required for semiconductor chip formation.

본 발명은 상술한 종래 반도체 장치의 문제점을 해결하기 위한 것으로, 패드와 ESD 구조 가지는 반도체 장치로서, 총 형성 면적을 줄일 수 있는 이들 요소 배열을 가지는 반도체 장치를 제공하는 것을 목적으로 한다.SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the conventional semiconductor device described above, and an object thereof is to provide a semiconductor device having a pad and an ESD structure and having these element arrangements capable of reducing the total formation area.

도1은 기존의 반도체 장치의 입출력 패드(10) 및 주변 회로(12)의 전기적 연결을 개념적으로 표시한 설명도이다.1 is an explanatory diagram conceptually showing electrical connection between an input / output pad 10 and a peripheral circuit 12 of a conventional semiconductor device.

도2는 종래의 패드와 ESD(Electrostatic Discharge) 구조의 상대적 위치를 나타낸 평면 배치도이다.2 is a plan view showing a relative position of a conventional pad and an electrostatic discharge (ESD) structure.

도3 및 도4는 본 발명에 따른 패드와 ESD(Electrostatic Discharge) 구조의 상대적 위치를 나타낸 평면 배치도이다.3 and 4 are planar layouts showing relative positions of a pad and an electrostatic discharge (ESD) structure according to the present invention.

상기 목적을 달성하기 위한 본 발명의 반도체 장치는 가드 링을 포함하는 ESD 구조가 형성된 영역과 적어도 일부에서 겹치도록 패드를 형성된 것을 특징으로 한다.The semiconductor device of the present invention for achieving the above object is characterized in that the pad is formed so as to overlap at least in part with the region in which the ESD structure including the guard ring is formed.

본 발명에서 바람직하게는 위쪽에서 볼 때 패드의 일부가 ESD 구조의 외측인 N+ 불순물로 도핑된 가드 링의 일 부분을 커버하도록 형성된다.In the present invention, preferably, a portion of the pad as viewed from above is formed to cover a portion of the guard ring doped with N + impurities that is outside of the ESD structure.

한편, 본 발명에서 패드가 ESD 구조의 전 영역을 커버하는 실시예도 상정할 수 있다.Meanwhile, in the present invention, an embodiment in which the pad covers the entire area of the ESD structure may also be assumed.

이하 도면을 참조하면서 실시예를 통해 본 발명을 설명하기로 한다.Hereinafter, the present invention will be described with reference to the accompanying drawings.

도3은 본 발명의 일 실시예에 따라 패드가 이 패드와 연관된 ESD 구조와 겹치도록 형성된 형태를 나타내는 평면도이다. 이때, ESD 구조(40)는 종래와 같이 기판에 주변 회로 장치와 함께 형성된다. 보다 구체적으로, ESD 장치(46)는 P+형 불순물로 도핑된 4각 띠모양의 가드 링(41)으로 둘러싸이고, P+형 불순물로 도핑된 가드 링(21)은 그 외측에 형성되는 4각 띠모양의 N+형 불순물로 도핑된 가드 링(42)으로 둘러싸여 있고, N+형 불순물로 도핑된 가드 링(42)은 또한 N 웰(nwell:44)에 내포되어 있다.Figure 3 is a plan view showing a pad formed so as to overlap with an ESD structure associated with the pad in accordance with one embodiment of the present invention. At this time, the ESD structure 40 is formed with the peripheral circuit device on the substrate as in the prior art. More specifically, the ESD device 46 is surrounded by a quadrangular guard ring 41 doped with P + type impurities, and the guard ring 21 doped with P + type impurities is a quadrangular band formed outside thereof. It is surrounded by a guard ring 42 doped with an N + type impurity in shape, and the guard ring 42 doped with an N + type impurity is also contained in an N well 44.

이어서, 셀 어레이 영역 등에서 소자 구조 형성이 이루어지고 1층 이상의 금속 배선 형성이 이루어진 후 층위를 달리하여 반도체 장치의 주변부에 패드(50)가 형성된다. 이때 패드(50)는 위쪽에서 볼 때 ESD 구조(40)가 형성된 영역과 일부가 겹치도록 형성된다. 즉, 패드(50)의 일 변 부분이 ESD 구조(40)에서 N 웰(44)과 4개의 변을 가진 4각 띠모양으로 형성된 N+ 불순물로 도핑된 가드 링(42)의 한 변을 덮도록 이루어진다.Subsequently, the device structure is formed in the cell array region or the like, and after forming one or more metal wires, the pad 50 is formed at the periphery of the semiconductor device at different layers. In this case, the pad 50 is formed to overlap a portion of the region where the ESD structure 40 is formed when viewed from above. That is, one side portion of the pad 50 covers the one side of the guard ring 42 doped with N + impurities formed in a four-sided quadrangular strip having an N well 44 and four sides in the ESD structure 40. Is done.

본 실시예에서 패드 일부와 ESD 구조를 이루는 영역의 일부가 겹치도록 형성되므로 종래에 비해 겹쳐지는 영역 이상으로 패드 및 ESD 구조 형성을 위해 소모되던 영역의 면적을 줄일 수 있다.In the present exemplary embodiment, since a part of the pad and a part of the area constituting the ESD structure overlap each other, the area of the pad and the area consumed for forming the ESD structure can be reduced more than the area overlapping with the related art.

도4는 본 발명의 다른 실시예를 나타낸 것이다. 다른 실시예에 따르면, ESD 구조(40)를 이루는 영역 전부가 패드(50) 아래쪽에 형성되어 있다. 패드(50)와 ESD 구조(40)가 층위를 달리하면서 형성되고, 이들 요소 사이에는 반도체 장치의 집적화에 따른 다층 배선화의 영향으로 충분한 층간 절연막, 기타 버퍼막들이 형성되어 있으므로 프루브를 이용하는 조사 단계에서도 패드(50)와 ESD 구조(40) 혹은 다른 주변 회로와의 의도되지 않는 연결, 단락은 회피될 수 있다.4 shows another embodiment of the present invention. According to another embodiment, all of the regions constituting the ESD structure 40 are formed below the pad 50. The pad 50 and the ESD structure 40 are formed with different layers, and sufficient interlayer insulating film and other buffer films are formed between the elements due to the multilayer wiring due to the integration of semiconductor devices, so that even in the irradiation step using the probe Unintended connections and shorts between the pad 50 and the ESD structure 40 or other peripheral circuitry can be avoided.

본 발명에 따르면, 주변 회로의 안전을 위해 형성되는 ESD 구조를 주변 회로와 패드 사이에 가지도록 형성되는 반도체 장치에서 상대적으로 다른 부분에 비해 많은 면적을 차지하는 패드와 ESD 구조를 적어도 일부에서 겹치도록 형성함으로써 반도체 장치의 형성에 필요한 소요 면적을 줄일 수 있고, 다른 측면에서 형성되는 반도체 장치의 칩 크기를 줄일 수 있게 된다.According to the present invention, in the semiconductor device formed to have an ESD structure formed between the peripheral circuit and the pad, which is formed for the safety of the peripheral circuit, the pad and the ESD structure, which occupy a larger area than other portions, are formed to overlap at least a part of the semiconductor device. As a result, the required area required for forming the semiconductor device can be reduced, and the chip size of the semiconductor device formed on the other side can be reduced.

Claims (3)

가드 링(guard ring)을 포함하는 ESD(ElectroStatic Discharge) 구조가 형성된 영역과 패드가 위에서 볼 때 적어도 일부에서 겹치도록 형성되는 것을 특징으로 하는 반도체 장치.A semiconductor device, characterized in that an area in which an electrostatic discharge (ESD) structure including a guard ring is formed and a pad overlap at least partially when viewed from above. 제 1 항에 있어서,The method of claim 1, 상기 패드가 상기 ESD 구조의 전 영역을 커버하는 것을 특징으로 하는 반도체 장치.And the pad covers the entire area of the ESD structure. 제 1 항에 있어서,The method of claim 1, 상기 ESD 구조는, 위에서 볼 때, 중앙부의 ESD 장치(20), 상기 EDS 장치를 둘러싸는 P+형 불순물로 도핑된 가드 링(21), 상기 P+형 불순물로 도핑된 가드 링(21)과 이격된 상태로 상기 P+형 불순물로 도핑된 가드 링(21)을 둘러싸는 N+형 불순물로 도핑된 가드 링(22), 상기 N+형 불순물로 도핑된 가드 링(22)을 내포하는 N웰(nwell:23)을 구비하여 이루어지며,The ESD structure is spaced apart from the ESD device 20 in the center, the guard ring 21 doped with P + type impurities surrounding the EDS device, and the guard ring 21 doped with the P + type impurities. N well containing a guard ring 22 doped with N + -type impurities and a guard ring 22 doped with N + -type impurities in a state surrounding the guard ring 21 doped with the P + -type impurities. ), 상기 패드의 일부가 상기 ESD 구조의 N웰(23) 및 상기 N+ 불순물로 도핑된 가드 링(22)의 일 부분과 겹치도록 형성됨을 특징으로 하는 반도체 장치.And a portion of the pad overlaps with a portion of the N well (23) of the ESD structure and a portion of the guard ring (22) doped with the N + impurity.
KR1020020000608A 2002-01-05 2002-01-05 Semiconductor device having layout for reducing chip size KR20030060012A (en)

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