JPH10125910A - Semiconductor integrated circuit and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize electrostatic breakdown preventive means, without requiring the area for protective elements by providing a protective insulation film over gate electrodes and protective conductive film connected to the ground potential in constitution of a semiconductor integrated circuit. SOLUTION: On the over layer of gate electrodes 4 a protective insulation film 7 is formed which is made thin to lower the electric resistance more than a lower gate oxide film 3. A protective conductive film 8 connected to the ground potential is formed. Even if a high voltage is applied to an input terminal IN connected to the gate electrode 4 due to the electrostatic charges, it is guided to the protective film having the lower electric resistance than that of the gate oxide film 3 and discharged through the conductive film 8. The protective insulation and conductive films 7, 8 are formed so as to cover the gate electrodes 4, thereby discharging from the corners of the gate electrodes 4 to which the electric field is concentrated. Thus the electrostatic breakdown can be surely avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor integrated circuit in which a transistor is formed by stacking an oxide film or a conductive film on a semiconductor substrate, and a method of manufacturing the same. 2. Description of the Related Art In recent years, as semiconductor integrated circuits have become finer in pattern with higher integration, the withstand voltage of each layer constituting the circuit has been reduced. The gate oxide film is easily destroyed by external static electricity, which hinders normal operation of the memory and the logic circuit.

Therefore, in a semiconductor integrated circuit, protection means for preventing destruction by high voltage such as static electricity is required.

[0003]

2. Description of the Related Art FIG. 9 is a diagram for explaining a semiconductor integrated circuit having a conventional protection means constituting a MOS transistor, which will be described below. FIG. 9A is a circuit diagram of a conventional semiconductor integrated circuit having an NMOS transistor 77 whose source and drain are connected to an internal circuit (not shown).
Is connected to an input terminal A.

In such a circuit, when a high voltage due to static electricity or the like is applied to the input terminal A, the gate (gate oxide film) of the NMOS transistor 77 is damaged by the high voltage. Therefore, the conventional semiconductor integrated circuit has protection transistors 78 and 7 as shown in FIG.
9 are provided.

FIG. 9B is a cross-sectional view showing a specific structure of the above-described circuit. An NMOS transistor 77 is formed on a P-type semiconductor substrate 71 via a gate oxide film 73 and is connected to an input terminal A. Gate electrode 74 and gate electrode 7
4 has a source electrode 75 and a drain electrode 76 formed on both sides of the N-type diffusion layer 72. This N
On both sides of the MOS transistor 77, the gate and source are short-circuited and connected to the power supply Vcc, and the drain is
NMO for protection connected to the gate of transistor 77
An S transistor 78 and a PMOS transistor 79 whose gate and drain are short-circuited and connected to the ground point GND, and whose source is connected to the gate of the NMOS transistor 77.
Are formed.

In the conventional semiconductor integrated circuit shown in FIGS. 9A and 9B, for example, the protection NMOS transistor 78 and the PMOS transistor 79 have a forward threshold voltage of 0.6 V and a reverse breakdown voltage. Voltage -30V, power supply V
Let cc be 5V. In the normal state, the NMOS transistor 7
7 is about 0.6 V, the protection NMOS transistor 78 and the PMOS transistor 7 are protected.
9 does not work.

On the other hand, when a high voltage is applied to the input terminal A due to static electricity or the like, the protection NMOS transistor 78 and the PMOS transistor 79 operate to release excess charge, thereby causing the gate oxide film 73 of the NMOS transistor 77 to escape. To prevent damage. That is, when the input voltage is 5
When the voltage becomes ３０30 V, the protection NMOS transistor operates to discharge a positive charge to the power supply Vcc side, and
If this is the case, the NMOS transistor 78 and P
Both MOS transistors 79 operate to discharge positive charges to the power supply Vcc side and the ground point GND side, respectively.

As described above, when a high voltage is applied to the input terminal A, the protection transistor operates to prevent the high voltage from being directly applied to the NMOS transistor 77, and to prevent the NMOS transistor 77 from receiving a high voltage. The destruction of the oxide film 73 is prevented. Even when a negative voltage is applied, the protection transistors operate in the same manner, and the sign charge is
It can escape to cc and the ground point GND.

[0009]

In the conventional semiconductor integrated circuit described above, in addition to the elements required for normal operation,
A protection element for preventing electrostatic destruction is required.
As shown in the example in FIG.
In addition, an area for forming the PMOS transistor 79 is required, which hinders miniaturization.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems and to obtain a small-sized semiconductor device by realizing a means for preventing electrostatic destruction which does not particularly require an area for a protection element.

[0011]

According to the present invention, there is provided a semiconductor device, comprising: a gate electrode formed on a semiconductor substrate via a gate oxide film; and a gate electrode formed in a region different from the gate electrode. In a semiconductor integrated circuit having a source electrode 5 and a drain electrode 6 to form a MOS transistor, a protective insulating film formed on the gate electrode 4 and having a lower electric resistance than the gate oxide film 3 7. A protection conductive film 8 formed on the insulating film 7 and connected to the ground potential.

According to the semiconductor integrated circuit of the present invention, since a gate oxide film can be protected from a high voltage without providing a protection element, a small circuit which does not require a space for the protection element can be realized. Can be.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a sectional view of an NMOS transistor for explaining a first embodiment of the present invention. The NMOS transistor of this embodiment is made of P
A gate electrode 4 is formed in a predetermined region of a semiconductor substrate 1 with a gate oxide film 3 interposed therebetween. A source electrode 5 and a drain electrode 6 are formed on the N-type diffusion layer 2 on both sides of the gate electrode 4. It is constituted by forming.

On the upper layer of the gate electrode 4, a protective insulating film 7 formed thinner to lower the electric resistance than the lower gate oxide film 3, and a protective conductive film 8 connected to the ground potential Is formed. In the semiconductor integrated circuit of the present embodiment, it is only necessary to add a step of forming the protective insulating film 7 and the protective conductive film 8.
It can be manufactured by ordinary wafer process technology such as thin film formation and lithography.

Further, an oxide film is formed in a peripheral region where the source electrode 5 and the drain electrode 6 are not formed as shown by oblique lines. In such a semiconductor integrated circuit, even if a high voltage due to static electricity is applied to the input terminal IN connected to the gate electrode 4, the high voltage is applied to the protective insulating film 7 having a lower electric resistance than the gate oxide film 3. Then, it is discharged through the protective conductive film 8.

Therefore, it is possible to prevent the gate oxide film 3 from being electrostatically damaged without providing a protection element. In the present embodiment, the insulating film is provided on the gate electrode 4. However, it is also possible to use a non-charged film in which electric charges easily move, and this is the same in the embodiments described below.

Further, the protective insulating film 7 and the protective conductive film 8
Is formed so as to cover the gate electrode 4 to generate a discharge from the corner of the gate electrode 4 where the electric field is concentrated,
Electrostatic breakdown can be more reliably prevented. FIG.
FIG. 4 is a schematic cross-sectional view of an NMOS transistor for explaining a second embodiment of the present invention, which has the same basic configuration as the first embodiment, but is characterized by the shape of the gate electrode 14.

That is, the structure of the source electrode 15 and the drain electrode 16 on the P-type semiconductor substrate 11, the gate oxide film 13, and the N-type diffusion layer 12 is the same as that of the first embodiment, and the insulating protection for the gate electrode 14 is performed. It is characterized in that a part of the surface in contact with the film 17 is shaped to protrude. This utilizes the property that an electric field is concentrated on the protruding portion. When a high voltage due to static electricity or the like is applied to the gate electrode 14 via the input terminal IN, this voltage is reduced to the lower gate oxide film. 1
It is easier to be guided to the protective insulating film 17 side than 3.

According to this embodiment, when a high voltage due to static electricity or the like is applied to the gate electrode 14, the high voltage is applied to the gate electrode 1
4 is guided to the protective insulating film 17 side through the protruding portion 4 and is discharged through the protective conductive film 18, so that the gate oxide film 13 in the lower layer can be reliably prevented from being broken. FIG.
FIG. 9 is a cross-sectional view for explaining a specific manufacturing process for forming a gate electrode having a protrusion.

First, as shown in FIG. 3A, a portion of the semiconductor substrate 11 where the gate oxide film 13 made of silicon oxide is formed is formed by using a first mask 19a having a large window. One electrode layer 14a is formed. The electrode layer 14a is doped polysilicon in which polysilicon is doped with ions such as boron or phosphorus, and is formed with a thickness of about several μm by a photolithography technique using a negative photoresist.

Thereafter, as shown in FIG. 3B, a second mask 19b having a smaller window than the first mask is used.
The second electrode layer 14b is formed on the first electrode layer 14a. The material and the thickness are the same as those of the first electrode layer 14a.
Then, as shown in FIG. 3C, the second electrode layer 14b is formed using a third mask 19c having a smaller window.
The third electrode layer 14c is formed thereon. Like the second electrode layer 14b, the material and the film thickness are the same as those of the first electrode 14a.

On the gate electrode thus formed, FIG.
As shown in (d), several hundreds of the protective insulating film 17 made of polysilicon are covered. As described above, by sequentially providing the electrode layers having patterns having different widths, the edge portion of each layer becomes a protruding portion, and the electric field can be concentrated, and as shown in FIG. When 17 is formed, a thin portion 17a is formed at this edge portion, so that discharge is easily generated from this portion.

In the first and second embodiments, the MOS
Although the present invention has been described with reference to a semiconductor integrated circuit forming a transistor, the present invention is not limited to this, and has the same effect in a semiconductor integrated circuit such as a bipolar transistor. FIG. 4 is a sectional view of an NMOS transistor for explaining a third embodiment of the present invention.

In this embodiment, a gate electrode 24 is formed in a predetermined region of a P-type semiconductor substrate 21 made of silicon via a gate oxide film 23. N-type diffusion layers 22 on both sides of the gate electrode 24 are formed. Then, a source electrode 25 and a drain electrode 26 are formed. A protective conductor 28 that is grounded is formed inside the gate oxide film 23 without being in contact with the gate electrode 24, thereby enabling discharge when a high voltage is applied to the gate electrode 24.

The protective conductor 28 of this embodiment is formed by first forming a thin oxide film and then patterning a metal material on this oxide film, and then forming an oxide film to form a gate oxide. It is in a state of being buried in the film 23. In addition, the gate electrode 24 has a shape protruding toward the protective conductor 28 so that a high voltage is reliably discharged through the protective conductive film 28.

According to the present embodiment, since the protective conductor 28 is buried in a part of the gate oxide film 23, a high voltage is applied through the part of the gate oxide film 23 Since the discharge is conducted by the film 28, the protective insulating film formed in the first and second embodiments can be eliminated, and the thickness can be reduced. FIG. 5 is a cross-sectional view for explaining a manufacturing process of the gate oxide film 23 in the present embodiment.

First, as shown in FIG. 5A, an oxide film 23a thicker than desired is formed so as to bury the protective conductor 28. Next, as shown in FIG. 5B, after covering a first etching mask 29a having a window of a predetermined size, the oxide film 23a is etched to form an oxide film 23b.

Further, as shown in FIG. 5 (c), after covering the second etching mask 29b having a window portion smaller than the first etching mask 29a, the oxide film 23b is etched to form the oxide film 23c. Form. Then, as shown in FIG. 5D, the second etching mask 29
Third etching mask 29 having a window smaller than b
After covering with c, the oxide film 23c is etched to form a desired gate oxide film 23 protruding toward the protective conductive film 28.

As described above, by sequentially performing etching with a plurality of etching masks having different windows, it is possible to form the oxide film 23 having a recess at the center.
If a gate electrode is stacked thereon, it becomes possible to form a protruding shape. In addition, each etching mask has a different width of the window portion also in the direction of the paper surface of the drawing.
The protruding shape can be made smoother as the number of etchings is increased.

FIG. 6 is a perspective view for explaining a fourth embodiment of the present invention. In this embodiment, as in the third embodiment described above, a gate electrode 34 is formed in a predetermined region of a P-type semiconductor substrate 31 made of silicon via a gate oxide film 33, and N electrodes on both sides of the gate electrode 34 are formed. A source electrode 35 and a drain electrode 36 are formed on the mold diffusion layer 32.

A pair of protective conductors 38, each of which is grounded, are formed inside the gate oxide film 33 to enable discharge when a high voltage is applied to the gate electrode 34. The protective conductor 38 of the present embodiment is also formed by the same method as in the third embodiment, and is buried in the gate oxide film 33.

The gate electrode 34 is formed so as to protrude toward the pair of protective conductors 38 so that a high voltage is reliably discharged through the protective conductive film 38. According to the present embodiment, since a pair of protective conductors 38 are buried in the gate insulating film 33, a high voltage can be reliably discharged. The thickness can be reduced by eliminating the need for an insulating film.

FIG. 7 is a perspective view for explaining a fifth embodiment of the present invention, in which a high voltage is discharged through a predetermined path in a plane direction. FIG. 7A shows a basic configuration of the first embodiment of the present invention described with reference to FIG. 1, and shows an example of the positional relationship in the plane direction. That is,
A gate electrode 44 is provided on a semiconductor substrate 41 via a gate oxide film 43, and has a source electrode 45 and a drain electrode 46 on both sides thereof.

Each of the electrodes leads a conductor pattern made of aluminum or the like in a predetermined direction. A wiring pattern 48 is connected to the conductor pattern of the gate electrode 44 via a protective insulating film 47. Wiring pattern 4
Reference numeral 8 (not shown) is grounded, and when a high voltage due to static electricity or the like is to be applied to the gate electrode 44 as shown by an arrow, the protection insulating film 47 and the wiring pattern 48 located in front of the gate electrode 44. Discharged. Therefore, destruction of the gate oxide film 43 under the gate electrode 44 is prevented.

Although FIG. 7A has been described by taking a MOS transistor as an example, a bipolar transistor may have a similar configuration. FIG. 7B shows an example in which an electrostatic breakdown preventing means is provided near an electrode pad which is a signal input portion. In this embodiment, the semiconductor element 5
A protective insulating film 53 and a grounded protective conductive film 54 are formed so as to be adjacent to the peripheral portions of the plurality of electrode pads 52 formed on one surface. The electrode pad 52 is an input portion of a signal to each electrode portion, and a high voltage due to static electricity or the like is input from the electrode pad 52.

Therefore, by providing the protective insulating film 53 and the protective conductive film 54 around the electrode pad 52 as in this embodiment, it becomes possible to immediately discharge the high voltage input to the electrode pad 52. In addition, destruction of the internal gate oxide film can be prevented. Further, the electrode pad 52 of the present embodiment has a shape protruding toward the protective insulating film 53, so that the electric charge is concentrated on the portion, so that the high-voltage discharge is performed more reliably.

The semiconductor integrated circuit of the present invention described above
Discharge is enabled by grounding via a lead terminal from a protective conductive film in a state of being mounted on a printed board.
However, when the semiconductor device is transported by itself, grounding becomes difficult. Therefore, an example of a grounding method when the semiconductor device is transported alone using a container will be described below.

FIG. 8 is a diagram for explaining an example of the grounding method in the semiconductor integrated circuit of the present invention. FIG.
1A and 1B show an external perspective view and a cross-sectional view of a semiconductor device 61 incorporating a semiconductor integrated circuit of the present invention. The semiconductor device 64 is sealed in a package 65, and the semiconductor device 64 is electrically connected to the semiconductor device 64. It has a lead terminal 63 which is electrically connected and led to the outside, and a grounding conductor 62 integrally formed with the lead terminal 63 and exposed on the surface of the package 65.

FIG. 8C is a cross-sectional view when the semiconductor device 61 is accommodated in a container 66.
Since the grounding conductor 62 exposed on the surface of the first package 65 is configured to contact the inner surface of the container 66, if the container 66 is grounded, even if a high voltage due to static electricity is applied, it is discharged. Destruction of the internal circuit can be prevented.

[0040]

According to the semiconductor integrated circuit of the present invention, a high voltage generated and applied by static electricity or the like is discharged through the protective insulating film and the conductive film provided on the electrode or adjacent to the electrode. Therefore, it is possible to realize a small-sized circuit with protection means which does not particularly require an area for a protection element.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining a first embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining a second embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a manufacturing process according to a second embodiment of the present invention.

FIG. 4 is a sectional view for explaining a third embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating a manufacturing process according to a third embodiment of the present invention.

FIG. 6 is a sectional view for explaining a fourth embodiment of the present invention.

FIG. 7 is a perspective view for explaining a fifth embodiment of the present invention.

FIG. 8 is a diagram for explaining an example of grounding in the semiconductor integrated circuit of the present invention.

FIG. 9 is a diagram illustrating a conventional semiconductor integrated circuit.

Claims (7)

[Claims] An N layer is provided by providing an impurity layer in a predetermined region.
A semiconductor integrated circuit that forms a transistor by patterning an oxide film and a conductive film on a semiconductor substrate separated into a P-type region and a P-type region; A semiconductor integrated circuit, comprising: a non-charged film; and a protective conductor which is in contact with the protective non-charged film and has a discharging means. 2. The semiconductor integrated circuit according to claim 1, wherein a portion of the conductive film to which an input signal is supplied has a protruding portion in which an electric field is concentrated at a contact portion with the non-conductive film for protection. . 3. The semiconductor integrated circuit according to claim 1, wherein the protruding portion of the conductive film is formed by repeating a photolithography process using different masks, thereby sequentially stacking a pattern having a gradually decreasing width. Manufacturing method. 4. A portion of the conductive film to which an input signal is supplied is a gate electrode formed on a gate oxide film, and has a source electrode and a drain electrode formed on an impurity layer on both sides thereof. 2. The MOS transistor according to claim 1, wherein said gate oxide film also functions as a protection non-charging film, and a protection conductor including a discharging means is buried in said gate oxide film. Semiconductor integrated circuit. 5. The semiconductor integrated circuit according to claim 3, wherein said gate electrode has a shape in which a contact portion with said gate oxide film protrudes toward said protective conductor. 6. The protruding gate electrode according to claim 5, wherein the lower gate oxide film is formed in a step-like shape descending toward the center by repeatedly performing an etching process using different etching masks. Forming a conductive film on the gate oxide film by laminating the conductive film to a predetermined thickness. 7. The discharge means of the protective conductor is configured to ground a ground conductor formed integrally with a lead terminal electrically connected to the protective conductor. Item 2. The semiconductor integrated circuit according to item 1.