KR20030059423A - A planalization method of semiconductor device - Google Patents

Abstract

PURPOSE: A method for planarizing a semiconductor device is provided to be capable of minimizing electrical resistance and improving uniformity of profile without using additional processes. CONSTITUTION: A lower structure having a desired topology between an insulating layer and a conductive layer is formed on a semiconductor substrate. The lower structure is planarized by ACE(Advanced Chemical Etching) using basic solutions. At the time, polysilicon is used as the conductive layer. The basic solution is one selected from group consisting of KOH, NaOH, LiOH, RbOH, CsOH, FrOH, BeOH, MgOH, CaOH, SrOH, NH4OH, and TMAH.

Description

A planarization method of a semiconductor device {A PLANALIZATION METHOD OF SEMICONDUCTOR DEVICE}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a planarization method of a semiconductor device.

As the integration of semiconductor technology increases, the density of patterns increases. As a result, the thickness of the metal layer increases, a multi-layered structure is used, and the pitch also decreases.

As a result, the upper part of the entire structure where one step process is completed during the process of the device causes bending such as Hill and Valley, resulting in deterioration of step coverage and subsequent process progress. The process margin is reduced, such as difficulty in pattern formation, and the probability of device defects is also increased.

Planarization refers to the degree of flatness of a vertical structure of a structure, and the planarization technology is one of the important elements in the semiconductor technology because of the problems caused by the above-described step coverage degradation.

The planarization technology is classified into three types, dry etching, chemical mechanical polishing (CMP), and advanced chemical etching (ACE). Take a look.

end. Planarization by CMP

A) the lower layer, in particular, as the mechanical polishing properties of the planarization process mechanism are key. Erosion of the oxide layer and dishing of polysilicon and metal lines, which are fine wires, occur.

B) The stress induced damage of the lower layer of the oxide film and the like and the polysilicon and the metal line adversely affect the device characteristics.

C) Abrasives, slurries, and polyurethane fiber pads of the process material are used to contaminate metals and organics on the substrate surface layer.

D) Equipment maintenance costs are high due to the use of abrasives, slurries and polyurethane fiber pads.

I. Flattening by dry front etching

A) The selectivity of the lower layer, in particular, the oxide series is high, but it is difficult to control the end point (hereinafter referred to as EOP), so that a seam occurs when a polysilicon plug is formed.

B) During dry etching, a small residue is left on the lower oxide film, which adversely affects device characteristics.

All. Planarization by ACE

ACE is a polishing using a hydrodynamic force of a high-speed rotating wet solution. In the conventional case, an acidic solution is mainly used. The flattening process by ACE will be described with reference to the accompanying drawings. .

FIG. 1 (a) shows an exploded perspective view of a wafer carrier (model name) SEZ201 (Bernoulli Chuck-Edge Ring N2 Blow) used in the ACE process, and FIG. 1 (b) shows a partial photograph.

Referring to FIG. 1A, the wafer carrier includes a media supply line 100 for supplying a wet solution such as a chemical, a chamber 110 in which a process is performed, a substrate 120, and a substrate 120. ) And a recovery line (Media return line) 140 for recovering the used wet solution.

The planarization process using ACE uses the principle that the wafer carrier is rotated at a high speed of 2500rpm while holding the wafer (Hold) and uniformly etched while the high pressure chemical etching solution is injected through the nozzle.

On the other hand, conventionally, the acid solution was used as the wet solution as described above, Figure 2 is a flow chart showing the planarization process sequence using the conventional ACE process described above.

Referring to FIG. 2, an acidic solution having a room temperature of about 25 ° C. is sprayed through a high speed nozzle to chemically etch in the form of a high pressure spray, maintaining high water pressure on a wafer, and rotating at high speed.

Using the acid solution described above, for example, the etching mechanism of polysilicon used as a plug forming material will be described.

First, looking at the composition of the acidic solution, hydrofluoric acid (HF), nitric acid (HNO ₃ ) and acetic acid (CH ₃ COOH) are each mixed in a volume ratio of 15: 250: 125: 20, the temperature is room temperature and the etching rate as described above Represents 1800 dl / min or less as a plate etch rate for polysilicon doped with phosphorus (P).

In addition, the viscosity is similar to that of water, there is no orientation for silicon crystals during etching, but the dependence on the doping concentration is large, the etching rate is different depending on the doping concentration, and the etching rate is higher than that of undoped phosphorus (P) Appears quickly.

Here, nitric acid serves to promote the oxidation of silicon, HF serves to remove the oxide film, acetic acid serves to mitigate the oxidation, thereby improving the etching uniformity, Scheme 1 is the acid solution described above The reaction mechanism of is shown.

Figure 3 shows the mass flow mechanism during the flat process by the ACE process.

Where Q is the flow rate, ω is the angular frequency, η is the viscosity, ρ is the density, r is the radius, and H (r) is the thickness. Represent each.

As shown in FIG. 3, when the flow rate of the etching solution increases above the threshold value, a vortex is formed inside the contact hole, thereby further reducing the flow of the etching solution and reaction by-products. Accordingly, the upper surface of the substrate is etched due to the rapid mechanical force and mass flow due to the hydraulic pressure, but the material flow disappears in the contact hole, thereby preventing etching. The anisotropic etching characteristic may be used to planarize the substrate.

4A to 4B are cross-sectional views illustrating a polysilicon plug forming process using the ACE planarization process according to the prior art.

First, as shown in FIG. 4A, a field insulating film 11 is locally formed on a substrate 10 on which various elements for forming a semiconductor device are formed. Then, the gate electrode 12, the hard mask 13, and the spacer ( 14), an interlayer insulating film 15 is formed over the entire structure.

Next, a landing plug contact (hereinafter referred to as LPC) process is performed to form contact holes (not shown) that expose the surface of the substrate 10 between the gate electrodes 12. Subsequently, the plug polysilicon film 17 is formed to sufficiently fill the contact hole. Here, the polysilicon film 17 uses polysilicon doped with a high concentration of phosphorus (P).

On the other hand, although there are differences depending on the contact hole difference, when the polysilicon film 17 is deposited by using a chemical vapor deposition (CVD) process, the concentration of phosphorus (P) in the silicon surface and inside is different. The occurrence of seam in the center portion of the contact as shown in the 'X' is inevitable, and the concentration of phosphorus (P) is distributed to the lower portion of the contact.

Next, as shown in FIG. 4B, the planarization process is performed until the surface of the interlayer insulating film 15 is exposed through the ACE process using the above-described acidic solution, thereby forming the interlayer insulating film 15 and the flattened plug 17 '. Is formed and is also electrically isolated from the neighboring plug 17 '.

Specifically, etching using the acid solution described above is preceded by oxidation of silicon by a strong oxidizing agent such as potassium permanganate. In particular, the oxidation of nitric acid, which is mainly used, generates by-products such as NO, NO ₂ or HNO ₃ during the reaction process, and thus rapidly proceeds by auto catalysis when the reaction starts.

When silicon is changed to silicon oxide by the oxidizing agent described above, dissolution reaction is performed by hydrofluoric acid, a strong oxidizing agent, and none of the currently known materials can replace hydrofluoric acid.

Therefore, etching of silicon is possible only in the region where nitric acid and hydrofluoric acid are present at the same time, and the etching characteristics of silicon are monocrystalline silicon although there are some differences depending on the composition of hydrofluoric acid, nitric acid and dilute acetic acid (H ₂ O + CH ₃ COOH) solution. The etching rate according to the crystal direction of is the same, and tends to increase with increasing temperature. However, the etching rate of silicon tends to increase in the order of doping, undoping, and phosphorus (P) of boron (B) according to the doping concentration.

Therefore, as shown in FIG. 4B, the doping concentration of phosphorus (P) is high in the surface of the substrate 10 and in the shim (X) region, and thus the etching speed in this region is faster than that in other regions, resulting in a deeper shim such as 'Y'. This is even worse if there is a void inside the contact.

5A to 5B illustrate a process in which a highly doped polysilicon film and an undoped polysilicon are laminated for a plug, and descriptions of the same processes and symbols as those of FIGS. 4A to 4B will be omitted.

That is, as illustrated in FIG. 5A, an undoped polysilicon film 18 is deposited on the polysilicon film 17 having a high concentration, and then a planarization process is performed by the ACE process as shown in FIG. 5B.

In this case, the problem of deepening the seam can be solved according to the difference in doping concentration, but the problem of increasing the resistance by the undoped polysilicon film 18 occurs.

6 is a cross-sectional profile picture (FIG. 6 (a)) inside the contact before the ACE process according to the ACE process using the acid solution described above, and a profile picture (FIG. 6 (b)) after the ACE process using a double polysilicon film and DAILY poly Profile pictures (FIG. 6 (c)) after the ACE process using a silicon film are shown, respectively.

Therefore, the problem of the ACE process using the acid solution described above is as follows.

A) The selectivity with respect to the oxide region of the lower portion is high, but the etching rate according to the doping concentration is significantly different, deepening the core inside the polyplug.

B) When the polysilicon is deposited in two stages due to the difference in etching rate due to the doping concentration, electrical property deterioration occurs due to the increase in resistance, and the process becomes complicated.

The present invention proposed to solve the problems of the prior art, it is possible to obtain a constant etching rate irrespective of the doping concentration, and to minimize the electrical resistance without the addition of a special process planarization method of a semiconductor device having a uniform profile The purpose is to provide.

1 is an exploded perspective view and a partial photograph of a wafer carrier used in the ACE process,

2 is a flowchart showing a planarization process sequence using a conventional ACE process,

3 is a view showing a mass flow mechanism during a flat process by the ACE process,

4A to 4B are cross-sectional views illustrating a polysilicon plug forming process using the ACE planarization process according to the prior art;

5A to 5B are cross-sectional views illustrating a process in which a highly doped polysilicon film and an undoped polysilicon are laminated for a plug;

Figure 6 is a photograph showing a cross-sectional profile before and after the ACE process according to the ACE process using an acid solution,

7 is a flowchart showing a planarization process sequence using the ACE process of the present invention,

8A to 8C are cross-sectional views illustrating a polysilicon plug forming process to which the ACE process using the basic solution of the present invention is applied;

Figure 9 is a photograph comparing the profile of the etching cross-section according to the vertical and inclined etching when performing a planarization process of polysilicon plug without high-speed rotation at high speed at room temperature using a basic solution and an acidic solution.

* Explanation of symbols for the main parts of the drawings

20: substrate 21: field insulating film

22: gate electrode 23: hard mask

24 spacer 25 interlayer insulating film

27: plug

In order to solve the above problems, the present invention includes the steps of forming a lower structure of the insulating film and the conductive film having a predetermined step; And planarizing the substructure using an Advanced Chemical Etching (ACE) process using a basic solution.

Preferably, the forming of the substructure of the present invention may include forming an open portion to selectively expose the surface of the conductive layer by selectively etching the insulating film on the conductive layer; And forming the conductive film to sufficiently fill the open part.

The conductive film is characterized in that it comprises polysilicon,

The basic solution is any one selected from the group consisting of potassium hydroxide, sodium hydroxide, lithium hydroxide, rubidium hydroxide, cesium hydroxide, francium hydroxide, beryllium hydroxide, magnesium hydroxide, calcium hydroxide, strontium hydroxide, rubidium hydroxide, radium hydroxide, ammonium hydroxide and TMAH It is characterized in that one is diluted in the ratio of 1wt% to 50wt% in water,

It characterized in that for maintaining the basic solution at a temperature of -20 ℃ to 100 ℃ in the step of flattening the lower structure,

It characterized in that it is carried out while maintaining the rotational speed of 100rpm to 5000rpm in the step of flattening the lower structure.

In the present invention, by using a basic solution as an etching solution in the planarization process by the ACE process, it is possible to obtain a constant etching rate regardless of the doping concentration, it is possible to omit the additional process and improve the film flatness and electrical properties of the device It is a technical feature to make.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can more easily implement the present invention.

7 is a flowchart showing a planarization process sequence using the ACE process of the present invention.

Referring to FIG. 7, a basic solution having a high temperature of 80 ° C. is sprayed through a high speed nozzle to chemically etch in the form of a high pressure spray, maintaining high water pressure on a wafer, and rotating at high speed.

The etching mechanism of polysilicon used as, for example, a plug forming material will be described using the above-described basic solution.

First, looking at the composition of the basic solution, the basic solution uses potassium hydroxide (KOH) and sodium hydroxide, both of which are diluted to 1 wt% (wt%) to 5wt% of water (H ₂ O), As described above, the temperature is a high temperature and the etching rate is 10000 dl / min or less as the plate etching rate for the polysilicon doped with phosphorus (P).

In addition, the viscosity is higher than the acid, the orientation of the silicon crystals during etching, there is little difference in the etching rate according to the doping concentration. For example, the etching speed of the (100) plane is considerably faster than the (111) plane.

In addition, the etching rate of silicon is affected only by the crystal plane as described above, and Scheme 2 shows the reaction mechanism of each basic solution described above.

8A to 8C are cross-sectional views illustrating a polysilicon plug forming process applying the ACE process using the basic solution of the present invention, which will be described later in detail.

Here, A-A 'represents a cell region, and B-B' represents a peripheral region.

First, as shown in FIG. 8A, a field insulating film 21 is locally formed on a substrate 20 on which various elements for forming a semiconductor device are formed. Then, the gate electrode 22, the hard mask 23, and the spacer are formed. Next, the interlayer insulating film 25 is formed over the entire structure.

Here, the interlayer insulating film 25 may be formed of a silicon oxide film, TEOS (TetraEthyl Ortho Silicate), HDP (High Density Plasma) oxide, PSG (Phospho Silicate Glass), BPSG (Boro Phospho Silicate Glass), O ₃ -TEOS or a silicon oxynitride film can be used alone or in a lamination.

In addition, the gate electrode 22 may also include a gate insulating film (not shown) at an interface in contact with the substrate 20, and the spacer 24 and the gate electrode 22 may be formed in a multilayer structure that is commonly used. Do.

Subsequently, an LPC process is performed to form contact holes 26 exposing the surface of the substrate 20 between the gate electrodes 22.

Next, as shown in FIG. 8B, a plug polysilicon film 27 ′ is formed to sufficiently fill the contact hole 26. Here, the polysilicon film 27 'is made of polysilicon doped with a high concentration of phosphorus (P).

On the other hand, as described above, although there is a difference depending on the size of the contact hole, when the polysilicon film 27 'is deposited using CVD, a difference in the concentration of phosphorus (P) occurs in the silicon surface and the inside, and thus' X' is shown. Likewise, the generation of seam in the center of the contact cannot be avoided, and the concentration of phosphorus (P) is distributed to the lower portion of the seam.

Next, as shown in FIG. 8C, by performing the ACE process until the surface of the interlayer insulating film 25 is exposed using the above-described basic solution, separation between the plugs 27 having the top flattened is performed.

Specifically, since the etching of the basic solution proceeds only with a hydration reaction with KOH or NaOH, for example, Si (OH) ₄ , the higher the wastewater pH, the higher the potential of OH ⁻ ions. On the other hand, since the reaction is faster than the acidic solution at room temperature, the etching rate is high, it is preferable to maintain the above 80 ℃, the etching of silicon is possible only with a solvent without an oxidizing agent.

Therefore, while sprinkling the basic solution at a high temperature, the substrate is rotated at a high speed of 1000 rpm to 5000 rpm to achieve film flattening. At this time, as described above, the basic solution is flattened without deepening the seam in the contact plug 27 because the etching rate does not show a large difference according to the doping concentration of the polysilicon film 27 '.

On the other hand, the basic solution described above, in addition to potassium hydroxide and sodium hydroxide, lithium hydroxide (LiOH), rubidium hydroxide (RbOH), cesium hydroxide (CsOH), francium hydroxide (FrOH), beryllium hydroxide (BeOH), magnesium hydroxide (MgOH), Any one selected from the group consisting of calcium hydroxide (CaOH), strontium hydroxide (SrOH), rubidium hydroxide (RbOH), radium hydroxide (RaOH), ammonium hydroxide (NH ₄ OH) and TMAH can be used.

In addition, the temperature of the basic solution is preferably maintained at about 80 ° C as described above, but can be used within the range of -20 ° C to 100 ° C in consideration of the viscosity of the solution.

FIG. 9 is a photograph comparing the profiles of etched sections according to vertical and inclined etching when the polysilicon plug is planarized without using a basic solution and an acidic solution at high speed at high speed without high-speed rotation. As shown in FIG. In the case of using the solution, it can be seen that the basic urine has improved core characteristics compared to the acidic solution even when the solution is not rotated at a high speed. do.

On the other hand, in the present invention described above ACE process using a basic solution using a polysilicon plug as an example, W, Cu, Al, Au, Ag, Ta, TiN or TaN, etc. can be used in addition to the polysilicon plug, In addition, it can be applied to the metallization process using the damascene or dual damascene process, and can be applied in various ways such as via contact and recess process.

The present invention described above by using the basic solution as an etching solution when the film planarization using the ACE process, it is possible to minimize the core formation according to the concentration of the lower layer, it was found through the embodiment that the additional process can be omitted .

In other words, when the acidic solution is used, the etching rate difference between the phosphorus (P) and the boron (B) is large, and thus the above-described effect may be obtained even when the boron and phosphorus are laminated, but the process is complicated.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

The present invention described above can reduce the device development period and cost by simplifying the film planarization process, minimize the deterioration of electrical characteristics, and ultimately expect excellent effects to improve the yield and price competitiveness of semiconductor devices. Can be.

Claims (6)

In the planarization method of a semiconductor element, Forming a lower structure in which the insulating film and the conductive film have a predetermined step; And Planarizing the substructure using an Advanced Chemical Etching (ACE) process using a basic solution. Planarization method of a semiconductor device comprising a. The method of claim 1, Forming the substructure, Selectively etching the insulating film on the conductive layer to form an open portion exposing the surface of the conductive layer; And Forming the conductive film to sufficiently fill the open portion Flattening method of a semiconductor device comprising a. The method of claim 2, And the conductive film comprises polysilicon. The method of claim 1, The basic solution is any one selected from the group consisting of potassium hydroxide, sodium hydroxide, lithium hydroxide, rubidium hydroxide, cesium hydroxide, francium hydroxide, beryllium hydroxide, magnesium hydroxide, calcium hydroxide, strontium hydroxide, rubidium hydroxide, radium hydroxide, ammonium hydroxide and TMAH Method for flattening a semiconductor device comprising one diluted in water at a rate of 1wt% to 50wt%. The method of claim 1, And in the step of planarizing the lower structure, maintaining the basic solution at a temperature of -20 ° C to 100 ° C. The method of claim 5, The planarization method of the semiconductor device characterized in that the step of maintaining the rotational speed of 100rpm to 5000rpm in the step of planarizing the lower structure.