KR20030058438A - Word line of semiconductor device and method for manufacturing thereof - Google Patents

Abstract

PURPOSE: A word line of a semiconductor device and a fabricating method thereof are provided to increase the length of a channel and a threshold voltage of a transistor by enlarging the width of a word line pattern overlapped on a boundary between an active region and a field region. CONSTITUTION: A word line(40) is arrayed on each upper portion of an active region(20) and a field region(10) of a semiconductor substrate. A T-shaped word line pattern is arranged on a boundary between the active region and the field region of the semiconductor. In the fabricating method, the active region and the field region of the semiconductor are separated each other by forming a shallow trench isolation layer. A gate insulating layer is formed on an upper portion of the semiconductor substrate including the shallow trench isolation layer. The length of a channel is enlarged by forming the T-shaped word line pattern on the boundary between the active region and the field region of the semiconductor.

Description

Word line of semiconductor device and manufacturing method therefor {WORD LINE OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a word line of a semiconductor device and a method of manufacturing the same, which can reduce a hump phenomenon of a transistor generated in a moat of a shallow trench device isolation film.

With the development of semiconductor device manufacturing technology and high integration of devices, research and development on device miniaturization technology is active. Accordingly, reduction of the device isolation film separating the devices has emerged as one of the important items in the technology for miniaturization of semiconductor devices.

Conventional device isolation is mainly based on LOCal Oxidation of Silicon (LOC) technology to selectively grow a thick oxide film on a semiconductor substrate to form a device isolation film, but due to lateral diffusion and bird's beak, it is no longer highly integrated device There was a limit in reducing the width of the device isolation layer in.

Accordingly, in a semiconductor device in which the device design dimension is reduced to submicron or less, a device isolation technology for forming a trench trench in a semiconductor substrate and electrically separating the devices is applied.

The device isolation method of the cell trench is a technology of forming a device isolation film by forming a trench having a constant depth in a semiconductor substrate, gap-filling an oxide film in the trench and polishing the oxide film only in the trench by a chemical mechanical polishing process. to be.

1 is a layout diagram illustrating a transistor arrangement of a general semiconductor device. FIG. 2 is a vertical cross-sectional view taken along line A-B of FIG. 1.

Referring to FIG. 1, the word line 30 according to the related art extends not only to the active region 20 of the semiconductor substrate 1 but also to the device isolation region 10 in which the shallow trench device isolation layer 12 is formed. . In particular, when the word line 30 has a 'T' pattern structure, the '-' pattern is disposed in the device isolation region 10 in the 'T' character, and the '|' pattern is the active region 20 of the semiconductor substrate 1. ) And device isolation region 10.

However, referring to FIG. 2, in the conventional transistor, a hump phenomenon of the word line 30 often occurs at the boundary 24 between the active region 10 and the device isolation region 10 of the semiconductor substrate 1. Done. In the trench etching process for the shallow trench isolation layer, even if the top and bottom corners of the trench are smoothed to improve electrical leakage characteristics, the profile of the trench upper corner is very important because the semiconductor device is actually operating. Therefore, when the gate insulating film is thinly deposited in the upper corner of the trench, an electrical path is generated through this portion, so that two transistors are in parallel, so that the transistor having a low threshold voltage is turned on first, and thus the inflection point at the subthreshold voltage of the transistor is turned on. This is called Hump.

This hump phenomenon mainly lowers the breakdown voltage of the transistor as the electric field is concentrated near the moat of the shallow trench device isolation layer 12, and eventually causes the transistor to turn on below the threshold voltage and cause a current to flow.

An object of the present invention is to increase the channel length by the word line is increased by the width of the pattern overlapping the boundary between the active region and the device isolation region of the semiconductor substrate in order to solve the problems of the prior art as described above The present invention provides a word line of a semiconductor device in which a threshold voltage is increased to reduce a hump phenomenon occurring in the mort of the shallow trench isolation layer.

Another object of the present invention is to place a word line with an increased pattern width at the boundary between an active region and a device isolation region of a semiconductor substrate, thereby increasing the channel length, thereby increasing the threshold voltage of the transistor, and thus, in the mode of the shallow trench isolation layer. The present invention provides a method of manufacturing a word line of a semiconductor device in which a hump phenomenon occurs.

In order to achieve the above object, the present invention provides a word line disposed on an active region and an isolation region of a semiconductor substrate, and the '-' pattern of the 'T'-shaped word line at the boundary between the active region and the isolation region of the semiconductor substrate. This arrangement extends the channel length of the word line.

In order to achieve the above object, another apparatus of the present invention is a word line disposed over an active region and a device isolation region of a semiconductor substrate, the image of the 'engine' shaped word line at the boundary between the active region and the device isolation region of the semiconductor substrate; The / h '-' pattern is arranged to widen the channel length of the word line.

In accordance with another aspect of the present invention, there is provided a word line fabrication method disposed over an active region and an isolation region of a semiconductor substrate, the method comprising: forming a trench trench isolation layer that separates the active region and the isolation region from a semiconductor substrate; Forming a gate insulating film on the semiconductor substrate on which the trench trench isolation layer is formed, and forming a word line such that a '-' pattern is disposed at the boundary between the shallow trench isolation layer and the semiconductor substrate Increase the channel length.

According to another aspect of the present invention, a method of manufacturing a word line disposed on an active region and an isolation region of a semiconductor substrate may include a shallow trench isolation layer that separates the active region and the isolation region from a semiconductor substrate. Forming a gate insulating film on the semiconductor substrate on which the trench trench isolation layer is formed, and 'up' and 'down' patterns of '工' are disposed on the boundary between the trench trench isolation layer and the semiconductor substrate Forming a word line to widen the channel length.

1 is a layout diagram showing a transistor arrangement of a general semiconductor device;

2 is a vertical cross-sectional view cut by the line A-B of FIG.

3 is a layout showing transistor arrangement of a semiconductor device according to an embodiment of the present invention;

4 is a layout diagram illustrating a transistor arrangement of a semiconductor device in accordance with another embodiment of the present invention.

<Description of the code | symbol about the principal part of drawing>

10: device isolation region 20: device isolation region

40: 'T' shaped word line 50: '工' shaped word line

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

3 is a layout diagram illustrating a transistor arrangement of a semiconductor device in accordance with an embodiment of the present invention. Referring to FIG. 3, in an embodiment of the present invention, a word line disposed on an active region 20 and an isolation region 10 of a semiconductor substrate includes an active region 20 and an isolation region of a semiconductor substrate. A '-' pattern of the 'T'-shaped word line 40 is disposed at the boundary of 10 to widen the channel length L' of the word line 40.

The word line 40 of the present invention configured as described above is manufactured by the following process.

A cell trench trench isolation layer is formed on the semiconductor substrate to separate the active region 20 and the device isolation region 10.

A gate insulating film is formed on the semiconductor substrate on which the shallow trench isolation layer is formed.

Then, the word line 40 is formed to extend the channel length L 'so that the'-'pattern is disposed at the boundary between the cell trench isolation layer and the semiconductor substrate.

4 is a layout diagram illustrating a transistor arrangement of a semiconductor device in accordance with another embodiment of the present invention. Referring to FIG. 4, another exemplary embodiment of the present invention is a word line 50 disposed over an active region 20 and an isolation region 10 of a semiconductor substrate, wherein the active region 20 and an element of the semiconductor substrate are formed. The upper and lower '-' patterns 52 and 54 of the 'engine'-shaped word line 50 are respectively disposed at the boundary of the isolation region 10 to widen the channel length L' of the word line 50.

The word line 40 of the present invention configured as described above is manufactured by the following process.

A cell trench trench isolation layer is formed on the semiconductor substrate to separate the active region 20 and the device isolation region 10.

A gate insulating film is formed on the semiconductor substrate on which the shallow trench isolation layer is formed.

Then, the word lines 50 are formed to extend the channel length L 'so that the upper and lower'-'patterns 52 and 54 of the' engineer 'are disposed on the boundary between the trench trench isolation layer and the semiconductor substrate surrounding the trench trench.

Therefore, as described above, the word lines 40 and 50 of one embodiment or the other embodiment of the present invention have a wide width at the boundary between the active region and the isolation region, even if a hump phenomenon occurs in the moat of the shallow trench isolation layer. The patterns of the word lines 40 and 50 lower the resistance per unit area, thereby lowering the electric field to lower the threshold voltage of the transistor.

As described above, according to the present invention, a channel length is increased by a word line having an increased width of a pattern overlapping a boundary between an active region and an isolation region of a semiconductor substrate, thereby increasing the threshold voltage of the transistor, thereby increasing the cell trench trench element. Hump phenomena generated in the mort of the separator are reduced to improve the yield and electrical properties of the semiconductor device.

On the other hand, the present invention is not limited to the above embodiments, but various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims below.

Claims (4)

In the word line disposed above the active region and the device isolation region of the semiconductor substrate, The word line of the semiconductor device, characterized in that the '-' pattern of the 'T'-shaped word line is disposed at the boundary between the active region and the device isolation region of the semiconductor substrate to extend the channel length of the word line. In the word line manufacturing method disposed on the active region and the device isolation region of the semiconductor substrate, Forming a shallow trench isolation layer separating the active region and the isolation region from the semiconductor substrate; Forming a gate insulating layer on the semiconductor substrate on which the shallow trench isolation layer is formed; And And forming a word line such that a '-' pattern is disposed on a boundary between the cell trench isolation layer and the semiconductor substrate around the cell trench, thereby increasing a channel length. In the word line disposed above the active region and the device isolation region of the semiconductor substrate, The word line of the semiconductor device, characterized in that the '-' pattern of the 'engine'-shaped word line is disposed on the boundary between the active region and the device isolation region of the semiconductor substrate to extend the channel length of the word line. In the word line manufacturing method disposed on the active region and the device isolation region of the semiconductor substrate, Forming a shallow trench isolation layer separating the active region and the isolation region from the semiconductor substrate; Forming a gate insulating layer on the semiconductor substrate on which the shallow trench isolation layer is formed; And And extending a channel length by forming a word line such that upper and lower '-' patterns of 'engineer' are disposed on the boundary between the cell trench isolation layer and the semiconductor substrate surrounding the cell trench. Manufacturing method.