KR20030058316A - Apparutus for fixing pulse width - Google Patents

Abstract

PURPOSE: A pulse width fix device is provided to generate the detection signal having a uniform pulse width although the timing of the applied address or the data is not exact. CONSTITUTION: A pulse width fix device includes a detection device(500) for detecting the shift of the address, a first delay block(100), an output block(400), a second delay block(200) and a pulse width control block(300). In the pulse width fix device, the first delay block(100) delays the detection signal by a predetermined time and outputs the delayed detection signal. The second delay block(200) delays the outputs of the first delay block(100) by a predetermined time and outputs the delayed signal. And, the pulse width control block(300) fixes the pulse width of the detection signal applied to the output block(400) as the delay time of the second delay block(200) by fixing the time transmitted to the output block(400) as the delay time of the second delay block(200) with the detection signal outputted from the first delay block(100).

Description

Pulse width fixing device {Apparutus for fixing pulse width}

The present invention relates to a detection device for detecting a transition of an address and data, and more particularly to a pulse width fixing device that makes a constant pulse width of a detection signal generated when detecting a transition of an address and data.

With the development of integrated circuit design technology, microprocessors and memories operating at higher clocks have been developed, and input / output signals of the microprocessors and memories operating at higher clocks require more precise pulse widths.

Therefore, in order for the detection signal generated by the address transition detector and the data transition detector to detect the transition of the address to operate at high speed without malfunction, a detection signal having a constant pulse width must be generated.

1A and a conventional address transition detector are shown.

Referring to FIG. 1A, an address transition detector for detecting a transition of an address composed of a plurality of bits, comprising: an address transition detector 10 for detecting a transition of an address by inputting the plurality of bits; And an output unit 20 for outputting a low level when detecting an address transition.

Hereinafter, the operation of the above-described configuration will be described with reference to FIG. 1A.

First, the address transition detecting unit 10 detects whether or not a transition is made for each address signal, and outputs a high level when the address transitions high or low.

The address transition detection unit 10 has the same number of address transition detection circuits as the number of bits of the address to be applied.

That is, if an address is composed of 16 bits, it has 16 address transition detection circuits.

Subsequently, when any one of the address transition detection circuits detects an address transition, the output unit is driven to output a low level.

Figure 1b illustrates another conventional address transition detector.

FIG. 1B is similar in configuration to that of FIG. 1A, but employs a logic combination circuit 30 instead of the output unit 20, and its operation is the same as that of FIG. 1A.

The logic combination circuit 30 may be configured using a NAND gate or a NOR gate, and generates a low level output signal when a transition occurs in any one of the applied addresses.

Referring to the address shift detector shown in FIG. 1A and the timing diagram of FIG. 2, the following description will be made.

First, when the timing characteristic when only one address AD [0] is applied to the address transition detection circuit 11 is shown, as shown in FIG. 2, when the address AD [0] applied from the low to the high level transitions, It can be seen that a detection signal OUT_1 is generated which transitions from high to low level.

Meanwhile, the detection signal OUT_2 finally generated when the plurality of addresses AD [1] to AD [4] are applied to the address detection circuit shown in FIG. 1A at slightly different timings, respectively, is shown in FIG. As described above, the timing (A) is lowered according to the first address AD [1] transitioned to the high level among the applied addresses AD [1] to AD [4] and the latest address AD [4] is lowered. At the point of transition).

That is, when the timing of the applied address is not correct, the detection signal descends according to the first transitioned address and rises according to the latest transitioned address, so that the pulse width of the detection signal OUT_4 increases, so that precise timing And an integrated circuit requiring a microcontroller or a memory and other address signals that require a pulse width may cause errors in operation.

SUMMARY OF THE INVENTION An object of the present invention is to provide a pulse width fixing device for generating a detection signal having a constant pulse width even if the timing of an address or data applied as proposed to solve the conventional problems as described above is not accurate.

1A and 1B show a conventional address transition detector,

2 is a timing diagram of FIG. 1A and FIG. 1B;

3 is a detailed circuit diagram of one embodiment of a pulse width fixing device according to the present invention;

4 is a timing diagram of a pulse width fixing device according to the present invention;

5 is another timing diagram of the pulse width fixing device according to the present invention;

* Explanation of symbols for the main parts of the drawings

100: first delay unit 200: second delay unit

300: pulse width control unit 400: output unit

The present invention for solving the above problems, the apparatus for fixing the pulse width of the detection signal generated when detecting the transition of the address and data, the first delay means for delaying the detection signal for a predetermined time and outputs; Output means; Second delay means for delaying and outputting the output of the first delay means for a predetermined time; By fixing the time for which the detection signal output from the first delay means is transmitted to the output means to the delay time of the second delay means, the pulse width of the detection signal applied to the output means is adjusted to the second delay means. And pulse width control means for fixing with a delay time.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

Figure 3 is an embodiment in which the pulse width fixing device according to the present invention is applied to the address transition detection device.

Referring to FIG. 3, in the detection apparatus 500 for detecting a transition of an address, and in a device for fixing a pulse width of a detection signal PD generated when detecting a transition of an address and data, the detection signal PD is fixed. Delay unit 100 for delaying a predetermined time and outputting the first delay unit 100, an output unit 400, and a second delay unit 200 for delaying and outputting the output of the first delay unit 100 by a predetermined time d1. And by fixing the time at which the detection signal PD output from the first delay unit 100 to the output unit 400 is delay time d2 of the second delay unit 200. And a pulse width controller 300 which fixes the pulse width of the detection signal PD applied to the output unit 400 to the delay time d2 of the second delay unit 200.

Specifically, the first delay unit 100 may include an inverter 101 for inverting the detection signal PD, a delay unit 102 for delaying the detection signal PD for a predetermined time, and the inverter 321. NMOS 103 and PMOS 104 which respectively respond to the output of the < RTI ID = 0.0 > and < / RTI > Are configured to include,

The pulse width controller 300 may include a first passgate 310 which isolates the output of the first delay unit 100 from the output of the node 1 in response to the output of the second delay unit 200. In response to the output of the second delay unit 200, a current path is formed in the node 1 and the node 2 so that the output unit 400 performs a latching operation. Including the pull-up unit 330 for pulling up the output terminal of the pulse width control unit 300 by the output of the delay unit 200,

The first passgate 310 has one side connected to an output terminal of the first delay unit 100, a gate connected to an output terminal of the second delay unit 200, and the other side connected to the node 1. NMOS 311 and the gate is connected to the output terminal of the inverter 101, one side is connected to the output terminal of the first delay unit 100 and the other side includes a PMOS 312 is connected to the node 1 ,

The second pass gate unit 320 includes an inverter 321 for inverting the output of the first delay unit 100, a gate connected to an output terminal of the second delay unit 200, and one side of the second pass gate unit 320. NMOS 322 connected to the other side and connected to the node 1, the gate is connected to the output terminal of the inverter 101, one side is connected to the node 2, the other side is connected to the node 1 PMOS 323 Consists of conducting, including

The pull-up unit 330, one side is connected to the power supply voltage, the other side is connected to the node 1, the gate is composed of a PMOS 330 is connected to the output terminal of the second delay unit 200,

The output unit 400 includes an inverter 401 for inverting the potential level of the node 1 and an output of the inverter 401 as an input to form a feedback loop, and an output terminal connected to the node 2 ( 402 and an inverter 403 for inverting the output of the inverter 401.

Hereinafter, the operation of one embodiment of the above-described configuration will be described in detail with reference to FIGS. 3 to 5.

First, when the operation of one embodiment according to the present invention is schematically described, when the potential levels of the plurality of addresses AD [0] to AD [n] that are applied do not transition, the first and second passgate portions When 310 or 320 is enabled and a transition occurs in any one of the potential levels of the plurality of addresses AD [0] to AD [n], the detection signal PD transitions to a low level. Each address applied by outputting a low level from the output unit 400 and outputting a low level until the first and second passgates 310 and 320 are deactivated by the second delay unit 200. Even if the transition timings are different, an output signal having a constant width is generated.

The above operation will be described in more detail with reference to the timing diagrams of FIGS. 4 and 5 as follows.

As shown in FIG. 4, the detection signal PD maintains a high level state before an address transition occurs, and the detection signal PD maintains the delay unit 102 and the second delay unit 200. After the predetermined time d1 is delayed, the first passgate 310 and the second passgate 320 are turned on.

Subsequently, when a transition occurs in any one of the plurality of addresses AD [0] to AD [n], the detection signal PD transitions to a low level, so that the NMOS 103 and the PMOS 104 are turned on. Output the level signal P1_OUT.

Meanwhile, the output signal P1_IN of the delay unit 102 is delayed by a predetermined time d2 from the second delay unit 200 to connect the first passgate 310 and the second passgate 320. Will be turned off.

Subsequently, when the detection signal PD transitions to a low level, the output signal P1_OUT of the first delay unit 100 is output by the signal P2_OUT output from the second delay unit 200. And a low level after being latched by the output unit 400 until the second pass gates 310 and 320 are turned off and the node 1 is isolated from the output signal P2_OUT of the second delay unit 200. Keep it and print it out.

Here, the turning off of the first passgate 310 by the output signal P2_OUT of the second delay unit 200 is an output signal P1_OUT of the node 1 and the first delay unit 100. The delay time d2 of the second delay unit 200 is greater than the maximum delay time that the addresses AD [1] to AD [4] can have. AD [4]) outputs a signal OUT having the same pulse width from the output unit 400 even when the respective transitions have different timings.

Subsequently, after the delay time d2 of the second delay unit 200, the first passgate 310 and the second passgate 320 are turned off, and the pull-up unit 330 is turned on to supply power. The voltage VDD is charged to the node 1.

The voltage occupied at the high level at node 1 is latched by the output unit 400 so that the output of the output unit 400 maintains the high level when the addresses AD [1] to AD [4] do not transition. Do it.

Therefore, the output signal OUT of the output unit 400 rises to a high level after the delay time d2, and the width of the output signal OUT generated by the output unit 400 whenever an address transition is detected. Is fixed to the delay time d2. If the width of the output signal OUT is to be adjusted, the second delay unit 200 may be adjusted to increase or decrease the delay time.

That is, even when the input addresses A [0] to A [n] have different timings, the pulse width of the output signal OUT is fixed constantly.

Finally, FIG. 5 shows an output OUT_1 when one address AD [0] is applied and a plurality of addresses AD [1] to AD [according to the timing diagram of FIG. 4. 3)) shows that the output OUT_3 is the same when applied at different timings, so that the address ADD [1] first goes from low to high and the address AD [4] last. In this case, the detection signal OUT_2 having the width corresponding to the delay time d2 of the second delay unit 200 is generated.

As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in the art.

As described above, the present invention can generate a detection signal having a constant pulse width even if the timing of the address applied using the delay time is not accurate.

Claims (8)

An apparatus for fixing a pulse width of a detection signal generated when detecting a transition of an address and data, First delay means for delaying and outputting the detection signal a predetermined time; Output means; Second delay means for delaying and outputting the output of the first delay means for a predetermined time; By fixing the time for which the detection signal output from the first delay means is transmitted to the output means to the delay time of the second delay means, the pulse width of the detection signal applied to the output means is adjusted to the second delay means. Pulse width control means for fixing with delay time Pulse width fixing device comprising a. According to claim 1, The pulse width control unit, A first passgate unit configured to isolate the output of the first delay means from the output of the first node in response to the output of the second delay means; A second pass gate portion forming a current path between the first node and the second node in response to the output of the second delay means to cause the output means to latch; And And a pull-up part configured to pull up an output terminal of the pulse width control part by an output of the second delay means. The method of claim 2, The first passgate portion, A first NMOS connected at one side to an output terminal of the first delay unit, at a gate thereof to an output terminal of the second delay unit, and at the other side to the first node; And The gate is connected to the output terminal of the second inverter, the pulse width fixing device characterized in that it comprises a first PMOS is connected to the output terminal of the first delay means and the other side is connected to the first node. The method of claim 2, The second passgate part, A first inverter for inverting the output of the first delay means; A second NMOS gate connected to an output terminal of the second delay means, one side of which is connected to the second node, and the other side of which is connected to the first node; And a gate is connected to an output terminal of the second inverter, one side is connected to the second node, and the other side includes a second PMOS connected to the first node. The method of claim 2, The pull-up unit, The pulse width fixing device, characterized in that one side is connected to the power supply voltage, the other side is connected to the first node, the gate is a third PMOS connected to the output terminal of the second delay means. The method of claim 1, The first delay means, A second inverter for inverting the detection signal; A delay unit for delaying the detection signal by a predetermined time; And a third NMOS and a fourth PMOS, each of which responds to the output of the first inverter and the output signal, each side of which is connected to an output of the first delay unit, and the other side of which is jointly connected to form an output stage. Pulse width fixing device characterized in that. The method of claim 1, The output means, A third inverter for inverting the potential level of the first node; A fourth inverter configured to form a feedback loop by using the output of the third inverter as an input, the output terminal being connected to the second node; And a fifth inverter for inverting the output of the third inverter. The method of claim 1, The delay time of the second delay means, And a delay time larger than a maximum delay time of said address and data.