KR20030058221A - A Short Line Linking Structure for Liquid Crystal Display Device - Google Patents

Abstract

PURPOSE: A short circuit wiring structure for a liquid crystal display is provided to improve the accuracy of a cutting process between odd short circuit wiring and even short circuit wring by removing only a semiconductor layer, thereby realizing the reliable liquid cell inspection process. CONSTITUTION: A semiconductor layer(124) made up of an active layer(124a) and an ohmic contact layer(124b) is formed on a gate insulating film(114) formed on a substrate(100). A first connecting bridge(133a) and a third b connecting bridge(135b) are formed on the semiconductor layer, separated from each other at certain intervals. The active layer between the first connecting bridge and the third b connecting bridge is used as a second connecting bridge(133b). A protective layer(144) is formed on the first connecting bridge and the third b connecting bridge, and the second connecting bridge. A cut area(II) exposing the active layer patterns of the second connecting bridge is formed on the protective layer. A second data pad electrode(154b) is formed at an area covering the third b connecting bridge. The active patterns in the cut area are removed.

Description

A short line linking structure for liquid crystal display device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and in particular, a short circuit wiring for a liquid crystal display device relates to a connection structure.

The driving principle of the liquid crystal display device is to use the optical anisotropy and polarization property of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, when the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal due to optical anisotropy to express image information.

Currently, an active matrix LCD (AM-LCD), in which a thin film transistor (TFT) and pixel electrodes connected to the thin film transistor are arranged in a matrix manner, is most noticeable because of its excellent resolution and video performance. I am getting it.

1 is a stereoscopic view of a part of a general liquid crystal display device.

As shown in the figure, the upper and lower substrates 10 and 30 face each other with a predetermined distance therebetween, and the liquid crystal layer 50 is interposed between the upper and lower substrates 10 and 30.

A plurality of gates and data lines 32 and 34 cross each other on the lower substrate 30, and a thin film transistor T is formed at a point where the gates and data lines 32 and 34 cross each other. A pixel electrode 46 connected to the thin film transistor T is formed in the pixel area P defined as an area where the gate and the data lines 32 and 34 intersect.

The color filter layer 12 and the common electrode 16 are sequentially formed below the upper substrate 10.

Although not shown in detail in the drawing, the color filter layer 12 is composed of a color filter for transmitting only light of a specific wavelength band and a black matrix positioned at a boundary of the color filter to block light on an area where the arrangement of liquid crystals is not controlled.

In addition, upper and lower polarizers 52 and 54 for transmitting only light parallel to the polarization axis are positioned on each outer surface of the upper and lower substrates 10 and 30, and a backlight, which is a separate light source, is provided below the lower polarizer 54. light) is placed.

The array substrate constituting the lower substrate is formed through a mask process.

The mask process refers to a series of processes for fabricating a separate mask and patterning each layer (insulating layer, active layer, metal layer) in an arbitrary form through etching by a photolithography process.

Conventionally, the 5 mask process is mainly used, but if the mask process is reduced, the process cost can be considerably reduced and the process time can be shortened, thereby reducing the incidence of defects.

In recent years, research has been actively conducted on a method of manufacturing an array substrate for a liquid crystal display device by a four mask process.

In the conventional five mask process, the gate process (gate electrode, gate pad, gate wiring), semiconductor layer process (active layer, ohmic contact layer), source process (source and drain electrodes, data wiring, data pad, channel), contact It consisted of a hole process (drain contact hole, pad contact hole) and an ITO process (pixel electrode, pad electrode).

However, the four mask process is characterized by comprising a gate process, a semiconductor layer / source process, a contact hole process, and an ITO process.

In particular, since the data metal and the semiconductor material are patterned correspondingly in the semiconductor layer / source process, the semiconductor layer is left in the channel portion by the diffraction exposure method. The diffraction exposure method is a method of controlling the thickness of the PR layer by using the diffraction phenomenon of light.

In addition, in the liquid crystal cell process of manufacturing a panel for a liquid crystal display device through a liquid crystal layer between the array substrate and the color filter substrate, which is another opposite substrate, an inspection process for discriminating a good product is performed. Short circuits are provided in the non-display area of the array substrate to prevent static electricity during the array process.

FIG. 2 is a plan view illustrating a connection structure of short circuits in a conventional four mask liquid crystal display, and will be described with reference to a data wiring unit as an example.

As shown in the drawing, the data line 60 is formed in one direction, and at one end of the data line 60, a data pad 62 connected to an external circuit is formed. It is connected to a short circuit 64 for the inspection process.

The short-circuit wire 64 includes an odd short-circuit wire 64a that binds odd-numbered wires like the first data wire 62a and an even-row wire that binds even-numbered wires like the second data wire 60b. The short-circuit wiring 64b is formed, and the first short-circuit wiring 64a has first and second connection bridges 66a and 66b extending from the first and second data pads 62a and 62b. In this case, the reason why the first and second connection bridges 66a and 66b connected to the first and second data pads 62a and 62b are configured from the odd short circuit line 64a is that the static electricity generated during the process in the array process, in particular, Static electricity, which is likely to occur in the active layer forming step or the protective layer etching step, is locally present between the substrate and the array pattern, and the voltage is very high in the local area, thereby damaging sensitive devices such as thin film transistors. To prevent this, it is to prevent this.

In addition, since the even short wiring 64b is formed in the gate process to prevent the short circuit of the odd short wiring 64a from being shorted, the third connection bridge 66c of the link type is connected to the second data pad 62b. Is formed, and the third connection bridge 66c is connected to the second data pad 62b.

In addition, first and second data pad electrodes 68a and 68b made of a transparent conductive material are formed in regions covering the first and second data pads 62a and 62b, respectively. In this case, the second data pad electrodes 68b are formed. Is formed with an area that simultaneously covers the second data pad 62b and the third connection bridge 66c.

In addition, a plurality of contact holes 70 are formed at positions corresponding to the first and second data pads 62a and 62b and the third connection bridge 66c, respectively. The pad 62a and the first data pad electrode 68a, the second data pad 62b, the third connection bridge 66c and the second data pad electrode 68b are electrically connected to each other.

In the process of forming the contact hole 70, the cut region exposing the data metal to the second connection bridge 66b in order to disconnect the connection between the odd short circuit line 64a and the second data line 60b ( I) is formed, and the data metal of the cut region I is removed through dry etching, so that the odd short wiring 64a and the second data wiring 60b are electrically disconnected.

The data line 60, the data pad 62, the odd short circuit line 64a, and the first and second connection bridges 66a and 66b include a semiconductor layer 72 pattern due to four mask process characteristics.

Accordingly, in the process of removing the data metal in the cut region I, there is a problem in that the semiconductor layer constituting the data metal lower layer is not properly removed. Because the cut region I is formed in the third mask process, and the process of removing the data metal material in the cut region I is performed after the fourth mask process, so that the metal in the cut region I is As the number of processes to remove material increases, it is easy to damage the product.

Accordingly, when the data metal and the semiconductor layer in the cut region I are removed under the same dry etching condition, the semiconductor layer may not be removed well, and disconnection between the odd-circuit wiring and the even-numbered wiring is not performed properly. There is a problem that causes wiring defects.

In order to solve the above problems, the present invention is characterized by providing a highly reliable process for inspecting the liquid crystal cell by reducing the defective rate between the even / odd short circuit.

To this end, in the present invention, in forming a connection bridge connecting the odd short wiring and the even wiring, the semiconductor material is configured by using a diffraction exposure method.

1 is a three-dimensional view of a portion of a general liquid crystal display device.

2 is a plan view showing a connection structure of short-circuit wiring in a conventional four-mask liquid crystal display device.

3 is a plan view of an array substrate for a liquid crystal display device according to the present invention;

4A and 4B are cross-sectional views each showing a section cut along the cutting line IVb-IVb of FIG. 3.

<Description of Symbols for Main Parts of Drawings>

124: semiconductor layer 133a: first connecting bridge

133b: second connection bridge 135b: 3a connection bridge

144: protective layer 154b: second data pad electrode

II: cut area

In order to achieve the above object, the present invention includes a plurality of gate and data lines formed to cross each other, a thin film transistor formed at a point where the gate and data lines intersect, a pixel electrode connected to the thin film transistor, and the data An array substrate for liquid crystal display devices in which a semiconductor layer pattern is positioned at a position corresponding to a wiring, comprising: an odd data short circuit wiring for binding an odd data wiring of the plurality of data wirings; An even data short-circuit wiring, which binds an even-numbered data wiring of the plurality of data wirings and is made of the same material as the gate wiring; A first connection bridge extending from the odd data short wiring and connecting the odd data short wiring and an odd-numbered data wire; A second connection bridge connecting the even data short line and an even-numbered data line and extending from the data line; A liquid crystal display including a third connection bridge formed between the first and second connection bridges and formed of a semiconductor material withdrawn from the first and second connection bridges and having a cut region from which the semiconductor layer material is removed; The short circuit wiring part of the array substrate is provided.

A data pad positioned at one end of the data line, the data pad being connected to an external circuit, connected to the data short circuit line through the data pad, and a data pad electrode formed of the same material as the pixel electrode in an area covering the data pad; Characterized in that it comprises a.

The second connection bridge includes a 2a connection bridge extending from an even data short-circuit wiring, and a second b connection bridge configured to be connected in the same direction as the second a connection bridge in the data pad. And an area covering the second connection bridge and the even-numbered data pad in one pattern.

The third connection bridge is formed by a diffraction exposure method, and the semiconductor layer is formed by sequentially forming an active layer and an ohmic contact layer, and the third connection bridge is formed of an active layer.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

3 is a plan view of an array substrate for a liquid crystal display device according to an exemplary embodiment of the present invention.

As shown in the drawing, a gate line 116 is formed in a first direction on an active area of an array substrate 110 including an active area defined as an area where a screen is implemented and an inactive area that is an outer portion of the active area. The data line 130 is formed in the second direction crossing the first direction, and the thin film transistor S is formed at the point where the gate and the data lines 116 and 130 intersect, and is connected to the thin film transistor S. Thus, the pixel electrode 150 is formed. In addition, an area of the pixel electrode 150 overlapping the gate line 116 forms a storage capacitor C _ST .

Hereinafter, the pad portion and the short circuit wiring portion formed on the inactive region will be described in detail with reference to the data pad portion and the data short circuit wiring portion, which are features of the present invention.

The data pad 132 is connected to the data line 130 on the inactive region, and the data pad 132 is connected to the data short line 137 for an antistatic and inspection process.

In more detail, the data short wiring 137 may include an odd data short wiring 134 for binding odd-numbered wires such as the first data wire 130a and an even-numbered wire like the second data wire 130b. It consists of an even data short wiring 122 which is bundled.

In this case, the data line 130, the data pad 132, and the odd data short circuit line 134 may include a semiconductor layer 124 pattern.

The odd data short circuit 134 includes a first connection bridge 133a connected to the first data pad 132a and a second connection bridge 133b connected to the second data pad 132b, and even data. The short-circuit wiring 122 includes a 3a connection bridge 135a having a link structure connected to the second data pad 132b, and the 3b connection bridge 135b extends from the second data pad 132b. Thus, the 3a, 3b connection bridges 135a, 135b are configured to be connected to each other in the same direction.

The odd data short wiring 134 is connected to all the wires to prevent static electricity between the wirings and to form an equipotential during the array process, and then connects the even data short wiring 122 and the second data pad 132b. The cut area II which cuts off the connection with the 2nd data pad 132b is comprised in the 2nd connection bridge 133b.

The second connection bridge 133b according to the present invention is a pattern made of an intrinsic semiconductor layer material, and is formed over the first and second data pads 132a and 132b.

In more detail, the second connection bridge 133b is formed of the active layer 124a of the semiconductor layer 124 as it proceeds using the same diffraction mask as the channel forming process of the thin film transistor, not shown. As the second connection bridge 133b is formed of a semiconductor layer material, static electricity of all the wires connected to the short circuit can be prevented.

In particular, in the present invention, since the second connection bridge 133b is formed of a semiconductor material containing no data metal, the connection between the odd data short-circuit wiring 134 and the second connection bridge 133b can be effectively interrupted in the cutting process. .

Meanwhile, a plurality of contact holes 142 are formed in the first and second data pads 132a and 132b and the third a connection bridge 135a, respectively, so that the first and second data pads may be formed through the contact holes 142. First and second data pad electrodes 154a and 154b are formed to be connected to the 132a and 132b and the third a connecting bridge 135a. In this case, the second data pad electrode 154b is formed to cover the second data pad 132b and the 3a and 3b connection bridges 135a and 135b in a single pattern.

4A and 4B are cross-sectional views each showing a cross section cut along the cutting line IVb-IVb of FIG. 3.

FIG. 4A is a step of forming a short-circuit interconnect bridge having a different stacked structure by diffraction exposure method. In this step, an active layer 124a and an ohmic contact layer 124b are formed on a substrate on which the gate insulating layer 114 is formed. The semiconductor layer 124 configured in this order is formed, and the first connection bridge 133a and the third b connection bridge 135b spaced apart from each other by a predetermined distance are formed on the semiconductor layer 124, and the first connection bridge is formed. The active layer 124a in the section between 133a and the 3b connection bridge 135b is used as the second connection bridge 133b.

In this case, the single-layer structure between the first and 3a connection bridges 133a and 135b and the second connection bridge 133b is different from that of the slit portion Va at a position corresponding to the second connection bridge 133b in the photolithography process. This is because the branch uses the mask 210.

The mask 210 includes an exposure part Vb at a position corresponding to the left and right gate insulating layers of the first and 3a connection bridges 133a and 135b.

Although not shown in the drawings, in the process using the mask, applying a PR layer on the data metal material, exposing and developing the PR layer through the mask to form a PR layer pattern, and Forming a metal pattern through.

In FIG. 4B, forming a protective layer 144 over the first and third connection bridges 133a and 135b and the second connection bridge 133b, and forming a second connection bridge 133b on the protective layer 144. Forming a cut region (II) exposing a pattern of the active layer 124a of the ()) and forming a second data pad electrode 154b in a region covering the third b bridge bridge 135b. This is a step of removing the active layer 124a pattern in the cut region II.

As described above, in the present invention, since only the active layer 124a pattern is present in the cut region II, the connection between the odd short wiring and the even-numbered wiring can be effectively blocked by one etching process in the cut process.

However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present invention.

As described above, according to the present invention, in the four-mask liquid crystal display device, in order to reduce the even / od short wiring defect by increasing the accuracy of the cut process between the odd short wiring and the even-numbered wiring in forming the data short wiring section, Since the connecting bridge connecting the wirings and the even-numbered wirings is constituted by the semiconductor layer pattern in the second mask process by the diffraction exposure method, only the semiconductor layer is removed in the cut process, so that the cut processability can be increased, thereby providing a reliable liquid crystal cell inspection. Process can be provided.

Claims (6)

A plurality of gate and data lines formed to cross each other, a thin film transistor formed at an intersection point of the gate and data lines, a pixel electrode connected to the thin film transistor, and a semiconductor layer pattern at a position corresponding to the data line In the array substrate for liquid crystal display device located, An odd data short wiring connecting the odd data wirings among the plurality of data wirings; An even data short-circuit wiring, which binds an even-numbered data wiring of the plurality of data wirings and is made of the same material as the gate wiring; A first connection bridge extending from the odd data short wiring and connecting the odd data short wiring and an odd-numbered data wire; A second connection bridge connecting the even data short line and an even-numbered data line and extending from the data line; A third connection bridge formed between the first and second connection bridges and formed of a semiconductor material withdrawn from the first and second connection bridges and having a cut region from which the semiconductor layer material is removed; Short circuit wiring portion of the array substrate for a liquid crystal display device comprising a. The method of claim 1, And a data pad positioned at one end of the data line, the data pad being connected to an external circuit and connected to the data short wiring through the data pad. The method of claim 2, And a data pad electrode formed of the same material as the pixel electrode in an area covering the data pad. The method according to claim 1 or 2, The second connection bridge includes a 2a connection bridge extending from an even data short-circuit wiring, and a second b connection bridge configured to be connected in the same direction as the second a connection bridge in the data pad. A short-circuit wiring portion of an array substrate for a liquid crystal display device having an area covering the second connection bridge and the even-numbered data pad in a pattern. The method of claim 1, And the third connecting bridge is a short-circuit wiring portion of an array substrate for a liquid crystal display device formed by a diffraction exposure method. The method of claim 1, The semiconductor layer is formed by sequentially forming an active layer and an ohmic contact layer, and wherein the third connection bridge comprises an active layer.