KR20030056361A - Method for forming location detecting pattern of semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a position detecting pattern of a semiconductor device is provided to be capable of detecting the position of a corresponding die at a wafer after carrying out a die sawing process by inserting a sub-pattern at a blind region. CONSTITUTION: A wafer includes a plurality of dies, an image field(21), and a blind region(22). A sub-pattern(23) is inserted at the blind region(22) by changing the formation position and shape of the sub-pattern corresponding to each die for carrying out a position detecting process. Preferably, the number of the position detecting patterns exposed to an adjacent die, is capable of being controlled by differently installing the blind region of each die. Preferably, the position detecting pattern is made of at least one selected from a group consisting of a box type, bar type, round type, agraffe type and number type structure.

Description

Method for forming location detecting pattern of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of semiconductor devices, and more specifically, to inserting an auxiliary pattern for position detection in a blind region so that a position on a wafer of a die can be detected even after a die sawing process. A method for forming a position detection pattern of an element.

In recent years, yield improvement is rapidly progressing in the manufacturing process of semiconductor devices. In addition, the improvement of process equipment and process technology greatly contributed to the yield improvement, but in-line monitoring applied in the actual manufacturing stage also contributed greatly.

In other words, the in-line monitoring technique, which is not an indirect monitoring method in which immediate measures are difficult to find when a problem is found, refers to inspecting a wafer actually produced in a unit process through a wafer inspection system.

Therefore, based on the inspection result obtained in the wafer inspection system, it is possible to quickly detect process defects and equipment defects occurring in each unit process and normalize them quickly.

Therefore, it is possible to minimize the production cost by maximizing the yield and reducing the waste of the production cost due to the defect by quickly detecting the occurrence of the defect in a short time and normalizing it.

Hereinafter, a semiconductor device manufacturing method of the prior art will be described.

1 is a wafer configuration for a wafer level test of the prior art.

What is done in the wafer inspection system during the in-line monitoring process is to inspect the defects on the wafer using a laser or optical system to determine the size, defect cluster and defect size of the defects on the wafer. Detect shape, color and density of defects, and location.

In a wafer on which a conductive pattern such as a metal pattern or a polysilicon pattern doped with impurities is formed, an optical system is used to recognize an image formed on the wafer through an image sensor, and the recognized image is processed in a digital state on a computer. do.

Typically, devices are manufactured in the following manner.

First, Fab. In the process of wafer processing in the process of collecting the in-line data.

After wafer processing is completed, a PT1 test is performed at the wafer level to confirm wafer characteristics through a bit map.

Subsequently, in the chip individualization process of the wafer which passed the PT1 test, the package step is performed after sawing of the die, and the package test is performed when the package process is completed.

In the case of PT1 test at the wafer level, it is possible to check where the repairable die and the non-repairable die exist on the wafer. Process parameters can be changed to vary wafer processing within.

However, even a die that passes in PT1 can fail when testing a package after completion.

However, as the die is already sawed, the position of the failed die in the wafer cannot be tracked.

In addition, the problem that the location of the failed die in the wafer can not be traced can cause the same problem in post-package mounting testing.

In the case where it is determined as a repairable die with the bitmap obtained after the PT1 test at the wafer level, sawing is performed in the form of a die as shown in FIG.

As shown in (b), it was determined that the die can be repaired at the wafer level, but when a problem is found after the package is completed, it is difficult to know its position in the wafer.

(C) shows an example of a die that works normally if it is determined to be normal even during a wafer level test and there is no problem in a test after package.

As such, even though all of the dies have been found to be repairable dies at the wafer level, they are found to fail again after package completion.

Since mass production has already begun, stable devices yield more than 90% of package yield, while devices in the development stage have yields of 40%. To solve this problem, the variable parameters of the process must be changed.

The process parameters are characteristic of the radial direction of the wafer, and where the location (center area or edge area) within the wafer of the failed die is packaged after packaging.

In other words, it is important to know the in-wafer location of the failed die when solving the problem of failing after package by changing inline process variable parameters.

However, such a device manufacturing process of the prior art has the following problems.

At the wafer level, if all dies are found to be repairable dies, the inline process variable parameters must be changed if they fail again after package completion. In the prior art, it is impossible to determine the in-wafer location of a failed die after package completion. .

This acts as a cause of lowering the yield of the device by preventing the change of the process parameters efficiently.

This increases the manufacturing cost of the product, which in turn lowers the product's competitiveness.

The present invention solves the problems of the prior art device fabrication process and test, by inserting an auxiliary pattern for position detection in the blind region to the wafer of the die after the die sawing process SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a position detection pattern of a semiconductor device capable of detecting a position of a semiconductor device.

1 is a wafer configuration for a wafer level test of the prior art

2 is a plan view of the reticle inserted with the position detection pattern according to the present invention

3 is a wafer configuration diagram to which the position detection pattern according to the present invention is applied.

* Description of the symbols for the main parts of the drawings *

21. Image Field 22. Blind Area

23. Position Detection Pattern

In order to achieve the above object, a method of forming a position detection pattern of a semiconductor device according to the present invention includes a plurality of dies, and packaged the die positions in a wafer having an image field to be exposed and a blind area excluding the image field. In order to be marked, an auxiliary pattern for position detection may be inserted into the blind area by varying a formation position and a shape corresponding to each die.

Hereinafter, a method of forming a position detection pattern of a semiconductor device according to the present invention will be described in detail.

2 is a plan view of a reticle having a position detection pattern inserted therein, and FIG. 3 is a wafer configuration to which the position detection pattern according to the present invention is applied.

The present invention is applied at the time of die testing in the wafer fab. The photolithography is used to insert an auxiliary pattern so that the wafer position of the die can be recognized even after die sawing.

As shown in FIG. 2, the reticle is configured in such a manner that an auxiliary pattern is inserted into an arbitrary layer.

Since only the image field 21 is exposed on the wafer, the blind area (obscured by an area other than the exposure area) 22 is set in accordance with the image field 21.

In this case, the blind region 22 is set differently in accordance with the wafer position so that the inserted position detection pattern 23 is exposed to the adjacent die.

In this way, the blind region 22 of each die may be set differently to control the number of the position detection patterns 23 exposed to the adjacent dies.

That is, the position detection pattern 23 is formed in the blind area 22 except the image field 21 of the die, so that the position detection pattern 23 can be used to determine the position on the wafer of the die.

The number and position of formation of the position detection pattern 23 are variable, and the die position is determined using the position detection pattern 23, and the wafer position of the found die is packaged and marked and used to reset the process parameters.

The number of position detection patterns 23 is sequentially adjusted using blinds or blades of the exposure equipment.

The position detection pattern 23 may be configured in any of box type, bar type, round type, angle bracket type, and numeric type.

In the case of using the inserted position detection pattern as shown in FIG. 3, it is possible to grasp the position in the wafer of each die even after the package by measuring the package after sawing.

Such a method for forming a position detection pattern of a semiconductor device according to the present invention has the following effects.

First, excellent wafer position-specific evaluation is possible compared to the wafer base characteristic evaluation.

Second, when the wafer is failed after evaluating the wafer level characteristics, it is possible to increase the accuracy of the process parameter change during the in-line process by identifying the position of the die in the wafer.

Third, it is possible to grasp the tendency of the wafer yield per package position, and can be applied by the repair of the reticle without additional equipment and materials investment, thereby reducing the manufacturing cost.

Claims (3)

In order to be able to mark post-package die positions in a wafer comprising a plurality of dies and having a blind area excluding the actual exposed image field, And forming an auxiliary pattern for position detection by varying a formation position and a shape corresponding to each die in the blind region. The method according to claim 1, wherein the number of position detection patterns exposed to adjacent dies is controlled by differently setting the blind regions of each die. The method for forming a position detection pattern of a semiconductor device according to claim 1, wherein the position detection pattern is formed of any one of box type, bar type, round type, angle type, number type, or a combination thereof.