KR20030055796A - Method of manufacturing semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to be capable of preventing the generation of defects due to remaining of a buffer oxide layer in SAC(Self Aligned Contact) processing. CONSTITUTION: A stacked gate(15) including a gate oxide layer(12), a gate conductive layer(13) and a hard mask(14), is formed on a semiconductor substrate(11). A buffer oxide layer and a nitride layer are sequentially formed on the stacked gate(15) and the substrate(11). An interlayer dielectric is formed on the resultant structure. By selectively etching the interlayer dielectric, the nitride layer and the buffer oxide layer, a buffer oxide pattern(16) and a nitride spacer(17) are formed. At this time, the etching selectivity of the nitride layer and the oxide layer is 1: 1.

Description

Manufacturing method of semiconductor device {METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for preventing the occurrence of process defects due to the residual of a buffer oxide film during a self aligned contact process.

As the integration of semiconductor devices has progressed, there has been difficulty in the electrical connection between the upper and lower patterns. Accordingly, the current semiconductor manufacturing process is performed by performing a self aligned contact (SAC) process. It is well known that a stable electrical contact to the liver is achieved.

Unlike the conventional process of performing electrical contact between the substrate and the bit line and the substrate and the capacitor, the SAC process has a gate electrode in a state in which contact holes for simultaneously exposing predetermined gates and a substrate region therebetween are formed. The plug pulleys are embedded between them, so that the electrical contact between the substrate and the bit line and the substrate and the capacitor is simultaneously performed.

On the other hand, a nitride film is used as the gate spacer material. If the nitride film is directly deposited after the gate is formed, the substrate is stressed due to the difference in thermal expansion coefficient between silicon and the nitride film.

Therefore, in the conventional semiconductor manufacturing process to which the SAC process is applied, an oxide film is thinly deposited as a stress buffer film between the gate and the nitride film spacer to improve transistor characteristics and secure refresh characteristics.

However, when the LPC (Landing Plug Contact) etching process, which is one of the SAC processes, is performed on the substrate product to which the buffer oxide film is applied, the gate 5 may be formed due to the etching selectivity between the nitride film and the oxide film. The phenomenon that the buffer oxide film deposited on the surface remains in a sharp shape, which causes difficulty in subsequent chemical mechanical polishing (CMP) of polysilicon, and furthermore, bit line contact ) And a shortage of storage node contacts.

In FIG. 1, reference numeral 1 denotes a semiconductor substrate, 2 a gate oxide film, 3 a gate conductive film, 4 a hard mask film, 6 a buffer oxide film, 6a a buffer oxide film remaining on the hard mask film, and 7 represents a nitride film spacer, respectively.

Accordingly, the present invention has been made to solve the above problems, it is possible to prevent the process defects to be generated in the subsequent by remaining the pointed buffer oxide film on the edge of the gate hard mask film during the LPC etching process. It is an object of the present invention to provide a method for manufacturing a semiconductor device.

1 is a view for explaining a problem in the prior art.

2 illustrates a semiconductor device formed in accordance with an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

11 semiconductor substrate 12 gate oxide film

13 gate conductive film 14 hard mask film

15 gate 16 buffer oxide film

17: nitride film spacer

According to an aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method including: forming a gate having a stacked structure of a gate oxide film, a gate conductive film, and a hard mask film on a semiconductor substrate provided with a device isolation film; Sequentially depositing a buffer oxide film and a spacer nitride film on the gate and the substrate; Depositing an interlayer insulating film on the nitride film; And etching the interlayer insulating film, the nitride film, and the buffer oxide film so that the substrate regions between the predetermined gates and the gates are exposed, wherein the etching is performed by selecting an etching selectivity ratio of nitride to oxide of the film. It is characterized by performing under an etching condition of 1.

Here, the etching may be performed using a CHF3 / CF4 base gas having a gas composition ratio of CF4: CHF3 of 1: 1 to 1: 2, or using a CF4 base gas, and CF4: CHF3 of 5: 1 or less at a total gas flow rate. It is carried out under process conditions such that the power range is 700W or less and the process pressure range is 50mT or less.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a view showing a semiconductor device manufactured according to an embodiment of the present invention, the manufacturing method will be described with reference to this.

First, a gate oxide film 12, a gate conductive film 13, and a hard mask film 14 are sequentially formed on a semiconductor substrate 11 on which a trench type isolation layer (not shown) is formed according to a known process. The films are patterned to form the gate 15.

Then, a buffer oxide film 16 is formed on the gate 15 and the substrate 11 to a thickness of 100 GPa or more, preferably 100 to 300 GPa, and then a nitride nitride film 17 for spacers is formed on the buffer oxide film 16. ), An interlayer insulating film (not shown) made of BPSG, HDP, or SROX is deposited on the nitride film 17.

Next, an LPC etching process is performed on the interlayer insulating layer to form contact holes (not shown) that expose all of the gates 15 and the substrate region therebetween. In this case, unlike the conventional one, the LPC etching is performed using an etching gas having an etching selectivity ratio of nitride to oxide of 1: 1.

That is, the present invention uses the CHF3 / CF4 base gas or CF4 base gas instead of the conventional CHF3 / O2 base gas as the etching gas, the gas composition ratio of CF4: CHF3 1: 1 to 1 :: 2, CF4: CHF3 is maintained at 5: 1 or less at the entire gas flow rate, and the power range is controlled to 700W or less and the process pressure range is set to 50mT or less.

Then, although not shown, the semiconductor device of the present invention is completed by performing a series of subsequent processes including polysilicon deposition and CMP thereto.

In the semiconductor device of the present invention manufactured according to the above process, the LPC etching is performed by setting the etching selectivity between the nitride film and the oxide film at about 1: 1, so that the buffer oxide film remains sharply at the edge of the gate hard mask film. The phenomenon can be prevented.

Therefore, due to the pointed shape of the buffer oxide film residues, subsequent process difficulties in polysilicon CMP are not caused, and as a result, it is possible to secure the reliability of the bit line contact and the storage node contact.

As described above, according to the present invention, the LPC etching process may be performed under process conditions in which the etching selectivity of the nitride film and the oxide film is 1: 1, thereby preventing the occurrence of process defects caused by the residual buffer oxide film. Furthermore, failure of bit line contacts and storage node contacts can be prevented.

Accordingly, the present invention can prevent the occurrence of defects in the LPC etching process, which is one of the SAC processes, to stabilize the process and to improve the manufacturing yield, and to improve the refresh characteristics of the transistor specification and the capacitor. Can be.

Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.

Claims (4)

Forming a gate having a stacked structure of a gate oxide film, a gate conductive film, and a hard mask film on a semiconductor substrate provided with an isolation layer; Sequentially depositing a buffer oxide film and a spacer nitride film on the gate and the substrate; Depositing an interlayer insulating film on the nitride film; And etching the interlayer insulating film, the nitride film, and the buffer oxide film so that a predetermined gate and a substrate region between the gates are exposed. The etching is a method of manufacturing a semiconductor device, characterized in that the etching is performed by the etching conditions of the etching selectivity ratio of the nitride film to the oxide film 1: 1. The method of claim 1, wherein the buffer oxide film is deposited to a thickness of 100 to 300 GHz. The method of claim 1, wherein the etching is Using a CHF3 / CF4 base gas with a gas composition ratio of CF4: CHF3 of 1: 1 to 1: 2, CF4: CHF3 of 5: 1 or less at a total gas flow rate, power range of 700W or less, process A process for producing a semiconductor device, characterized in that the pressure range is carried out under process conditions of 50 mT or less. The method of claim 3, wherein the etching is performed using a CF 4 base gas.