KR20030054882A - Liquid Crystal Display - Google Patents

Abstract

PURPOSE: A liquid crystal display device is provided to improve the quality of a picture by preventing signal delay with a buffer formed in the center of a signal line located in an active area. CONSTITUTION: A digital video card converts analog data to digital video data. A data driver supplies the video data to a plurality of data lines of a liquid crystal panel. A gate driver drives a plurality of gate lines of the liquid crystal panel sequentially. A control unit controls the data driver and the gate driver. A buffer(35) is formed in the center of the gate line within an active area for compensating a gate signal(GS) delayed due to resistances and capacitors. A relatively distorted n/2 gate signal is inputted to a non-inverting input terminal of the buffer. The buffer compensates the distorted signal for outputting an (n+1)/2 gate signal equal to the gate signal, so that a compensated gate signal(GSn) appears at a right end of the gate line.

Description

Liquid Crystal Display

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of improving image quality.

In general, a liquid crystal display (hereinafter referred to as "LCD") displays an image in response to a video signal using a pixel matrix arranged at an intersection between gate lines and data lines. Each pixel includes a liquid crystal cell Clc for adjusting light transmittance according to a video signal, and a thin film transistor for switching a video signal to be supplied to the liquid crystal cell Clc from the data line DL. : "TFT") and a gate line GL for supplying a gate driving signal so that a video signal supplied from the data line DL can be supplied to the liquid crystal cell Clc. In addition, the LCD is provided with gate and data drivers (not shown) for supplying driving signals to the gate line GL and the data line DL.

The gate terminal of the TFT is connected to the gate line GL, and the source terminal of the TFT is connected to the data line DL. The drain terminal of the TFT is connected to the pixel electrode of the liquid crystal cell Clc. When the gate line GL corresponding to one line is represented by an electrical equivalent circuit, as shown in FIG. 2, the resistors R and the capacitors C may be represented. The resistors R constitute a resistance of the gate line GL, and a value thereof is determined by the material constituting the gate line GL, length, width, and thickness. In addition, the capacitance value of the capacitor C is added by the capacitance value of the gate electrodes of the TFTs, the capacitance value between the electrodes included in the liquid crystal cell Clc, and the capacitance value between the gate line GL and the data line DL. It is decided. The line delay occurs in the gate signal GS generated by the gate driver (not shown) by the resistor R and the capacitor C. FIG. This will be described with reference to FIG. 3.

Referring to FIG. 3, the gate signal GS is input to the gate line GL in a period in which the data signal DS is supplied to the data line DL. At this time, the delayed gate signal DGS that gradually increases from the rising edge of the gate signal GS appears at the right end of the gate line GL far from the input terminal of the gate signal GS. The delayed gate signal DGS corresponds to the point of time when the threshold voltage Vth becomes higher than its threshold voltage, that is, the product of the resistance value R and the capacitance value of the capacitor D in FIG. 2 from the rising edge of the gate signal GS. Turn on at a time elapsed by the time constant? The delayed gate signal DGS is gradually reduced from the falling edge of the gate signal GS. At this time, the TFT located at the right end of the gate line GL has a time constant τ from the time when the delayed gate signal DGS becomes lower than its threshold voltage Vth, that is, the falling edge of the gate signal GS. Turn off at elapsed time. As a result, the effective gate signal EGS is applied to the gate electrode of the TFT located at the right end far from the input terminal of the gate signal GS, which is delayed by a time corresponding to the time constant?. By this effective gate signal EGS, the liquid crystal cell Clc positioned at the right end of the gate line GL has elapsed from the rising edge of the data signal DS by the time constant τ of the gate line GL. The signal voltage is charged from the time point from the falling edge of the data signal DS to the time point elapsed by the time corresponding to the time constant? Of the gate line GL. In other words, the liquid crystal cell Clc charges the data signal voltage of the next line from the falling edge of the gate signal GS during the time constant τ. Therefore, the effective charging voltage CS charged in the liquid crystal cell does not maintain the data signal voltage DS but changes by the difference voltage with the data signal voltage to be applied to the liquid crystal cell of the next line. As a result, the signal voltage charged in the liquid crystal cells Clc is distorted due to the propagation delay of the gate signal GS in the gate line GL. This problem is exacerbated as the gate line GL becomes longer, i.e., becomes larger.

Accordingly, an object of the present invention is to provide a liquid crystal display device capable of improving image quality.

1 illustrates a liquid crystal cell formed at an intersection of a data line and a gate line.

FIG. 2 is an equivalent circuit diagram showing gate lines for one line shown in FIG.

3 is a waveform diagram illustrating signals applied to gate lines and data lines of a liquid crystal panel;

4 is a diagram illustrating a liquid crystal display according to a first embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram showing gate lines for one line shown in FIG. 4; FIG.

FIG. 6 is a diagram illustrating a compensator shown in FIG. 4. FIG.

7 is a waveform diagram illustrating a signal applied to a gate line of the liquid crystal panel shown in FIG. 4.

8 illustrates a liquid crystal display according to a second exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

31 digital video card 32 control unit

33: data driver 34: gate driver

35: compensator 36: liquid crystal panel

In order to achieve the above object, the liquid crystal display according to the first embodiment of the present invention includes a gate line to which a gate signal is supplied, and a buffer formed on the gate line in the effective display area.

The buffer is characterized in that formed in the center of the gate line.

In order to achieve the above object, the liquid crystal display according to the second embodiment of the present invention includes a data line to which data is supplied and a buffer formed on the data line in the effective display area.

The buffer is formed at the center of the data line.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 8.

Referring to FIG. 4, the liquid crystal display according to the first exemplary embodiment of the present invention may include a digital video card 31 for converting analog data into digital video data, and data lines DL of the liquid crystal panel 36. The data driver 33 for supplying video data, the gate driver 34 for sequentially driving the gate lines GL of the liquid crystal panel 36, and the data driver 33 and the gate driver 34 A control unit 32 for controlling is provided.

The digital video card 31 converts an analog input video signal into digital video data and detects a synchronization signal included in the video signal.

The control unit 32 supplies the red (R), green (G) and blue (B) digital video data from the digital video card 31 to the data driver 33. In addition, the controller 32 generates the dot clock Dclk and the gate start pulse GSP using the horizontal / vertical synchronization signals H and V input from the digital video card 31 to generate the data driver 33 and the data driver 33. The timing of the gate driver 34 is controlled. The dot clock Dclk is supplied to the data driver 33, and the gate start pulse GSP is supplied to the gate driver 34.

The data driver 33 receives a dot clock Dclk together with video data of red (R), green (G), and blue (B) from the control unit 32. The data driver 33 latches the red (R), green (G) and blue (B) digital video data in synchronization with the dot clock Dclk, and then corrects the latched data in accordance with the gamma voltage Vγ. Done. The data driver 33 converts the data corrected by the gamma voltage Vγ into analog data and supplies the data lines DL by one line.

The gate driver 34 may include a shift register (not shown) that sequentially generates a gate signal in response to a gate start pulse GSP input from the controller 32, and a level suitable for driving a gate signal voltage of the liquid crystal cell. And a level shifter (not shown) for shifting to a low level. In response to the gate signal input from the gate driver 34, video data on the data line DL is supplied to the pixel electrode of the liquid crystal cell Clc by the TFT.

In the liquid crystal panel 36, liquid crystal is injected between two glass substrates, and the gate lines GL and the data lines DL are orthogonal to each other on the lower glass substrate. A TFT for selectively supplying an image signal input from the data lines DL to the liquid crystal cell Clc is formed at the intersection of the gate lines GL and the data lines DL. For this purpose, the drain terminal of the TFT is connected to the pixel electrode of the liquid crystal cell Clc, and the source terminal of the TFT is connected to the data line DL. The gate terminal of the TFT is connected to the gate line GL.

A compensation unit 35 is formed in the gate line GL as shown in FIG. 5. The compensator 35 is formed at the center of the gate line GL to prevent a delay of the gate signal GS. In detail, the electrical equivalent circuit of the gate line GL corresponding to one line may be represented by resistors R and capacitors C. FIG. The resistors R constitute a resistance of the gate line GL, and a value thereof is determined by the material constituting the gate line GL, length, width, and thickness. The capacitance value of the capacitor C is determined by adding the capacitance value of the gate electrodes of the TFTs, the capacitance value between the electrodes included in the liquid crystal cell Clc, and the capacitance value between the gate line GL and the data line DL. do. The line delay occurs in the gate signal GS generated by the gate driver 34 by the resistor R and the capacitor C. In order to compensate for this line delay, a compensation part 35 is formed at the center of the gate line GL. This compensator 35 is formed of a buffer as shown in FIG. Here, the n / 2th gate signal is input to the non-inverting (+) input terminal of the buffer, the inverting (-) input terminal is connected to the output terminal and the feedback, and the (n + 1) / 2th gate to the output terminal. The signal is output. That is, the n / 2-th gate signal of which the gate signal GS is relatively distorted is input to the input terminal of the compensator 35, and the compensator 35 compensates for this and is equal to the gate signal GS of the input terminal. The (n + 1) / 2th gate signal is generated. Accordingly, the gate signal GSn in which the distorted signal is compensated for appears at the right end of the gate line GL far from the input terminal of the gate signal GS. Since the input gate signal GS and the gate signal GSn at the right end are the same as illustrated in FIG. 7, the voltage charged in the liquid crystal cell corresponding to the input end and the right end is the same.

The compensation unit 35 may be formed at any position of the gate line GL as well as the center portion of the gate line GL, and a plurality of compensation units 35 may be formed.

8 is a diagram illustrating a liquid crystal display according to a second exemplary embodiment of the present invention.

The liquid crystal display shown in FIG. 8 has the same components as the liquid crystal display shown in FIG. 4 except that the compensator 35 is formed on the data line DL instead of the gate line GL. Equipped.

The compensator 35 formed at the center of the data line DL is formed as a buffer so that the n / 2th data signal is input to the non-inverting (+) input terminal of the buffer, and the inverting (-) input terminal is the output terminal. And (n + 1) / 2th data signal is output to the output terminal. That is, the n / 2-th data signal of which the data signal GS is relatively distorted is input to the input terminal of the compensator 35, and the compensator 35 compensates for the same (n +) as the gate signal of the input terminal. 1) A second data signal is generated. Accordingly, at the last end of the data line DL far from the input terminal of the data signal, a data signal compensated for the distorted signal appears. As a result, distortion of the data signal can be prevented and the image is improved.

As described above, the liquid crystal display according to the present invention forms a compensating portion in the center of the signal line located in the effective display area. This compensation unit can prevent signal delay and improve the image quality.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (4)

A gate line to which a gate signal is supplied; And a buffer formed on said gate line in an effective display area. The method of claim 1, And the buffer is formed at the center of the gate line. The data line to which the data is supplied, And a buffer formed on said data line in an effective display area. The method of claim 3, wherein And the buffer is formed at the center of the data line.