KR20030054308A - Method for fabricating bottom electrode in capacitor - Google Patents
Method for fabricating bottom electrode in capacitor Download PDFInfo
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- KR20030054308A KR20030054308A KR1020010084449A KR20010084449A KR20030054308A KR 20030054308 A KR20030054308 A KR 20030054308A KR 1020010084449 A KR1020010084449 A KR 1020010084449A KR 20010084449 A KR20010084449 A KR 20010084449A KR 20030054308 A KR20030054308 A KR 20030054308A
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- Prior art keywords
- lower electrode
- capacitor
- insulating film
- insulating layer
- film
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000003990 capacitor Substances 0.000 title abstract description 49
- 238000004519 manufacturing process Methods 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000011521 glass Substances 0.000 claims abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 10
- 239000010408 film Substances 0.000 description 43
- 239000011229 interlayer Substances 0.000 description 16
- 239000010410 layer Substances 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 230000015654 memory Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000000635 electron micrograph Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013043 chemical agent Substances 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
본 발명은 반도체 집적회로의 제조방법에 관한 것으로, 특히 반도체 소자의 캐패시터 하부전극을 제조하는 공정에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a process for manufacturing a capacitor lower electrode of a semiconductor device.
반도체 소자, 특히 DRAM(Dynamic Random Access Memory)의 반도체 메모리의 집적도가 증가함에 따라 정보 기억을 위한 기본 단위인 메모리 셀의 면적이 급격하게 축소되고 있다.As the degree of integration of semiconductor devices, in particular DRAM (Dynamic Random Access Memory) semiconductor memories, increases, the area of memory cells, which are basic units for information storage, is rapidly being reduced.
이러한 메모리 셀 면적의 축소는 셀 캐패시터의 면적 감소를 수반하여, 센싱 마진과 센싱 속도를 떨어뜨리고, α-입자에 의한 소프트 에러(Soft Error)에 대한 내구성이 저하되는 문제점을 유발하게 된다. 따라서, 제한된 셀 면적에서 충분한 정전용량을 확보할 수 있는 방안이 필요하게 되었다.Such a reduction in the memory cell area is accompanied by a reduction in the area of the cell capacitor, thereby lowering the sensing margin and the sensing speed, and causes a problem that the durability against soft errors caused by α-particles is degraded. Accordingly, there is a need for a method capable of securing sufficient capacitance in a limited cell area.
캐패시터의 정전용량(C)은 하기의 수학식 1과 같이 정의된다.The capacitance C of the capacitor is defined as in Equation 1 below.
여기서, ε은 유전률, As는 전극의 유효 표면적, d는 전극간 거리를 각각 나타낸 것이다. 따라서, 제한된 면적에서 캐패시터의 정전용량을 늘리기 위해서는전극의 표면적이 최대한 넓게 되도록 캐패시터의 구조를 3차원으로 형성해 왔다.Is the dielectric constant, As is the effective surface area of the electrode, and d is the distance between the electrodes. Therefore, in order to increase the capacitance of the capacitor in a limited area, the structure of the capacitor has been formed in three dimensions so that the surface area of the electrode is as wide as possible.
3차원 캐패시터의 구조에는 콘케이브 구조, 실린더 구조, 다층 핀 구조이 있으나 이중에서 콘케이브 구조가 가장 보편적으로 사용되고 있다. 그러나, 콘케이브 구조등과 같이 3차원으로 캐패시터를 형성하는 방법도 반도체 소자가 초고집적화 되면서 전극의 유효 표면적을 증대시키는데 한계를 보이고 있다.The three-dimensional capacitor structure includes a concave structure, a cylinder structure, and a multilayer fin structure, but a concave structure is most commonly used. However, a method of forming a capacitor in three dimensions, such as a concave structure, has also shown a limitation in increasing the effective surface area of an electrode as the semiconductor device becomes very high density.
도1a는 종래기술에 따른 캐패시터를 형성하기 위한 캐패시터홀의 단면을 나타내는 전자현미경 사진이다.1A is an electron micrograph showing a cross section of a capacitor hole for forming a capacitor according to the prior art.
도1a에 도시된 바와 같이, 종래에 콘케이브 캐패시터를 형성하기 위해, 콘택 타입(contact type)의 마스크를 이용하여 단면 모양을 타원형으로 하여 캐패시터 홀을 형성한후 캐패시터홀에 하부전극, 유전체박막, 상부전극을 형성하였다.As shown in FIG. 1A, in order to form a concave capacitor in the related art, a capacitor hole is formed by elliptical cross-sectional shape using a contact type mask and then a lower electrode, a dielectric thin film, An upper electrode was formed.
도1b는 종래기술에 따른 콘케이브 캐패시터 하부전극을 나타내는 도면이다.Figure 1b is a view showing a concave capacitor lower electrode according to the prior art.
도1b을 참조하여 살펴보면, 반도체기판(10)상에 제1 층간절연막(11)을 형성하고, 이어서, 캐패시터를 형성할 높이 만큼 제2 층간절연막(12)을 형성한다.Referring to FIG. 1B, the first interlayer insulating film 11 is formed on the semiconductor substrate 10, and then the second interlayer insulating film 12 is formed to a height sufficient to form a capacitor.
캐패시터 형성영역의 제2 층간절연막(12)을 식각해서 캐패시터 홀(13)을 형성하고, 이어서, 캐패시터 홀(13)에 하부전극, 유전체 박막 상부전극을 차례로 적층하여 캐패시터를 형성하게 된다.The second interlayer insulating film 12 in the capacitor formation region is etched to form the capacitor hole 13, and then the lower electrode and the dielectric thin film upper electrode are sequentially stacked on the capacitor hole 13 to form a capacitor.
그러나, 반도체 소자가 고집화 되어 갈수록 디자인 룰이 감소함에 따라 캐패시터의 하부전극 자체의 CD(critical dimention)는 계속 감소되고 있다.However, as semiconductor devices become more highly integrated, as the design rules decrease, the critical dimention (CD) of the lower electrode of the capacitor itself continues to decrease.
0.13um 이하의 기술에서는 캐패시터홀의 감광막 패턴을 위한 포토리소그래피 공정에서 해상도 한계에 다다르게 되고, 이에 따라 콘택홀 타입의 마스크를 이용하여 캐패시터 홀을 정상적으로 구현하는 것이 어려우며, 캐패시터 홀에 전극을 형성할 때에도 캐패시터 홀간의 생기는 단락현상을 방지하기가 어렵다.In the technology of 0.13um or less, the resolution limit is reached in the photolithography process for the photoresist pattern of the capacitor hole. Therefore, it is difficult to properly implement the capacitor hole using a contact hole type mask, and even when forming an electrode in the capacitor hole. It is difficult to prevent short circuiting between holes.
또한, 제한된 면적에서 캐패시터의 일정한 정전용량을 충족시키기 위해 캐패시터 홀의 높이를 증가시키고 있으나, 캐패시터의 홀의 어스펙트 비(aspect ratio)가 18 이상인 경우는 패터닝 공정이 한계에 다달아 있다.In addition, although the height of the capacitor hole is increased to satisfy the constant capacitance of the capacitor in a limited area, the patterning process is approaching its limit when the aspect ratio of the hole of the capacitor is 18 or more.
본 발명은 식각 공정의 마진을 증가시키고, 같은 높이에서 보다 표면적이 증가된 캐패시터 하부전극 제조방법을 제공함을 목적으로 한다.An object of the present invention is to increase the margin of the etching process, and to provide a method for manufacturing a capacitor lower electrode having an increased surface area at the same height.
도1a는 종래기술에 따른 콘케이브 캐패시터를 형성하기 위한 캐패시터홀의 단면을 나타내는 전자현미경 사진.1A is an electron micrograph showing a cross section of a capacitor hole for forming a concave capacitor according to the prior art.
도1b는 종래기술에 따른 반도체 소자의 콘케이브 캐패시터 하부전극을 나타내는 단면도.1B is a cross-sectional view showing a concave capacitor lower electrode of a semiconductor device according to the prior art;
도2a 내지 도2f는 본 발명의 바람직한 실시예에 따른 콘케이브 캐패시터 하부전극 제조방법을 나타내는 도면.2A to 2F illustrate a method of manufacturing a concave capacitor lower electrode according to a preferred embodiment of the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
20 : 기판20: substrate
21 : 제1 층간절연막21: first interlayer insulating film
22 : 제2 층간절연막22: second interlayer insulating film
23 : 감광막23: photosensitive film
24 : Low-k 막24: Low-k membrane
25 : 산화막 패턴25: oxide film pattern
A : 캐패시터 홀A: Capacitor Hall
상기의 목적을 달성하기 위한 본 발명의 일측면에 따르면, 기판 상부에 캐패시터가 형성된 높이만큼 제1 절연막을 형성하는 단계; 상기 제1 절연막을 라인 형태로 선택적 식각하여 패터닝하는 단계; 상기 제1 절연막과 고식각선택비를 가지는 제2 절연막으로 패터닝된 상기 제2 절연막이 덮히도록 형성하는 단계; 및 패터닝된 상기 제1 절연막과 교차하도록 라인형태로 상기 제2 절연막을 선택적으로 식각하여 캐패시터가 형성될 홀을 형성하는 단계를 포함하는 하부전극 제조방법이 제공된다.According to an aspect of the present invention for achieving the above object, the step of forming a first insulating film as high as the capacitor formed on the substrate; Selectively etching and patterning the first insulating layer in a line form; Forming a second insulating film patterned with the first insulating film and a second insulating film having a high etching selectivity; And selectively etching the second insulating film in a line shape to intersect the patterned first insulating film to form a hole in which a capacitor is to be formed.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
도2a 내지 도2f는 본 발명의 바람직한 실시예에 따른 콘케이브 캐패시터 하부전극 제조방법을 나타내는 도면이다.2A to 2F illustrate a method of manufacturing a concave capacitor lower electrode according to a preferred embodiment of the present invention.
콘케이브 캐패시터 하부전극 제조방법은 먼저 도2a에 도시된 바와 같이, 반도체 기판(20)상에 제1 층간절연막(21)을 형성하고, 이후 콘케이브 캐패시터를 형성할 높이 만큼 실리콘산화막으로 제2 층간절연막(22)을 형성한다. 이어서 감광막(23)을 제2 층간절연막(22)상부에 도포한다. 여기서 제2 층간절연막(22)으로 사용되는 산화막의 높이는 10000 ~ 25000Å 범위로 한다.In the method of manufacturing a concave capacitor lower electrode, first, as shown in FIG. 2A, a first interlayer insulating film 21 is formed on a semiconductor substrate 20, and then a second interlayer is formed of a silicon oxide film to a height sufficient to form a concave capacitor. The insulating film 22 is formed. Subsequently, a photosensitive film 23 is applied over the second interlayer insulating film 22. Here, the height of the oxide film used as the second interlayer insulating film 22 is in the range of 10000 to 25000 kPa.
이어서, 도2b에 도시된 바와 같이, 포토리소그래피를 이용하여 캐패시터 하부전극의 한쪽 축에 해당하는 라인(Line) 타입으로 감광막(23)을 패터닝한다.Subsequently, as illustrated in FIG. 2B, the photosensitive film 23 is patterned in a line type corresponding to one axis of the capacitor lower electrode using photolithography.
이어서, 도2c를 참조하여 살펴보면, 패터닝된 감광막(23)을 이용하여 제2 층간절연막(22)를 건식식각 공정을 진행하고, 잔류하는 감광막(23)을 제거한다. 여기서 C4F8CH2F2C5F8C4F6등 다량의 폴리머를 유발하는 가스를 이용하여감광막에 대한 선택비를 유지하는 조건으로 건식식각 공정을 진행한다.Subsequently, referring to FIG. 2C, the second interlayer insulating layer 22 may be subjected to a dry etching process using the patterned photoresist 23 to remove the remaining photoresist 23. Here, the dry etching process is performed under the condition of maintaining the selectivity to the photoresist using a gas that causes a large amount of polymer such as C 4 F 8 CH 2 F 2 C 5 F 8 C 4 F 6 .
이러한 라인 타입의 패터닝은 종래의 타원형태(비대칭 홀타입)의 패터닝에 비해 포토리소그래피와 식각공정의 마진(margin)을 증가시킨다.Such line type patterning increases the margin of photolithography and etching processes as compared to the conventional elliptical (asymmetric hole type) patterning.
이어서, 도2d를 참조하여 살펴보면, 패터닝된 라인타입의 제2 층간절연막(22) 상부에 코팅되도록 저유전율 절연막(low-k)(24)을 형성한다. 이 때패터닝된 제2 층간절연막(22) 상부로 1000Å정도 저유전율막(24)이 형성되도록 한다.Next, referring to FIG. 2D, a low dielectric constant (low-k) 24 is formed to be coated on the patterned line type second interlayer insulating layer 22. At this time, the low dielectric constant film 24 is formed on the patterned second interlayer insulating film 22 by about 1000 Å.
이때 플로우 특성이 우수한 저유전율막(24)은 갭필(Gap-fill)과 상부평탄화를 동시에 수행하는 것을 가능하게 한다. 여기서 저유전율막(24)은 폴리머(polymer) 계열의 SOG(spin on glass) 타입을 사용하는 것이 바람직하며 , 여기에 해당하는 제품으로는 Silk, BCB, FLARE등이 있다.At this time, the low dielectric constant film 24 having excellent flow characteristics makes it possible to simultaneously perform gap fill and top planarization. Here, the low dielectric constant film 24 preferably uses a polymer-type spin on glass (SOG) type, and the corresponding products include silk, BCB, and FLARE.
이어서 저유전율막(24) 패터닝에 필요한 하드마스크층으로 실리콘산화막(25)을 증착한다. 이 때 실리콘 산화막을 대신하여 실리콘질화막을 증착할 수 있다.Subsequently, a silicon oxide film 25 is deposited as a hard mask layer for patterning the low dielectric constant film 24. In this case, a silicon nitride film may be deposited instead of the silicon oxide film.
이어서, 도2e를 참조하여 살펴보면, 이미 패터닝된 라인 타입의 제2 층간절연막(22)에 수직한 방향으로 실리콘 산화막(25)을 패터닝한다.Subsequently, referring to FIG. 2E, the silicon oxide film 25 is patterned in a direction perpendicular to the line patterned second interlayer insulating film 22.
즉, 캐패시터 하부전극 다른쪽 측에 해당하는 라인판입의 패턴이 그려진 마스크로 사용한 사진 및 식각 공정을 진행한다.That is, the photolithography process and the etching process are used as a mask on which the line insertion pattern corresponding to the other side of the capacitor lower electrode is drawn.
이어서, 도2f를 참조하여 살펴보면, 패터닝된 실리콘산화막(25)를 하드마스크로 이용하여 저유전율막(24)을 건식식각하여 하부전극이 형성될 홀 영역(A)을 정의한다.Next, referring to FIG. 2F, the low dielectric constant layer 24 is dry-etched using the patterned silicon oxide layer 25 as a hard mask to define a hole region A in which the lower electrode is to be formed.
여기서 저유전율막(24)을 건식식각할 때, 고밀도 또는 고밀도 플라즈마 방식의 식각반응기에서, 산소분위기로 가스화학제를 사용하면, 저유전율막(24)은 실리콘산화막 또는 실리콘질화막에 대해 30:1 이상의 고선택비를 가지므로, 이미 형성되어 있는 실리콘산화막으로 구성된 제2 층간절연막(22) 패턴에 손상없이 그와 수직으로 저유전율막(24) 패턴을 형성할 수 있다. 가스화학제로는 O2/N2/CH4,O2/N2, O2/SO2, O/CO등이 사용할 수 있다.When the low dielectric constant film 24 is dry etched, when the gas chemical is used as the oxygen atmosphere in the high-density or high-density plasma type etching reactor, the low dielectric constant film 24 is 30: 1 or more relative to the silicon oxide film or silicon nitride film. Since it has a high selectivity, the low dielectric constant film 24 pattern can be formed perpendicularly to the second interlayer insulating film 22 pattern formed of the silicon oxide film already formed without being damaged. As a gas chemical agent, O 2 / N 2 / CH 4 , O 2 / N 2 , O 2 / SO 2 , O / CO, and the like can be used.
이어서, 제2 층간절연막(22) 패턴과 저유전율막(24) 패턴으로 형성된 캐패시터 홀에 하부전극, 절연막, 상부전극을 형성시켜 캐패시터를 완성한다.Subsequently, a lower electrode, an insulating film, and an upper electrode are formed in the capacitor hole formed of the second interlayer insulating film 22 pattern and the low dielectric constant film 24 pattern to complete the capacitor.
결국, 제2 층간절연막(22) 패턴과 저유전율막(24) 패턴으로 형성된 사각형 모양의 캐패시터 홀은 종래의 타원형(비대칭 홀 타입)으로 생긴 캐패시터 홀의 패턴에 비해 포토리소그래피(photolithography) 및 식각공정의 마진을 증가시켜 패터닝의 난이도를 감소시키므로 종래에 불가능했던 선폭의 하부전극 패터닝을 가능하게 해주고, 또한 공정안정성을 확보할 수 있도록 해준다.As a result, the rectangular capacitor hole formed of the second interlayer insulating film 22 pattern and the low dielectric constant film 24 pattern has a photolithography and etching process compared to the pattern of the capacitor hole formed by the conventional elliptic (asymmetric hole type). By increasing the margin to reduce the difficulty of patterning, it is possible to pattern the lower electrode of the line width that has not been possible in the past, and also to ensure process stability.
또한, 이렇게 형성된 사각형 모양의 캐패시터 홀 패턴은 해당 선폭에서 표면적을 극대화 하여 동일 높이, 동일 전극을 사용할 경우, 정전용량을 향상시킴으로 하여 소자의 전기적 특성 마진을 향상시킬 수 있다.In addition, the rectangular capacitor hole pattern formed as described above maximizes the surface area at the corresponding line width, thereby increasing the capacitance when the same height and the same electrode are used, thereby improving the electrical characteristic margin of the device.
또한, 이러한 사각형 모양의 캐패시터 홀을 형성하는 공정은 실린터 형태의 캐패시터 제조공정에도 사용될 수 있고, 캐패시터의 구조가 SIS(Silicon Insulator Silicon),MIS(Metal Insulator Silicon) 또는 MIM(Metal Insulator Metal)구조에 모두 적용가능하다.In addition, the process of forming the rectangular capacitor hole may be used in the manufacturing process of the capacitor of the cylinder type, the capacitor structure is SIS (Silicon Insulator Silicon), MIS (Metal Insulator Silicon) or MIM (Metal Insulator Metal) structure All are applicable to.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명에 따라 캐패시터 하부전극을 제조하면, 공정마진이 증가되어 패터닝의 난이도가 해소됨으로서 공정안정성을 확보하고 전극 면적을 확보하는 효과를 거둘 수 있다.When the capacitor lower electrode is manufactured according to the present invention, the process margin is increased, thereby reducing the difficulty of patterning, thereby securing process stability and securing an electrode area.
Claims (7)
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100822581B1 (en) * | 2006-09-08 | 2008-04-16 | 주식회사 하이닉스반도체 | Method of manufacturing a flash memory device |
| US8598711B2 (en) | 2010-07-16 | 2013-12-03 | Hynix Semiconductor Inc. | Semiconductor device and method for forming the same |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100822581B1 (en) * | 2006-09-08 | 2008-04-16 | 주식회사 하이닉스반도체 | Method of manufacturing a flash memory device |
| US7687403B2 (en) | 2006-09-08 | 2010-03-30 | Hynix Semiconductor | Method of manufacturing flash memory device |
| US8598711B2 (en) | 2010-07-16 | 2013-12-03 | Hynix Semiconductor Inc. | Semiconductor device and method for forming the same |
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