KR20030052271A - Method for manufacturing salicide layer of semiconductor device - Google Patents
Method for manufacturing salicide layer of semiconductor device Download PDFInfo
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- KR20030052271A KR20030052271A KR1020010081501A KR20010081501A KR20030052271A KR 20030052271 A KR20030052271 A KR 20030052271A KR 1020010081501 A KR1020010081501 A KR 1020010081501A KR 20010081501 A KR20010081501 A KR 20010081501A KR 20030052271 A KR20030052271 A KR 20030052271A
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- Prior art keywords
- film
- silicide
- gate electrode
- layer
- source
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 62
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 61
- 229910052751 metal Inorganic materials 0.000 claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 125000006850 spacer group Chemical group 0.000 claims abstract description 12
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 238000000137 annealing Methods 0.000 claims description 15
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 229910019001 CoSi Inorganic materials 0.000 claims description 3
- VLJQDHDVZJXNQL-UHFFFAOYSA-N 4-methyl-n-(oxomethylidene)benzenesulfonamide Chemical compound CC1=CC=C(S(=O)(=O)N=C=O)C=C1 VLJQDHDVZJXNQL-UHFFFAOYSA-N 0.000 claims description 2
- 229910005883 NiSi Inorganic materials 0.000 claims description 2
- 229910021340 platinum monosilicide Inorganic materials 0.000 claims description 2
- 229910008484 TiSi Inorganic materials 0.000 claims 1
- 150000002739 metals Chemical class 0.000 claims 1
- 238000010438 heat treatment Methods 0.000 abstract 2
- 239000002019 doping agent Substances 0.000 abstract 1
- 239000010936 titanium Substances 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 7
- 229910052719 titanium Inorganic materials 0.000 description 7
- 229910021341 titanium silicide Inorganic materials 0.000 description 7
- 239000010941 cobalt Substances 0.000 description 6
- 229910017052 cobalt Inorganic materials 0.000 description 6
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 230000002776 aggregation Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- 238000005054 agglomeration Methods 0.000 description 1
- 238000004220 aggregation Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- -1 for example Chemical compound 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052761 rare earth metal Inorganic materials 0.000 description 1
- 150000002910 rare earth metals Chemical class 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823443—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
Abstract
Description
본 발명은 반도체 제조방법에 관한 것으로서, 특히 반도체소자의 살리사이드막 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor, and more particularly, to a method for producing a salicide film of a semiconductor device.
일반적으로 금속 실리사이드는 낮은 저항, 높은 열적 안정성, 현 실리콘 공정과의 적용 등이 용이하여 VLSI 배선 공정에 활발히 적용되고 있다. 더욱이, 게이트 전극 또는 소오스/드레인 접합 표면에 형성되는 실리사이드막은 각각 게이트 전극의 비저항과 소오스/ 드레인의 접촉저항을 낮출 수 있기 때문에 배선 저항을 크게 낮출 수 있는 이점이 있다. 대개 실리사이드의 물질로서 실리콘과 반응하는 희토류 금속을 이용하는데, 예를 들어 텅스텐 실리사이드(WSi2), 티타늄 실리사이드(TiSi2), 코발트 실리사이드(CoSi2) 등이 있다.In general, metal silicides are actively applied to VLSI wiring processes because of low resistance, high thermal stability, and easy application to current silicon processes. Furthermore, the silicide film formed on the gate electrode or the source / drain junction surface can lower the resistivity of the gate electrode and the contact resistance of the source / drain, respectively, and thus, the wiring resistance can be greatly reduced. Rare earth metals that react with silicon are usually used as the material of the silicide, for example, tungsten silicide (WSi 2 ), titanium silicide (TiSi 2 ), cobalt silicide (CoSi 2 ), and the like.
그런데, 게이트 전극의 측벽에 있는 스페이서 절연막에 의해 게이트 전극 및 소오스/드레인 접합 표면에 실리사이드막이 동시에 형성되는 것을 살리사이드(salicide: self-aligned silicide) 공정이라 하는데, 그 제조 공정은 다음과 같다.By the way, a silicide film is formed simultaneously on the gate electrode and the source / drain junction surface by the spacer insulating film on the sidewall of the gate electrode, which is called a salicide (self-aligned silicide) process.
도 1a 내지 도 1g는 종래 기술에 의한 반도체소자의 살리사이드막 제조 공정을 나타낸 공정 순서도이다.1A to 1G are process flowcharts showing a salicide film manufacturing process of a semiconductor device according to the prior art.
우선, 반도체기판으로서 실리콘 기판(10)에 소자분리 및 웰 공정을 진행한 후에 기판 전면에 게이트산화막(미도시함)을 형성한다. 도 1a에 도시된 바와 같이, 게이트산화막 위에 게이트 도전막(12)으로서 도프트 폴리실리콘을 증착한다.First, after the device isolation and the well process are performed on the silicon substrate 10 as a semiconductor substrate, a gate oxide film (not shown) is formed on the entire surface of the substrate. As shown in Fig. 1A, doped polysilicon is deposited as the gate conductive film 12 on the gate oxide film.
그리고 도 1b에 도시된 바와 같이, 게이트 도전막(12) 상부에 게이트 전극 영역을 정의하는 포토레지스트 패턴(14)을 형성한다.As shown in FIG. 1B, a photoresist pattern 14 defining a gate electrode region is formed on the gate conductive layer 12.
그 다음 도 1c에 도시된 바와 같이, 건식 식각 공정으로 포토레지스트 패턴(14)에 맞추어 게이트 도전막(12)을 식각하여 게이트 전극(12a)을 형성한 후에포토레지스트 패턴(14)을 제거한다.Next, as shown in FIG. 1C, the gate conductive layer 12 is etched in accordance with the photoresist pattern 14 by a dry etching process to form the gate electrode 12a, and then the photoresist pattern 14 is removed.
이어서 도 1d에 도시된 바와 같이, 기판 전면에 절연막(16)으로서 실리콘질화막을 증착하고 전면 식각(etch back)하여 게이트 전극(12a) 측벽에 스페이서(16')를 형성한다.Subsequently, as shown in FIG. 1D, a silicon nitride film is deposited on the entire surface of the substrate as the insulating film 16 and etched back to form a spacer 16 ′ on the sidewall of the gate electrode 12a.
그리고 도 1e에 도시된 바와 같이, 결과물 전면에 n형 또는 p형 불순물을 고농도로 이온 주입하여 실리콘 기판(10)내에 소오스/드레인 접합(18)을 형성한다.As shown in FIG. 1E, the source / drain junction 18 is formed in the silicon substrate 10 by ion implantation of high concentration of n-type or p-type impurities on the entire surface of the resultant.
그 다음 도 1f에 도시된 바와 같이, 결과물 전면에 실리사이드용 금속(20)으로서, 티타늄(Ti)을 증착하고 어닐링(annealing) 공정을 실시한다. 그러면 도 1g에 도시된 바와 같이, 스페이서(16')를 제외하고 게이트 전극(12a) 및 소오스/드레인 접합(18)의 실리콘 표면과 티타늄(Ti)이 실리사이드 반응을 하여 티타늄 실리사이드막(TiSi)(22)이 형성된다. 그리고 세정 공정을 실시하여 실리사이드화되지 않은 티타늄을 제거함으로써 종래 살리사이드 공정이 완료된다.Next, as shown in FIG. 1F, titanium (Ti) is deposited as an silicide metal 20 on the entire surface of the resultant, and an annealing process is performed. Then, as shown in FIG. 1G, except for the spacer 16 ′, the silicon surface of the gate electrode 12a and the source / drain junction 18 and the titanium surface Ti undergo a silicide reaction to form a titanium silicide layer (TiSi) ( 22) is formed. The conventional salicide process is then completed by performing a cleaning process to remove unsilicided titanium.
그런데, 종래 기술에 의한 살리사이드막 제조 방법은 소자의 미세화에 의해 게이트 전극의 선폭이 줄어들 경우 게이트 전극 표면에서 실리사이드막의 형성이 어렵고 금속 응집(agglomeration)이 일어나 양질의 실리사이드막을 얻을 수 없었다. 이를 해결하기 위해 게이트 전극을 전면 식각해서 게이트 전극의 노출 표면을 크게하거나 실리사이드 금속 물질을 티타늄 대신에 코발트를 사용하였다.However, according to the prior art method of manufacturing a salicide film, when the line width of the gate electrode is reduced due to the miniaturization of the device, it is difficult to form a silicide film on the surface of the gate electrode and agglomeration of metal occurs to obtain a high quality silicide film. In order to solve this problem, the gate electrode was etched entirely to increase the exposed surface of the gate electrode, or cobalt was used instead of titanium as the silicide metal material.
하지만, 과도한 전면 식각은 게이트 전극의 전기적인 특성을 열화시킬 수 있으며 실리사이드 금속 물질로 코발트를 사용할 경우 코발트를 증착하기전에 세정 작업에 주위를 요하는 단점이 있었다.However, excessive front side etching may degrade the electrical characteristics of the gate electrode, and when cobalt is used as the silicide metal material, there is a disadvantage in that the cleaning operation is required before deposition of cobalt.
본 발명의 목적은 이와 같은 종래 기술의 문제점을 해결하기 위하여 게이트 전극에 실리사이드막을 1차로 형성한 후에 소오스/드레인 접합에 실리사이드막을 2차로 형성함으로써 미세화된 소자에도 양질의 살리사이드막을 형성할 수 있는 반도체소자의 살리사이드막 제조방법을 제공하고자 한다.An object of the present invention is to solve the problems of the prior art by forming a silicide film on the gate electrode first, and then a silicide film on the source / drain junctions to form a high quality salicide film on the micronized device. It is to provide a method for producing a salicide film of the device.
이러한 목적을 달성하기 위하여 본 발명은 게이트 전극 및 소오스/드레인 접합 표면에 각각 실리사이드막을 갖는 트랜지스터의 제조 방법에 있어서, 반도체 기판에 게이트 도전막을 형성하고 그 위에 제 1금속막을 증착하고 어닐링 공정을 실시하여 제 1실리사이드막을 형성하는 단계와, 제 1실리사이드막과 게이트 도전막을 패터닝하여 게이트 전극을 형성하는 단계와, 게이트 전극 측벽에 스페이서를 형성하는 단계와, 게이트 전극 및 스페이서를 마스크로 삼아 기판내에 이온 주입하여 소오스/드레인 접합을 형성하는 단계와, 반도체 기판 전면에 제 2금속막을 증착하고 어닐링 공정을 실시하여 게이트 전극 및 소오스/드레인 접합 표면에 제 2실리사이드막을 형성한 후에, 실리사이드화되지 않은 금속막을 제거한다.In order to achieve the above object, the present invention provides a method of manufacturing a transistor having a silicide film on a gate electrode and a source / drain junction surface, wherein a gate conductive film is formed on a semiconductor substrate, a first metal film is deposited thereon, and an annealing process is performed. Forming a first silicide layer, patterning the first silicide layer and the gate conductive layer to form a gate electrode, forming a spacer on the sidewall of the gate electrode, implanting ions into the substrate using the gate electrode and the spacer as a mask Forming a source / drain junction, depositing a second metal film on the entire surface of the semiconductor substrate, and performing an annealing process to form a second silicide film on the gate electrode and the source / drain junction surface, and then removing the unsilicided metal film. do.
도 1a 내지 도 1g는 종래 기술에 의한 반도체소자의 살리사이드막 제조 공정을 나타낸 공정 순서도,1A to 1G are process flowcharts showing a salicide film manufacturing process of a semiconductor device according to the prior art;
도 2a 내지 도 2f는 본 발명에 따른 반도체소자의 실리사이드막 제조 공정을 나타낸 공정 순서도.2A to 2F are process flowcharts showing a silicide film manufacturing process of a semiconductor device according to the present invention;
＜도면의 주요부분에 대한 부호의 설명＞<Description of the code | symbol about the principal part of drawing>
100 : 반도체 기판 102 : 게이트 도전막100 semiconductor substrate 102 gate conductive film
104 : 제 1금속층 106 : 포토레지스트 패턴104: first metal layer 106: photoresist pattern
108 : 실리콘 질화막 110 : 소오스/드레인 접합108: silicon nitride film 110: source / drain junction
112 : 제 2 금속막112: second metal film
이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 2a 내지 도 2f는 본 발명에 따른 반도체소자의 실리사이드막 제조 공정을 나타낸 공정 순서도이다.2A to 2F are process flowcharts illustrating a silicide film manufacturing process of a semiconductor device according to the present invention.
우선, 반도체기판으로서 실리콘 기판(100)에 소자분리 및 웰 공정을 진행한후에 기판 전면에 게이트산화막(미도시함)을 형성한다. 그리고 도 2a에 도시된 바와 같이, 게이트산화막 위에 게이트 도전막(102)으로서 도프트 폴리실리콘을 증착한다. 그 위에 그 위에 실리사이드용 제 1금속막(104)으로서 코발트를 형성한다.First, after a device isolation and a well process are performed on the silicon substrate 100 as a semiconductor substrate, a gate oxide film (not shown) is formed on the entire surface of the substrate. 2A, doped polysilicon is deposited as the gate conductive film 102 on the gate oxide film. Cobalt is formed thereon as the first metal film 104 for silicide.
도 2b에 도시된 바와 같이, 어닐링 공정을 실시하여 제 1금속막(104)과 실리콘이 실리사이드 반응하여 제 1실리사이드막(104')을 형성한다. 이에 따라, 본 발명은 고집적화 기술에 따라 게이트 전극의 선폭이 축소될지라도 미리 게이트 도전막 상부 전면에 실리사이드막을 형성함으로써 좁은 면적에서 일어나는 금속 응집 현상을 방지할 수 있다. 제 1실리사이드막(104') 상부에 게이트 전극 영역을 정의하는 포토레지스트 패턴(106)을 형성한다.As shown in FIG. 2B, an annealing process is performed to form a first silicide layer 104 ′ by silicide reaction between the first metal layer 104 and silicon. Accordingly, in the present invention, even if the line width of the gate electrode is reduced according to the high integration technology, a silicide film may be formed on the entire upper surface of the gate conductive film in advance to prevent metal aggregation from occurring in a narrow area. A photoresist pattern 106 defining a gate electrode region is formed on the first silicide layer 104 ′.
그 다음 도 2c에 도시된 바와 같이, 건식 식각 공정으로 포토레지스트 패턴(106)에 맞추어 제 1실리사이드막(104') 및 게이트 도전막(102)을 식각하여 게이트 전극(102a)을 형성한 후에 포토레지스트 패턴(106)을 제거한다. 그리고 기판 전면에 절연막으로서 실리콘질화막(108)을 증착한다.Next, as shown in FIG. 2C, the first silicide layer 104 ′ and the gate conductive layer 102 are etched in accordance with the photoresist pattern 106 by a dry etching process to form the gate electrode 102a. The resist pattern 106 is removed. Then, the silicon nitride film 108 is deposited as an insulating film over the entire substrate.
이어서 도 2d에 도시된 바와 같이, 전면 식각 공정으로 실리콘질화막(108)을 식각 해서 게이트 전극(102a) 측벽에 스페이서(108a)를 형성한다. 그리고 결과물 전면에 n형 또는 p형 불순물을 고농도로 이온 주입하여 실리콘 기판(100)내에 소오스/드레인 접합(110)을 형성한다.Subsequently, as shown in FIG. 2D, the silicon nitride film 108 is etched by the front side etching process to form the spacer 108a on the sidewall of the gate electrode 102a. The source / drain junction 110 is formed in the silicon substrate 100 by ion implantation of n-type or p-type impurities in high concentration on the entire surface of the resultant.
여기서, 게이트 전극(102a) 측벽에 형성된 스페이서(108a)는 산화막 또는 질화막 중 어느 하나이거나 산화막과 질화막이 순차적으로 형성된다.Here, the spacer 108a formed on the sidewall of the gate electrode 102a may be either an oxide film or a nitride film, or an oxide film and a nitride film are sequentially formed.
계속해서 도 2e에 도시된 바와 같이, 결과물 전면에 실리사이드용 제 2금속막(112)으로서, 티타늄(Ti)을 증착한다. 이때, 제 2금속막(112)은 제 1금속막(104), 예를 들어 코발트와 동일할 수 있거나 다른 실리사이드용 금속 물질로 대체할 수도 있다.Subsequently, as shown in FIG. 2E, titanium (Ti) is deposited as the silicide second metal film 112 on the entire surface of the resultant product. In this case, the second metal film 112 may be the same as the first metal film 104, for example cobalt, or may be replaced with another silicide metal material.
그리고나서 도 2f에 도시된 바와 같이, 어닐링 공정을 실시한다. 이에 따라, 소오스/드레인 접합(110)의 실리콘 표면과 티타늄(Ti)이 실리사이드 반응을 하여 티타늄 실리사이드막(TiSi)인 제 2실리사이드막(112')이 형성되며 이와 동시에, 게이트 전극(102a) 상부인 제 1실리사이드막(104')에도 제 2실리사이드막(112')이 형성된다. 그리고 세정 공정을 실시하여 실리사이드화되지 않은 티타늄을 제거함으로써 본 발명의 살리사이드 공정을 완료한다.Then, as shown in FIG. 2F, an annealing process is performed. Accordingly, the silicon surface of the source / drain junction 110 reacts with the titanium (Ti) to form a silicide reaction, thereby forming a second silicide layer 112 ′, which is a titanium silicide layer (TiSi), and at the same time, the upper portion of the gate electrode 102a. A second silicide film 112 'is also formed in the first silicide film 104'. The cleaning process is then performed to remove the unsilicided titanium to complete the salicide process of the present invention.
한편, 본 실시예는 제 1실리사이드막(104')과 제 2실리사이드막(112')을 티타늄 실리사이드(TiSi)로 한정하였지만, 이들 실리사이드막은 당업자에 의해 변경이 가능하다. 바람직하게는 제 1실리사이드막(104') 및 제 2실리사이드막(112')은 TiSi, CoSi, PtSi, NiSi 중에서 어느 하나로 한다.In the present embodiment, the first silicide film 104 'and the second silicide film 112' are limited to titanium silicide (TiSi), but these silicide films can be changed by those skilled in the art. Preferably, the first silicide film 104 'and the second silicide film 112' are made of any one of TiSi, CoSi, PtSi, and NiSi.
그리고, 제 1실리사이드막(104') 및 제 2실리사이드막(112')은 동일한 어닐링 조건에서 진행될 수 있으나, 제 1실리사이드막(104')의 어닐링은 저온에서 진행하고 제 2실리사이드막(112')의 어닐링은 고온에서 진행할 수도 있다. 이때, 저온 어닐링에 의해 불완전한 상구조를 갖는 제 1실리사이드막(104')은 이후 제 2실리사이드막(112')을 위한 고온 어닐링 공정에 의해 안정된 상태로 상변이한다.The first silicide film 104 'and the second silicide film 112' may be processed under the same annealing conditions, but the annealing of the first silicide film 104 'proceeds at a low temperature and the second silicide film 112' Annealing of) may proceed at a high temperature. At this time, the first silicide film 104 'having an incomplete phase structure by low temperature annealing is later changed to a stable state by a high temperature annealing process for the second silicide film 112'.
이상 설명한 바와 같이, 본 발명은 미세한 선폭을 갖는 게이트 전극에 실리사이드막을 1차로 형성한 후에 다시 게이트 전극 및 소오스/드레인 접합에 실리사이드막을 2차로 형성함으로써 미세화된 소자에도 양질의 살리사이드막을 형성할 수 있어 게이트 전극 및 소오스/드레인 접합의 전기 저항을 낮출 수 있다.As described above, according to the present invention, a high-quality salicide film can be formed in a micronized device by first forming a silicide film on the gate electrode having a fine line width and then forming a second silicide film on the gate electrode and the source / drain junction. The electrical resistance of the gate electrode and the source / drain junction can be lowered.
따라서, 본 발명은 게이트 전극의 표면적을 늘리기 위한 과도한 식각 공정을 생략할 수 있고 게이트 전극 및 소오스/드레인 접합 영역에 형성되는 각각의 실리사이드막의 종류를 소자 특성에 맞추어 다르게 제조할 수도 있다.Accordingly, the present invention can omit an excessive etching process for increasing the surface area of the gate electrode and different types of silicide films formed in the gate electrode and the source / drain junction region can be manufactured differently according to the device characteristics.
한편, 본 발명은 상술한 실시예에 국한되는 것이 아니라 후술되는 청구범위에 기재된 본 발명의 기술적 사상과 범주내에서 당업자에 의해 여러 가지 변형이 가능하다.On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.
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