KR20030051920A - Level shift circuit - Google Patents

Abstract

PURPOSE: A level shift circuit is provided to perform a level shift operation by comparing an input voltage with a reference voltage to control only the reference voltage. CONSTITUTION: A level shift circuit includes a level shift portion and a current compensation portion. The level shift portion is formed with a plurality of TFTs(Thin Film Transistors) in order to compare an input voltage with a reference voltage. The level shift portion outputs the first power more than a high level if the input voltage is the high level more than the reference voltage whereas it outputs the second power more than a low level if the input voltage is the low level less than the reference voltage. The current compensation portion compensates the amount of current of a reduced output voltage when threshold voltages of the TFTs are more than a particular value.

Description

LEVEL SHIFT CIRCUIT}

The present invention relates to a driving circuit of a liquid crystal display device using polysilicon, and more particularly, to a level shift circuit suitable for being embedded on a polysilicon liquid crystal panel.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix and a driving circuit for driving the liquid crystal panel. In the liquid crystal panel, the gate lines and the data lines are arranged to cross each other, and the liquid crystal cells are positioned in an area where the gate lines and the data lines cross each other. The liquid crystal panel is provided with pixel electrodes and a common electrode for applying an electric field to each of the liquid crystal cells. Each of the pixel electrodes is connected to any one of the data lines via source and drain terminals of a thin film transistor, which is a switching element. The gate terminal of the thin film transistor is connected to any one of the gate lines through which the pixel voltage signal is applied to the pixel electrodes of one line. The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, and a common voltage generator for driving the common electrode. The gate driver sequentially supplies the scanning signals to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. The data driver supplies a video signal to each of the data lines whenever a gate signal is supplied to any one of the gate lines. The common voltage generator supplies a common voltage signal to the common electrode. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the video signal for each liquid crystal cell.

Thin film transistors used in such liquid crystal display devices are classified into amorphous silicon type and polysilicon type depending on whether amorphous silicon and poly silicon are used as semiconductor layers. The amorphous silicon thin film transistor has an advantage that the amorphous silicon film has a relatively uniformity and stable characteristics, but it is difficult to apply when the pixel density is improved because the charge mobility is relatively small. In addition, in the case of using an amorphous silicon type thin film transistor, peripheral driving circuits such as the gate driver and the data driver have to be manufactured separately and mounted on the liquid crystal panel, which has a disadvantage in that the manufacturing cost of the liquid crystal display device is high. On the other hand, as the polysilicon thin film transistor has a high charge mobility, the pixel density is not difficult to increase and the peripheral driving circuits are mounted on the liquid crystal panel to reduce manufacturing costs. Accordingly, a liquid crystal display device using a polysilicon thin film transistor has been in the spotlight.

In fact, the polysilicon liquid crystal panel incorporating a driving circuit includes an image display unit 22, a data shift register array 12, a data level shifter array 14, and a sampling switch array 16 as shown in FIG. And a gate driver including a gate shift register array 18 and a gate level shifter array 20.

The data shift register array 12, the data level shifter array 14, the sampling switch array 16, the gate shift register array 18, and the gate level shifter array 20 included in the liquid crystal panel 10 may include an image display unit ( 22) and a thin film transistor process including a polysilicon process.

In the image display unit 22, liquid crystal cells LC are arranged in a matrix to display an image. Each of the liquid crystal cells LC includes a thin film transistor TFT using polysilicon as a switching element connected to an intersection of the gate line GL and the data line DL. As the thin film transistor TFT uses polysilicon 100 times faster than amorphous silicon, the liquid crystal cells LC are driven in a point-sequential manner. The gate lines GL are supplied with scan pulses through the gate level shifter array 20. The data lines DL receive a video signal through the sampling switch array 16.

The gate shift register array 18 is composed of a plurality of gate shift registers (not shown), each having an output terminal connected to a plurality of level shifters included in the gate level shifter array 20. The gate shift registers shift the input gate start pulse (GSP) to sequentially supply the shift pulses to the level shifters.

The gate level shifter array 20 is composed of a plurality of level shifters (not shown) respectively connected between the gate shift register and the gate line GL. The level shifters supply a shift pulse from the gate shift register to the gate lines GL as a scan pulse by increasing its swing voltage. For example, the gate level shifter array 20 level shifts a shift signal input with a swing voltage of about 10V from the gate shift register array 18 to have a swing width of about 18V and outputs it as a scan pulse.

The data shift register array 12 is composed of a plurality of data shift registers (not shown), each having an output terminal connected to a plurality of level shifters included in the data level shifter array 14. The data shift registers shift the input data start pulses (DSP) to sequentially supply shift signals to the level shifters.

The data level shifter array 14 is composed of a plurality of level shifters (not shown) respectively connected between the data shift register and the sampling switch of the sampling switch array 16. Level shifters supply a shift pulse from the data shift register to the sampling switch by increasing its swing voltage. For example, the data level shifter array 14 level shifts a shift pulse input with a swing voltage of about 10V from the data shift register array 12 to have a swing width of about 18V including a negative voltage. Output by sampling signal.

The sampling switch array 16 is composed of a plurality of sampling switches (not shown), each having an output terminal connected to the data lines DL, and driven by a sampling signal input from the data level shifter array 14. The sampling switches sequentially sample the video signal input from the control chip 42 in response to the sampling signal and supply the data signal to the data lines DL.

In the polysilicon liquid crystal panel, in order to embed the data driver and the gate driver, the number of thin film transistors and the number of required power sources must be relatively small. In particular, the data driver must have a fast response characteristic that can respond to a frequency of several MHz band in order to sample the video signal in a point-sequential manner.

In particular, the following level shift circuits have been proposed in order to embed a level shifter on a liquid crystal panel to level shift signals of low voltage levels generated by a general purpose low voltage controller to reduce power consumption.

Referring to FIG. 2, a conventional level shift circuit includes a first terminal having a gate terminal commonly connected to an input voltage VIN input line and connected in series between a first power supply VDD input line and a third power supply VSS2 input line. A gate terminal is commonly connected to the PMOS transistor MPT1 and the first NMOS transistor MNT1 and the first node N1 between the first PMOS transistor MPT1 and the first NMOS transistor MNT1 and the first power source VDD. ) Between the second PMOS transistor MPT2 and the second NMOS transistor MNT2 connected in series between the input line and the third power supply VSS2 input line, and between the second PMOS transistor MPT2 and the second NMOS transistor MNT2. A third PMOS transistor MPT3 connected between an input line of the first power supply VDD and a third node N3 and a fourth node N4 that is an output node, with a gate terminal connected to the second node N2 of the second node N2 of FIG. The third N-type MOS thin film transistor connected to the third node N3 and the second power source VSS1 input line A fourth PMOS transistor MPT4 and a third node connected to the master MNT3 and the first node N1 and connected between the first power supply VDD input line and the fourth node N4. A gate terminal is connected to N3 and a fourth NMOS transistor MNT4 is connected between the fourth node N4 and the second power supply VSS1 input line. In addition, the level shift circuit shown in FIG. 2 further includes two inverters INV1 and INV2 connected in series to the fourth node N4. These inverters INV1 and INV2 are commonly connected to the first and second power sources VDD and VSS1.

The level shift circuit having such a configuration swings 10V with the first power supply VDD, -10V with the second power supply VSS1, -4V with the third power supply VSS2, and 0V-5V with the input voltage. Assuming that a pulse voltage is supplied, a pulse voltage having a swing width of -10V to 10V is output as an output voltage.

When the first low-level voltage 0V is input to the input voltage VIN, the first PMOS transistor MPT1 is turned on to supply a second high voltage supplied from the first power source VDD to the first node N1. The voltage of the level 10V is charged. The second NMOS transistor MNT2 is turned on by the second high level voltage 10V charged in the first node N1, and the second NMOS transistor MNT2 is supplied to the second node N2 from the third power source VSS2. The low level voltage (-4V) is charged. The third PMOS transistor MPT3 is turned on by the first low-level voltage (-4V) charged in the second node N2, and the high voltage supplied from the first power source VDD to the third node N3 is provided. The voltage of the level 10V is charged. The fourth NMOS transistor MNT4 is turned on by the second high level voltage 10V charged in the third node N3, and the third low level voltage (-10V) supplied from the second power source VSS1 is provided. ) Is charged to the fourth node N4 which is an output node. In this case, the fourth PMOS transistor MPT4 is turned off by the second high level voltage 10V charged in the first node N1. Accordingly, the third low level voltage-10V charged in the fourth node N4 is supplied to the output voltage VOUT via the first and second inverters INV1 and INV2. As a result, the first low level voltage 0V input to the input voltage VIN is level-shifted to a smaller third low level voltage-10V.

On the contrary, when the first high level voltage 5V is input to the input voltage VIN, the first NMOS transistor MNT1 is turned on and the second node supplied from the third power source VSS2 to the first node N1. The low level voltage (-4V) is charged. The second and fourth PMOS transistors MPT2 and MPT4 are turned on by the second low-level voltage (-4V) charged in the first node N1 to turn on the second node N2 and the fourth node N4. ) Is charged with a second high level voltage 10V supplied from the first power supply VDD. The third PMOS transistor MNT4 is turned off by the second high level voltage 10V charged in the second node N2. At the same time, the third NMOS transistor MNT3 is turned on by the second high level voltage 10V charged in the fourth node N4, and the third low level voltage-10V is applied to the third node N3. This supply turns off the fourth NMOS transistor MNT4. Accordingly, the second high level voltage 10V charged in the fourth node N4 is supplied to the output voltage VOUT via the first and second inverters INV1 and INV2. As a result, the first high level voltage 5V input to the input voltage VIN is level shifted to the second high level voltage 10V.

As described above, the level shift circuit shown in FIG. 2 outputs a level shifted input voltage VIN having a swing width of 0V to 5V to an output voltage VOUT having a swing width of -10V to 10V. However, the level shift circuit shown in FIG. 2 has a disadvantage in that a third power source VSS2 is additionally used as compared to other level shift circuits. In addition, the MOS transistors MNT and MPT included in the level shift circuit shown in FIG. 2 do not operate normally when the threshold voltages of the MOS transistors are changed due to the difficult manufacturing process of polysilicon. Will occur. In particular, when the threshold voltages of the MOS transistors MNT and MPT increase, the turn-on current amount decreases, causing a problem that the output voltage VOUT is attenuated.

In general, polysilicon thin film transistors MNT and MPT having a much higher threshold voltage than amorphous silicon thin film transistors are variable according to the charge mobility of polysilicon. The charge mobility of the polysilicon depends on the size of the grain boundary generated during the crystallization of the polysilicon, and the size of the grain boundary is usually different for each crystallization region of the polysilicon. The thin film transistors MNT and MPT fabricated in the same process may have different threshold voltages depending on the crystallization region, that is, the position formed on the glass. As the threshold voltages of the thin film transistors MNT and MPT are changed for each crystallization region, the threshold voltage is changed for each level shifter circuit. However, the conventional level shift circuit shown in FIG. 2 does not have a compensation method for the case where the threshold voltage is variable, resulting in a problem that the reliability of the level shift circuit is degraded, such as attenuation of the output voltage VOUT.

3 illustrates another level shift circuit embedded on a polysilicon liquid crystal panel.

The level shift circuit shown in FIG. 3 includes a first PMOS transistor MPT1 having a gate and a source terminal commonly connected to a first node N1, and a drain terminal connected to a first power supply VDD supply line, and the first PMOS transistor MPT1. A first NMOS transistor MNT1 having a gate and a drain terminal commonly connected to the node N1 and a source terminal connected to the second power supply VSS supply line, and a gate terminal connected to the first node N1, A second PMOS transistor MPT2 connected between the power supply VDD supply line and the second node N2 as an output node, and a gate terminal connected to the first node N1, and the second node N2 and the input line are connected to each other. A second NMOS transistor MNT2 connected therebetween is provided. In addition, the level shift circuit shown in FIG. 3 further includes two inverters INV1 and INV2 connected in series to the second node N2. These inverters INV1 and INV2 are commonly connected to the first and second power sources VDD and VSS.

The first PMOS and the first NMOS transistors MPT1 and MNT1 connected in series between the first power supply VDD supply line and the second power supply VSS supply line are always turned on to act as voltage dividers. do.

When the low level voltage 0V is input to the input voltage VIN, the second NMOS transistor MNT2 is turned on and the second PMOS transistor MPT2 is turned off so that the output node N2 has a low level. The voltage OV is charged. This low level voltage 0V is outputted to the output voltage VOUT via the first and second inverters INV1 and INV2.

When the high level voltage 5V is input to the input voltage VIN, the second NMOS transistor MNT2 is turned off and the second PMOS transistor MPT2 is turned on so that the first power source is supplied to the output node N2. The high level voltage (VDD) is charged. This high level voltage is output to the output voltage VOUT via the first and second inverters INV1 and INV2.

The level shift circuit having such a configuration has the advantage of not requiring an additional power source and requiring a relatively small number of MOS transistors as compared to the level shift circuit shown in FIG. On the other hand, as the low level of the level shifted output voltage VOUT is fixed to the low level of the input voltage, the level shift range is very limited and the operating frequency is significantly reduced. In addition, when the threshold voltage of the MOS transistor is variable, there is no compensating method as in the level shift circuit shown in FIG. 2, which causes a problem that the reliability of the level shift circuit such as attenuation of the output voltage VOUT is degraded.

Accordingly, an object of the present invention is to provide a level shift circuit capable of compensating for signal attenuation caused by a change in characteristics of a polysilicon transistor.

1 is a block diagram schematically showing the configuration of a conventional polysilicon liquid crystal panel.

FIG. 2 is a level shift circuit diagram included in the level shift array shown in FIG. 1. FIG.

3 is another level shift circuit diagram included in the level shift array shown in FIG.

4 is a level shift circuit diagram according to an embodiment of the present invention.

5 is a level shift circuit diagram according to another embodiment of the present invention.

<Description of Main Parts of Drawing>

10 liquid crystal panel 12 data shift register array

14 data level shifter array 16 sampling switch array

18: gate shift register array 20: gate level shifter array

22: image display unit

In order to achieve the above object, the level shifter circuit according to the present invention is composed of a plurality of thin film transistors and the input voltage is higher than the high level voltage when the input voltage is a high level voltage larger than the reference voltage A level shift unit configured to output a first power and output a second power smaller than the low level voltage when the input voltage is a low level voltage smaller than a reference voltage; It characterized in that it comprises a current compensation unit for compensating the amount of current of the output voltage which decreases because the threshold voltage of the thin film transistors is more than a specific value.

The current compensator is a current mirror connected between the first and second power supply lines to compensate the amount of current of the second power supplied to the level shift unit.

And a second level shift unit configured to level-shift back to the first power source and the second power source using the output voltage of the level shift unit as an input voltage.

The second level shift unit may include first and second inverters connected in series to an output terminal of the level shift unit and receiving first and second power.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 and 5.

4 illustrates a level shifter circuit diagram according to an embodiment of the present invention.

The level shift circuit shown in FIG. 4 compares the input voltage VIN with the reference voltage VREF to output the voltage of any one of the first power supply VDD and the second power supply VSS as the output voltage VOUT. A comparator is provided.

First, the pulse voltage swinging from the first low level to the first high level is supplied to the input voltage VIN, and the voltage of the second high level greater than the first high level is supplied to the first power supply VDD. Assume that VSS is supplied with a second low level voltage smaller than the first low level.

The comparator includes first and second NMOSs connected in parallel to a second node N2 to which a gate terminal is connected to each of an input voltage VIN supply line and a reference voltage VREF supply line, and to which a second power supply VSS is supplied. A first PMOS transistor MPT1 and a first voltage connected in series with the first NMOS transistor MNT1 between the transistors MNT1 and MNT2, the first voltage VDD supply line, and the second node N2. VDD) A second PMOS transistor MPT2 is connected between the supply line and the second node N2 in series with the second NMOS transistor MNT2. Here, the gate terminals of the first and second PMOS transistors MPT1 and MPT2 are commonly connected to the first node N1 connected to the source terminal of the first NMOS transistor MNT1, and the second PMOS and NMOS transistors MPT2, A third node N3 serving as an output node is provided between the MNT2s.

When the first high level voltage greater than the reference voltage VREF is supplied to the input voltage VIN, the first NMOS transistor MNT1 is turned on and the second NMOS transistor MNT2 is turned off. Accordingly, the first node N1 is charged with a second low level voltage from the second power supply VSS via the turned-on first NMOS transistor MNT1. The first and second PMOS transistors MPT1 and MPT2 are turned on by the second low-level voltage charged in the first node N1 to output the output voltage VOUT through the third node N3 as an output node. Is supplied with the second high level voltage from the first power supply VDD.

In contrast, when the first low level voltage smaller than the reference voltage VREF is supplied to the input voltage VIN, the first NMOS transistor MNT1 is turned off and the second NMOS transistor MNT2 is turned on. . Accordingly, the first and second PMOS transistors MPT1 and MPT2 connected to the first power source VDD are turned off, and the third node N3 is turned on through the turned-on second NMOS transistor MNT2. The second low level voltage from the second power supply VSS is supplied and output to the output voltage VOUT.

Here, when the threshold voltages of the transistors constituting the level shift circuit are determined to be greater than or equal to a specific voltage, the second power source VSS supplied to the third node N3 as the amount of current flowing through the second NMOS transistor MNT2 decreases. Is attenuated and supplied.

In order to correct the characteristics of the MOS transistors MNT and MPT, that is, the signal attenuation due to the change of the threshold voltage, the level shift circuit shown in FIG. 4 includes the second node N2 and the second power source VSS included in the comparator. ) And a current compensation unit connected between supply lines.

The current compensator includes a third PMOS transistor MPT3 in which a gate and a source terminal are commonly connected to a fourth node N4 and a drain terminal is connected to a first power supply VDD supply line as a current mirror. A third NMOS transistor MNT3 having a gate and a drain terminal commonly connected to the fourth node N4 and a source terminal connected to the second power supply VSS supply line, and a gate terminal connected to the fourth node N4, A fourth NMOS transistor MNT4 is connected between the second node N2 and the second power supply VSS supply line.

The three MOS transistors MPT3, MNT3, and MNT4 constituting the current compensator are configured in the form of current mirrors, and thus, when the threshold voltages of the MOS transistors MNT and MPT constituting the level shift unit are not uniform, an operation error caused by the current compensator To compensate. In other words, the MOS transistors MPT3, MNT3, and MNT4 of the current compensator have a relatively low threshold voltage of the NMOS transistors MNT constituting the level shifters at a specific position. The amount of current is compensated to keep the voltage relatively high. In addition, when the threshold voltages of the NMOS transistors MNT are relatively high, the amount of current is compensated to maintain the voltage of the second node N2 at a higher value. As a result, the current compensator makes it possible to compensate for differences in operating characteristics resulting from nonuniformity of the threshold voltage.

5 illustrates a level shift circuit according to another embodiment of the present invention.

The level shift circuit shown in FIG. 5 is for performing a level shifting operation in two stages to stabilize the level shifted pulse voltage, and is connected to the output node N3 in comparison with the level shift circuit shown in FIG. A level shift part is further provided. In other words, the level shift circuit shown in Fig. 5 includes: a first level shifter section composed of a comparator; A current compensator for compensating for signal attenuation according to a change in transistor characteristics of the first level shifter; A second level shifter unit is configured to perform a two-level level shifting operation by using the same first and second power sources VDD and VSS as the first level shifter unit.

First, the pulse voltage swinging from the first low level to the first high level is supplied to the input voltage VIN, and the voltage of the second high level larger than the first high level is supplied to the first power supply VDD. It is assumed that the power supply VSS is supplied with a second low level voltage smaller than the first low level.

The first level shifter unit is a comparator, and a gate terminal is connected to each of the input voltage VIN supply line and the reference voltage VREF supply line, and is connected in parallel to the second node N2 to which the second power supply VSS is supplied. A first PMOS transistor MPT1 connected in series with the first NMOS transistor MNT1 between the first and second NMOS transistors MNT1 and MNT2, the first voltage VDD supply line, and the second node N2; And a second PMOS transistor MPT2 connected in series with the second NMOS transistor MNT2 between the first voltage VDD supply line and the second node N2. Here, the gate terminals of the first and second PMOS transistors MPT1 and MPT2 are commonly connected to the first node N1 connected to the source terminal of the first NMOS transistor MNT1, and the second PMOS and NMOS transistors MPT2, A third node N3 serving as an output node is provided between the MNT2s.

The current compensator includes a third PMOS transistor MPT3 in which a gate and a source terminal are commonly connected to a fourth node N4 and a drain terminal is connected to a first power supply VDD supply line as a current mirror. A third NMOS transistor MNT3 having a gate and a drain terminal commonly connected to the fourth node N4 and a source terminal connected to the second power supply VSS supply line, and a gate terminal connected to the fourth node N4, A fourth NMOS transistor MNT4 is connected between the second node N2 and the second power supply VSS supply line.

The second level shifter unit includes a fourth PMOS transistor MPT4 and a fourth gate terminal commonly connected to the third node N3 and connected in series between the first power supply VDD supply line and the second power supply VSS supply line. A first inverter composed of five NMOS transistors MNT5, and a fifth PMOS transistor connected to a third terminal N3 having a gate terminal connected between the first power supply VDD supply line and a sixth node N6; A gate terminal is connected to the fifth node N5 between the MPT5 and the fourth PMOS transistor MPT4 and the fifth NMOS transistor MNT5, and is a seventh node N7 that is a first power supply VDD supply line and an output node. ) And a sixth NMOS transistor MNT6 having a gate and a drain terminal commonly connected to the sixth node N6 and a source terminal connected to the second power supply VSS supply line. And a seventh NMOS transistor having a gate terminal connected to the sixth node N6 and connected between the seventh node N7 and the second power supply VSS supply line. And a second inverter composed of a rotor MNT7.

The three MOS transistors MPT3, MNT3, and MNT4 constituting the current compensator are always turned on so that the threshold voltages of the transistors constituting the level shift circuit are determined to be below a specific voltage so that the transistors are normally driven. The second power source VSS is supplied to the second node N2 of the device.

When the first high level voltage greater than the reference voltage VREF is supplied to the input voltage VIN, the first NMOS transistor MNT1 is turned on and the second NMOS transistor MNT2 is turned off. Accordingly, the first node N1 is charged with the second low level voltage from the second power supply VSS supplied to the second node N2 via the turned-on first NMOS transistor MNT1. The first and second PMOS transistors MPT1 and MPT2 are turned on by the second low-level voltage charged in the first node N1 so that the third node N3, which is an output node of the first level shifter unit, is turned on. The second high level voltage from one power supply VDD is charged.

The fifth NMOS transistor MNT5 is turned on by the second high level voltage charged in the third node N3, and the second low level is supplied from the second power source VSS to the fifth node N5. The voltage is charged. The sixth PMOS transistor MPT6 is turned on by the second low level voltage charged in the fifth node N5, and the fourth and fifth PMOS transistors MPT4 and MPT5 and the sixth and seventh NMOS transistors are turned on. MNT6 and MNT7 are turned off. The seventh node N7, which is an output node, is charged with a second high level voltage from the first power supply VDD by the turned-on sixth PMOS transistor MPT6 and supplied to the output voltage VOUT.

The first high level voltage supplied to the input voltage VIN is level shifted to the second high level voltage supplied from the first power supply VDD in two stages by the first and second level shifters, thereby outputting the output voltage ( The voltage supplied to VOUT is in a state where the first power supply VDD is sufficiently reached.

In contrast, when the first low level voltage smaller than the reference voltage VREF is supplied to the input voltage VIN, the first NMOS transistor MNT1 is turned off and the second NMOS transistor MNT2 is turned on. . Accordingly, the first and second PMOS transistors MPT1 and MPT2 connected to the first power source VDD are turned off, and the third node N3 is turned on through the turned-on second NMOS transistor MNT2. The second low level voltage from the second power supply VSS is charged.

Here, when the threshold voltage of the transistors constituting the level shift circuit is determined to be higher than or equal to a specific voltage, when the amount of current flowing through the second NMOS transistor MNT2 decreases, the current compensation unit increases the amount of current supplied to the second node N2. To compensate. Accordingly, when the second NMOS transistor MNT2 is turned on, the current amount reduced due to the increase in the threshold voltage is compensated for, so that the second power supply VSS supplied to the third node N3 is normally charged.

The fourth and fifth PMOS transistors MPT4 and MPT5 are turned on by the second low-level voltage charged in the third node N3 so that the fifth and sixth nodes N5 and N6 have a first power supply ( The second high level voltage supplied from VDD) is charged. The sixth PMOS transistor MPT6 is turned off by the second high level voltage charged in the fifth node N5. In contrast, the sixth and seventh NMOS transistors MNT6 and MNT7 are turned on by the second high level voltage charged in the sixth node N6, and the seventh node N7 is turned on by the second power source VSS. The supplied second low level voltage is charged. The second low level voltage charged in the second node N2 is supplied to the output voltage VOUT.

The first low level voltage supplied to the input voltage VIN is level shifted to the second low level voltage supplied from the second power supply VSS in two stages by the first and second level shifters, thereby outputting the output voltage ( VOUT is in a state where the second power supply VSS is sufficiently reached.

On the other hand, even when the level shift circuit shown in FIG. 5 is composed of only the first and second level shifters except for the current compensating part, the input voltage VIN is level shifted in two stages so that a stable level shifting voltage can be output. do.

As described above, the level shift circuit according to the present invention can arbitrarily vary the level shift voltage range by adjusting only the reference voltage by level shifting the input voltage with respect to the reference voltage. Such adjustment of the level shift voltage range makes it possible to increase the margin and correction capability and reliability of the level shift circuit in charge of the interface part in a polysilicon liquid crystal panel in which the driving circuit is incorporated.

In addition, the level shift circuit according to the present invention includes a current compensating unit to compensate for signal attenuation due to characteristic changes such as threshold voltages of the transistors, thereby ensuring reliability regardless of the characteristics of the transistors.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (5)

In the level shifter circuit for increasing the swing width of the input voltage and outputting Comprising a plurality of thin film transistors and when the input voltage is a voltage of a high level greater than the reference voltage, and outputs a first power greater than the high level voltage and the input voltage is greater than the reference voltage A level shift unit outputting a second power supply smaller than the low level voltage when the voltage is a low level voltage; And a current compensator for compensating for the amount of current of the output voltage which decreases when the threshold voltages of the thin film transistors are greater than or equal to a specific value. The method of claim 1, The level shift unit includes first and second N-type thin film transistors each having a gate terminal connected to each of the input voltage supply line and the reference voltage supply line, and connected in parallel to the second power supply line; A first P-type thin film transistor connected in series with the first N-type thin film transistor between the first power supply line and the second power supply line; A second P-type thin film transistor connected in series with the second N-type thin film transistor between the first power supply line and the second power supply line, And a gate terminal and a source terminal of the first P-type thin film transistor and the gate terminal of the second P-type thin film transistor are connected to each other. The method of claim 2, The current compensation unit And a current mirror connected between the first and second power supply lines to compensate the amount of current of the second power supplied to the level shift unit. The method of claim 1, And a second level shift unit for level shifting again with the first power supply and the second power supply using the output voltage of the level shift unit as an input voltage. The method of claim 4, wherein The second level shift unit And a first and a second inverter connected in series to an output terminal of the level shift unit and supplied with the first and second power sources.