KR100583141B1 - Level shifter and flat panel display having the same - Google Patents

Abstract

The present invention relates to a level shifter and a flat panel display having the same to reduce power consumption.

The level shifter according to the present invention includes a first transistor for applying a first voltage to an output terminal according to a first input signal, a second transistor for applying a second voltage to an output terminal according to a gate-source voltage, and the first input. A third transistor for equalizing the gate-source voltage of the second transistor according to a signal, and a capacitor for maintaining the gate-source voltage of the second transistor so that the second transistor is turned on according to a second input signal It is provided.

By such a configuration, the present invention can reduce the power consumption due to leakage current by blocking the static current path of the second transistor connected between the output terminal and the second power supply using the third transistor, and by using the capacitor. By maintaining the on state of the transistor, a voltage having a pull-down level (or a pull-up level) may be output to the output terminal. In addition, the present invention may output a voltage that rises (or falls) from the first voltage to the second voltage and decreases (or rises) from the second voltage to the first voltage.

Description

LEVEL SHIFTER AND FLAT PANEL DISPLAY HAVING THE SAME}             

1 is a circuit diagram illustrating a level shifter including a PMOS transistor according to an exemplary embodiment of the present invention.

FIG. 2 is a waveform diagram illustrating an input voltage and an output voltage of the level shifter shown in FIG. 1.

3 is a circuit diagram illustrating a level shifter including an NMOS transistor according to an exemplary embodiment of the present invention.

4 is a waveform diagram illustrating an input voltage and an output voltage of the level shifter shown in FIG. 1.

5 is a block diagram illustrating a flat panel display device having a level shifter according to an exemplary embodiment of the present invention.

6 is a block diagram illustrating another flat panel display device having a level shifter according to an exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: image display unit 108: control unit

111 pixel 120 scan driver

122: shift register section 124: level shifter section

130: data driver 140: level shifter

The present invention relates to a level shifter and a flat panel display having the same, and more particularly, to a level shifter and a flat panel display having the same to reduce power consumption.

In the design of semiconductor integrated circuits, there are cases where a voltage level converter is required for the interface between circuits requiring different voltage levels. For example, an integrated circuit such as a DRAM operates in a predetermined voltage range, but may require a signal voltage over the predetermined voltage range to interface with external circuits or provide signals to other circuits. The level shifter used in this case is a circuit that is placed between two systems to change the magnitude of the signal voltage when two systems having different magnitudes of signal voltage are connected. This level shifter is especially used for changing the signal voltage magnitude from a small voltage range to a large voltage range.

The conventional level shifter has a structure composed of first and second PMOS transistors. In this case, the first transistor is connected between the first power source HVDD and the output terminal, and the second transistor is connected between the output terminal and the second power source LVSS in a diode-connected form.

In the conventional level shifter, when the low input voltage Vin is input to the gate electrode of the first transistor, the output voltage of the high level HVDD is controlled by the on resistance ratio of the first and second transistors. (Vout) is determined.

When the high level input voltage Vin is input to the gate electrode of the first transistor, the output voltage Vout of the low level LVSS is higher than the low level LVSS by the threshold voltage Vth of the second transistor. It becomes the voltage LVSS + | Vth |.

As such, the conventional level shifter has a problem in that power consumption is high due to leakage current due to static current of the PMOS second transistor.

In addition, the conventional level shifter has a desired low level because the output voltage Vout of the low level LVSS becomes a voltage LVSS + | Vth | There is a problem that the output voltage Vout of the level LVSS cannot be obtained.

Accordingly, an object of the present invention is to provide a level shifter and a flat panel display having the same so as to reduce power consumption.

Further, another object of the present invention is to provide a level shifter and a flat panel display having the same so as to output an output voltage having an amplitude between a first voltage and a second voltage.

In order to achieve the above object, a level shifter according to an embodiment of the present invention is applied to a first transistor for applying a first voltage to an output terminal in accordance with a first input signal, and a second voltage to the output terminal in accordance with a gate-source voltage. A second transistor; a third transistor for equalizing a gate-source voltage of the second transistor according to the first input signal; and a second transistor for turning on the second transistor according to a second input signal. And a capacitor that maintains the gate-source voltage of the circuit.

The level shifter further includes a fourth transistor for turning on the second transistor according to the second input signal.

The second input signal and the first input signal are inverted with each other in the level shifter.

In the level shifter, the first to fourth transistors are any one of a PMOS transistor and an NMOS transistor.

In the level shifter, the capacitor stores the gate-source voltage of the second transistor according to the on of the fourth transistor, and the voltage at the output terminal reaches the level of the second voltage using the stored voltage. The on state of the second transistor is maintained.

A level shifter according to an embodiment of the present invention is provided by a first transistor connected between a first power supply and an output terminal and controlled by a first input signal, and a signal connected between a second power supply and an output terminal and applied to a first node. A second transistor to be controlled, a capacitor having a first electrode connected to the output terminal and a second electrode connected to the first node, and a second transistor connected between the output terminal and the first node and controlled by the first input signal. And a fourth transistor connected to the first node and the second power supply and controlled by a second input signal.

In the level shifter, the first to fourth transistors are any one of a PMOS transistor and an NMOS transistor.

The second input signal and the first input signal are inverted with each other in the level shifter.

A level shifter according to an embodiment of the present invention includes a first pass for supplying a first voltage to an output terminal according to a first input signal, and a second pass for supplying the second voltage to the output terminal according to a second input signal. And a third transistor for blocking the second pass according to the first input signal, and a capacitor for maintaining the second pass so that the voltage at the output terminal reaches the second voltage according to the second input signal. It is provided.

The second input signal and the first input signal are inverted from each other in the level shifter.

In the level shifter, the second voltage is lower than the first voltage.

The first pass in the level shifter includes a first transistor connected between a first power supply for supplying the first voltage and the output terminal and operated according to the first input signal.

The second pass in the level shifter includes a second transistor connected between a second power supply for supplying the second voltage and the output terminal and operated according to a voltage across the capacitor.

The level shifter further includes a fourth transistor connected between a first node connected to the gate electrode of the second transistor and the second power supply and turning on the second transistor according to the second input signal. .

In the level shifter, the first to fourth transistors are any one of a PMOS transistor and an NMOS transistor.

In the level shifter, the capacitor has a first electrode connected to the output terminal and a second electrode connected to the first node.

In the level shifter, the third transistor supplies the first voltage via the first transistor to the first node according to the first input signal.

In the level shifter the second transistor forms the second pass in accordance with the voltage on the first node.

In the level shifter, the capacitor stores the voltage between the gate and the source of the second transistor according to the on of the fourth transistor, and the voltage at the output terminal reaches the level of the second voltage using the stored voltage. The on state of the second transistor is maintained.

According to an exemplary embodiment of the present invention, a flat panel display includes an image display unit including a pixel formed at an intersection area between data lines and scan lines, a data driver supplying a data signal to the data line, and a start pulse input. And a level shifter comprising a plurality of shift registers and a plurality of the level shifters for level shifting the output signals from the shift registers and outputting them to the scan lines.

The flat panel display further includes a control unit for controlling the data driver and supplying the start pulse to the shift register.

The flat panel display further includes the level shifter connected between the control unit and the shift register unit and level shifting the start pulse from the control unit to supply the shift register unit.

The flat panel display is a light emitting display.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS. 1 to 6 which can be easily implemented by those skilled in the art.

Referring to FIG. 1, a level shifter according to an embodiment of the present invention includes a first transistor M1 connected between a first power source HVDD and an output terminal N2, an output terminal N2, and a second power source LVSS. The second transistor M2 connected therebetween, and the capacitor C connected to the first node N1 connected to the output terminal N2 and the second electrode connected to the gate electrode of the second transistor M2. ), Between the first node N1, the output terminal N2, and the third transistor M3 connected to the gate electrode of the first transistor M1, and between the first node N1 and the second power supply LVSS. The fourth transistor M4 is connected. Here, the first power source HVDD is larger than the second power source LVSS. In addition, the first to fourth transistors M1 to M4 are PMOS transistors.

As shown in FIG. 2, the input voltage Vin has a pulse shape in which a high level voltage and a low level voltage are alternately repeated. The inverted input voltage Vinb is inverted to the input voltage Vin.

The source electrode of the first transistor M1 is connected to the first power source HVDD, and the drain electrode is connected to the output terminal N2. The input voltage Vin is supplied to the gate electrode of the first transistor M1. The first transistor M1 forms a first path as a path for supplying a voltage of a first level, that is, the first power source HVDD to the output terminal N2 according to the level of the input voltage Vin. do.

The gate terminal of the second transistor M2 is connected to the first node N1, the source electrode is connected to the output terminal N2, and the drain electrode is connected to the second power supply LVSS. The second transistor M2 has a second pass as a path for supplying a voltage having a second level, that is, the second power supply LVSS to the output terminal N2 according to the voltage of the first node N1, that is, the gate electrode. form a path. At this time, the voltage HVDD of the first level is greater than the voltage LVSS of the second level.

The source electrode of the third transistor M3 is connected to the output terminal N2 and the drain electrode is connected to the first node N1. The input voltage Vin is supplied to the gate electrode of the third transistor M3. The third transistor M3 supplies the first node N1 with the voltage HVDD of the first level supplied through the first transistor M1 according to the level of the input voltage Vin. Accordingly, the third transistor M3 is turned on by the low level input voltage Vin so that the voltage Vgs between the gate and the source of the second transistor M2 is the same, that is, zero. To block the second path.

The source electrode of the fourth transistor M4 is connected to the first node N1 and the drain electrode is connected to the second power source LVSS. The inverted input voltage Vinb is supplied to the gate electrode of the fourth transistor M4. The fourth transistor M4 supplies the second level voltage LVSS to the first node N1 according to the inverted input voltage Vinb.

The capacitor C has a first electrode connected to the output terminal N2 and a second electrode connected to the first node N1. The capacitor C stores the voltage Vgs between the gate and the source of the second transistor M2 according to the switching of the fourth transistor M4 and then stores the voltage between the gate and the source of the second transistor M2. Vgs) serves to switch the second transistor M2. The capacitor C maintains the on state of the second transistor M2 according to the switching of the fourth transistor M4 so that the second path is continuously maintained.

The operation of the level shifter according to the embodiment of the present invention will be described with reference to FIG. 2 as follows.

First, when the input voltage Vin is at the low level as in the T1 period, the first and third transistors M1 and M3 are turned on and the fourth transistor M4 is applied to the inverted input voltage Vinb. By turning it off. Accordingly, the voltage of the first level, that is, the first power source HVDD is supplied to the output terminal N2 through the first transistor M1 and simultaneously supplied to the first node N1 via the third transistor M3. Supplied. Therefore, the first power source HVDD is output to the output terminal N2 in the T1 section as the voltage of the first level.

On the other hand, in the T1 section, the second transistor M2 blocks the static current path between the output terminal N2 and the second power supply LVSS. In other words, the gate electrode of the second transistor M2 is supplied with a first level voltage from the first power source HVDD via the first and third transistors M1 and M3 and the first node N1. The source electrode is supplied with the voltage of the first level from the first power source HVDD via the first transistor M1 and the output terminal N2. As a result, in the T1 section, since the gate-source voltage Vgs of the second transistor M2 becomes zero (0), the path of the second transistor M2 is blocked so that the current loss due to the static current is reduced. .

Therefore, the level shifter according to the embodiment of the present invention uses the third transistor M3 to output the voltage Vgs between the gate and the source of the second transistor M2 while outputting the voltage of the first level to the output terminal N2. The power consumption can be reduced by cutting off the static current path to zero.

Subsequently, when the input voltage Vin is at the high level as in the period T2, the first and third transistors M1 and M3 are turned off, and the fourth voltage is controlled by the low level inverted input voltage Vinb. Transistor M4 is turned on.

As the fourth transistor M4 is turned on, the voltage of the first node N1 drops, and thus, between the second terminal and the first terminal of the capacitor C, that is, between the source and the gate of the second transistor M2. Is applied to a voltage equal to or greater than the absolute value | Vth | of the threshold voltage of the second transistor M2. In this manner, the second transistor M2 is turned on.

Thereafter, when the voltage of the first node N1 continues to drop and the voltage between the source and the gate of the fourth transistor M4 becomes less than or equal to the absolute value of the threshold voltage of the fourth transistor M4, the fourth transistor M4. ) Is turned off.

When the fourth transistor M4 is turned off, the first terminal of the capacitor C is in a floating state so that the voltage of the capacitor C is kept constant. Therefore, the voltage between the second terminal and the first terminal of the capacitor C maintains a voltage equal to or greater than the absolute value | Vth | of the threshold voltage of the second transistor M2, so that the voltage at the output terminal N2 is full. The on-state state of the second transistor M2 is maintained to reach the second-down voltage, that is, the second power source LVSS.

As such, the level shifter according to the embodiment of the present invention cuts off the current loss by blocking the static current path of the second transistor M2 while outputting the voltage HVDD of the first level using the third transistor M3. In addition, the capacitor C is used to maintain the on state of the second transistor M2 to output the second level voltage LVDD that is pulled down. As a result, the level shifter according to the embodiment of the present invention enables the output of the voltage of the first level and the second level of the full swing (Vout) as shown in FIG. Power consumption is reduced by reducing the current loss caused by static current. Here, the voltage of the first level and the second level of the full swing are increased (or decreased) from the voltage value of the first power supply HVDD to the voltage value of the second power supply LVDD, and the voltage of the second power supply. Refers to a pulse that falls (or rises) from the value to the voltage value of the first power supply.

Meanwhile, the level shifter according to the exemplary embodiment of the present invention uses NMOS transistors M1, M2, M3, and M4 as shown in FIGS. 3 and 4 instead of PMOS transistors, and each NMOS transistor M1, M2, The output Vout of the voltage of the first level and the voltage of the second level that is fully swinged by being supplied inverted with the PMOS transistors of the input voltages Vin and Vinb of the M3 and M4 is possible.

On the other hand, the level shifter according to the embodiment of the present invention is included in a driving circuit for outputting a low-level voltage pulled down using a PMOS transistor, a level conversion circuit (step-up circuit) and a scan driving circuit of a flat panel display device. Can be configured in the shift register and the level shifter.

For example, as illustrated in FIG. 5, a flat panel display having a level shifter according to an exemplary embodiment of the present invention includes an image display unit including pixels 111 formed at an intersection area between a scan line SL and a data line DL. 100, the scan driver 120 for driving the scan lines SL, the data driver 130 for driving the data lines DL, the scan driver 120 and the data driver 130 are controlled. In addition, a control unit 108 for supplying a data signal to the data driver 130 is provided.

Each of the pixels 111 is selected when a selection signal is applied to the scan line SL, and displays an image corresponding to the data signal supplied to the data line DL. The pixels 111 may include liquid crystal cells of a liquid crystal display, field emission panels, discharge cells of a plasma display panel, and light emitting displays. May be a light emitting cell. In particular, each of the pixels 111 is a pixel of a large flat panel display including a light emitting display that drives a pixel using a PMOS transistor.

The controller 108 supplies the scan control signals for controlling the driving timing of the scan driver 120 to the scan driver 120 and the data control signals for controlling the driving timing of the data driver 120. ) And a data signal from the outside to the data driver 130.

The data driver 130 supplies the data signal from the controller 108 to the pixel 111 through the data lines DL in response to the data control signals supplied from the controller 108. In this case, the data driver 130 supplies data signals of one horizontal line to the data lines DL every one horizontal period.

The scan driver 120 generates a selection signal for enabling the scan lines SL in response to scan control signals from the controller 108, that is, a start pulse and a clock signal, and sequentially supplies the scan signals to the scan lines SL. do.

To this end, the scan driver 120 shifts the shift register 122 for sequentially shifting the start pulse from the controller 108 and the input signals input from the shift register 122 to scan lines SL. ) Is provided with a level shifter portion 124.

The shift register unit 122 sequentially shifts the start pulse using a plurality of shift registers and supplies the shift signal to the level shifter unit 124.

The level shifter unit 124 includes a plurality of level shifters according to the embodiment of the present invention described above. Each of the level shifters converts a voltage range of an input signal input from the shift register and supplies the converted voltage to the scan lines SL.

Meanwhile, as shown in FIG. 6, the flat panel display having the level shifter according to the exemplary embodiment of the present invention configures the level shifter 140 according to the exemplary embodiment of the present invention between the controller 108 and the scan driver 120. Thus, the voltage range of the start pulse output from the control unit 108 can be converted into the voltage range used by the shift register unit 122.

The above detailed description and drawings are merely exemplary of the present invention, which are used only for the purpose of illustrating the present invention and are not intended to limit the scope of the present invention as defined in the claims or the claims. Therefore, those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical protection scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

As described above, the level shifter and the flat display device having the same according to the exemplary embodiment of the present invention block the static current path of the second transistor connected between the output terminal and the second power supply by using the third transistor to prevent leakage current. Therefore, power consumption can be reduced, and a voltage of a pull-down level (or pull-up level) can be output to the output terminal by maintaining an on state of the second transistor using a capacitor.

In addition, the present invention may output a voltage that rises (or falls) from the first voltage to the second voltage and decreases (or rises) from the second voltage to the first voltage.

Claims (23)

A first transistor M1 connected between the first power supply HVDD as the first level voltage and the output terminal N2 and supplied with an input voltage to the gate electrode; A second transistor M2 connected between the output terminal N2 and the second power supply LVSS as a second level voltage, and having a gate electrode connected to the first node N1; A third transistor M3 connected between the first node N1 and the output terminal N2 and supplied with an input voltage to a gate electrode; And a capacitor (C) connected between the first node (N1) and the output terminal (N2). The method of claim 1, And a fourth transistor (M4) connected between the first node (N1) and the second power supply (LVSS) and supplied with an inverted input voltage to the gate electrode. delete The method of claim 2, The first to fourth transistors are any one of a PMOS transistor and an NMOS transistor. The method of claim 2, The capacitor stores the gate-source voltage of the second transistor according to the on of the fourth transistor, and uses the stored voltage to cause the voltage at the output terminal to reach the second level voltage. Level shifter to keep the On state. A first transistor connected between the first power supply and the output terminal and controlled by the first input signal, A second transistor connected between the second power supply and the output terminal and controlled by a signal applied to the first node, A capacitor having a first electrode connected to the output terminal and a second electrode connected to a first node; A third transistor connected between the output terminal and the first node and controlled by the first input signal; And a fourth transistor connected to said first node and said second power supply and controlled by a second input signal. The method of claim 6, The first to fourth transistors are any one of a PMOS transistor and an NMOS transistor. The method of claim 6, And a level shifter in which the second input signal and the first input signal are inverted from each other. A first path for supplying a first voltage to an output terminal according to the first input signal, A second path for supplying a second voltage to the output terminal according to a second input signal; A third transistor connected between the output terminal and the first node and controlled by the first input signal to block the second path according to the first input signal; A first electrode is connected to the output terminal and a second electrode is connected to the first node to maintain the second path such that the voltage at the output terminal reaches the second voltage according to the second input signal. Level shifter with a capacitor. The method of claim 9, And a level shifter in which the second input signal and the first input signal are inverted from each other. The method of claim 9, And the second voltage is lower than the first voltage. The method of claim 9, And the first path comprises a first transistor connected between a first power supply for supplying the first voltage and the output terminal and operated according to the first input signal. The method of claim 12, And said second path comprises a second transistor connected between a second power supply for supplying said second voltage and said output terminal and operated according to a voltage across said capacitor. The method of claim 13, And a fourth transistor connected between the first node connected to the gate electrode of the second transistor and the second power supply, and configured to turn on the second transistor according to the second input signal. The method of claim 14, The first to fourth transistors are any one of a PMOS transistor and an NMOS transistor. delete The method of claim 14, And the third transistor supplies the first voltage to the first node according to the first input signal. The method of claim 17, And said second transistor forms said second pass in accordance with a voltage on said first node. The method of claim 14, The capacitor stores the voltage between the gate and the source of the second transistor according to the on of the fourth transistor, and uses the stored voltage so that the voltage at the output terminal reaches the level of the second voltage. A level shifter to keep the transistor on. An image display unit including pixels formed at intersections of data lines and scan lines; A data driver for supplying a data signal to the data line; A shift register section for sequentially shifting input start pulses; 20. A flat panel display comprising: a level shifter comprising a plurality of level shifters according to any one of claims 1 to 19 for level shifting an output signal from a shift register section and outputting them to the scan lines. The method of claim 20, And a control unit which controls the data driver and supplies the start pulse to the shift register. The method of claim 21, 20. A flat panel display further comprising a level shifter according to any one of claims 1 to 19 connected between said control section and said shift register section and for level shifting said start pulse from said control section and supplying said shift register section. Device. The method of claim 20, The flat panel display is a light emitting display device.

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