KR20030051072A - Method For Manufacturing Analogue Capacitor - Google Patents
Method For Manufacturing Analogue Capacitor Download PDFInfo
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- KR20030051072A KR20030051072A KR1020010081971A KR20010081971A KR20030051072A KR 20030051072 A KR20030051072 A KR 20030051072A KR 1020010081971 A KR1020010081971 A KR 1020010081971A KR 20010081971 A KR20010081971 A KR 20010081971A KR 20030051072 A KR20030051072 A KR 20030051072A
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- analog
- film
- interlayer dielectric
- analog capacitor
- metal wiring
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- 239000003990 capacitor Substances 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title abstract description 14
- 238000000034 method Methods 0.000 title abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 48
- 229910052751 metal Inorganic materials 0.000 claims abstract description 48
- 239000011229 interlayer Substances 0.000 claims abstract description 42
- 150000004767 nitrides Chemical class 0.000 claims abstract description 38
- 239000010410 layer Substances 0.000 claims abstract description 23
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims description 26
- 238000010030 laminating Methods 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 claims 1
- 238000000151 deposition Methods 0.000 abstract 1
- 239000010949 copper Substances 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 230000005669 field effect Effects 0.000 description 4
- 230000009977 dual effect Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000005685 electric field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
- H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
- H01L27/0733—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors in combination with capacitors only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02247—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 아날로그 커패시터에 관한 것으로서, 특히, 반도체기판상의 일반회로영역 및 아날로그영역에 각각 하부금속배선 및 아날로그 커패시터 하부전극을 형성하고, IMD공정으로 산화막, 질화막 및 산화막으로 된 층간절연막을 형성하고, 듀얼 다마신(Damascene)공정으로 하부금속배선 및 아날로그 커패시터 하부전극이 노출되도록 하고, 노출된 이중콘택홀을 통하여서 절연질화막 및 구리 금속을 매립하여서 식각으로 상부금속배선 및 아날로그 커패시터 상부전극을 형성하므로 안정적이고, 신뢰성 있는 소자를 제조하도록 하는 아날로그 커패시터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog capacitor, and in particular, a lower metal wiring and an analog capacitor lower electrode are formed in a general circuit region and an analog region on a semiconductor substrate, and an interlayer insulating film made of an oxide film, a nitride film, and an oxide film is formed by an IMD process. The dual damascene process exposes the lower metal wiring and the analog capacitor lower electrode, and forms the upper metal wiring and the analog capacitor upper electrode by etching by embedding the insulating nitride film and copper metal through the exposed double contact hole. The present invention relates to an analog capacitor manufacturing method for manufacturing a reliable device.
일반적으로, 반도체장치의 종류에는 여러 가지가 있으며, 이 반도체장치 내에 형성되는 트랜지스터 및 커패시터등을 구성시키는 방법에는 다양한 제조기술이 사용되고 있다. 최근에는 반도체기판 상에 산화막을 입혀 전계효과를 내도록 하는 모스형 전계효과트랜지스터(MOSFET; metal oxide semiconductor field effect transistor)를 점차적으로 많이 사용하고 있는 실정에 있다.In general, there are various kinds of semiconductor devices, and various manufacturing techniques are used in the method of constructing transistors, capacitors, and the like formed in the semiconductor device. Recently, MOSFETs (metal oxide semiconductor field effect transistors) for applying an oxide film on a semiconductor substrate to produce an electric field effect have been gradually used.
상기한 모스형 전계효과트랜지스터는 반도체 기판상에 형성된 게이트가 반도체층에서 얇은 산화 실리콘막에 의해 격리되어 있는 전계효과 트랜지스터로 접합형과 같이 임피던스가 저하되는 일이 없으며, 확산 공정이 1회로 간단하고, 소자간의 분리가 필요 없는 장점을 지니고 있어서, 고밀도 집적화에 적합한 특성을 지니고있는 반도체 장치이다.The MOS type field effect transistor is a field effect transistor in which a gate formed on a semiconductor substrate is isolated by a thin silicon oxide film in a semiconductor layer, and the impedance is not lowered like a junction type. The semiconductor device is advantageous in that it does not require separation between devices, and is suitable for high density integration.
이러한 반도체 장치에는 모스형 전계효과트랜지스터에서 아날로그 신호를 디지털 신호로 변화시켜야 하는 옵션프로세스가 적용되는 경우에 디지털부분인 트랜지스터(Transistor) 영역(이하, 일반회로 영역이라 함)을 형성하면서 동시에 아날로그(Analogue) 회로용으로 사용되는 커패시터(Capacitor) 영역(이하, 아날로그영역이라 함)이 형성된 아날로그형 반도체소자를 제조하여 사용하고 있으며, 본 발명은 아날로그 회로용으로 사용되는 커패시터의 특성을 개선시킨 새로운 발명을 제안하고 있다.In the semiconductor device, when an option process for converting an analog signal into a digital signal is applied in a MOS type field effect transistor, a digital portion of a transistor region (hereinafter, referred to as a general circuit region) is formed and at the same time an analog (Analogue) ) An analog semiconductor device having a capacitor region (hereinafter referred to as an analog region) formed for a circuit is manufactured and used. The present invention provides a new invention that improves the characteristics of a capacitor used for an analog circuit. I'm proposing.
종래의 방법으로 MIM(Metal-Insulator-Metal)커패시터를 형성함에 있어서, 새로운 금속층을 추가하여야 하는 문제점과 추가되는 금속층으로 인하여 "일반회로영역" 과 "아날로그영역" 사이에 단차가 발생하고, 후속 금속 배선 형성에 어려움이 발생할수 있는 문제점이 있었다.In forming a metal-insulator-metal (MIM) capacitor by a conventional method, a step is generated between the "normal circuit area" and the "analog area" due to the problem of adding a new metal layer and the added metal layer, and subsequent metals. There was a problem that difficulty in wiring formation may occur.
본 발명은 이러한 점을 감안하여 안출한 것으로서, 반도체기판상의 일반회로영역 및 아날로그영역에 각각 하부금속배선 및 아날로그 커패시터 하부전극을 형성하고, IMD공정으로 산화막, 질화막 및 산화막으로 된 층간절연막을 형성하고, 듀얼 다마신공정으로 하부금속배선 및 아날로그 커패시터 하부전극이 노출되도록 하고, 노출된 이중콘택홀을 통하여서 절연질화막 및 구리 금속을 매립하여서 식각으로 상부금속배선 및 아날로그 커패시터 상부전극을 형성하므로 안정적이고, 신뢰성 있는소자를 제조하는 것이 목적이다.The present invention has been made in view of this point, and the lower metal wiring and the analog capacitor lower electrode are formed in the general circuit region and the analog region on the semiconductor substrate, and an interlayer insulating film made of oxide film, nitride film and oxide film is formed by IMD process. And dual damascene process to expose the lower metal wiring and analog capacitor lower electrode, and to form the upper metal wiring and analog capacitor upper electrode by etching by embedding insulating nitride film and copper metal through exposed double contact hole. The purpose is to manufacture a device.
도 1 내지 도 6은 본 발명의 일 실시예에 따른 아날로그 커패시터 제조방법을 보인 도면이고,1 to 6 is a view showing an analog capacitor manufacturing method according to an embodiment of the present invention,
도 11 내지 도 17은 본 발명의 다른 실시예에 따른 아날로그 커패시터 제조방법을 보인 도면이다.11 to 17 illustrate an analog capacitor manufacturing method according to another embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
1,101 : 반도체기판 3,103 : 하부금속배선1,101 semiconductor board 3,103 lower metal wiring
3a,103a : 아날로그 커패시터 하부전극3a, 103a: Analog capacitor lower electrode
5,105 : 제1층간절연산화막 7,107 : 층간절연질화막5,105: first interlayer dielectric oxide film 7,107: interlayer dielectric nitride film
9,109 : 제2층간절연화막 11,111 : 제1감광막9,109: Second interlayer insulating film 11,111: First photosensitive film
13,113 : 콘택홀 15,115 : 제2감광막13,113: contact hole 15,115: second photosensitive film
17,117 : 이중콘택홀 19,119 : 절연질화막17,117: double contact hole 19,119: insulating nitride film
21, 121 : 제3감광막 23a, 123a : 아날로그 커패시터 상부전극21, 121: third photosensitive film 23a, 123a: analog capacitor upper electrode
이러한 목적은, 일반회로영역과 아날로그영역으로 이루어진 반도체장치에 있어서, 반도체기판 상에 일반회로영역에는 하부금속배선을 형성하고, 아날로그영역에는 아날로그 커패시터 하부전극을 형성한 후, 층간절연산화막, 층간절연질화막 및 층간절연산화막을 순차적으로 적층하는 단계와; 상기 층간절연산화막 상에 제1감광막을 적층하여 패터닝한 후, 상기 층간절연산화막 및 층간절연질화막을 순차적으로 식각하여 콘택홀을 형성하는 단계와; 상기 결과물에서 제1감광막을 제거한 후, 층간절연막 상에 제2감광막을 적층하여서 상기 하부금속배선 및 아날로그커패시터 하부전극이 노출되도록 식각을 진행하는 단계와; 상기 제2감광막을 제거한 후, 결과물 상에 절연질화막을 적층하는 단계와; 상기 단계 후에 아날로그 영역만 차단되도록 제3감광막을 적층한 후, 일반회로영역의 절연질화막을 식각하여서 하부금속배선을 노출하도록 하는 단계와; 상기 단계 후에 상기 제3감광막을 제거한 후, 노출된 이중콘택홀 내에 금속을 매립하여서 상부금속배선 및 아날로그 커패시터 상부전극을 형성하는 단계를 포함하여 이루어진 아날로그 커패시터 제조방법을 제공함으로써 달성된다.In the semiconductor device comprising a general circuit region and an analog region, a lower metal wiring is formed in the general circuit region on the semiconductor substrate and an analog capacitor lower electrode is formed in the analog region. Sequentially stacking a nitride film and an interlayer dielectric oxide film; Stacking and patterning a first photoresist layer on the interlayer dielectric oxide film, and subsequently forming a contact hole by sequentially etching the interlayer dielectric oxide film and the interlayer dielectric nitride film; Removing the first photoresist film from the resultant, and then laminating a second photoresist film on the interlayer insulating film to etch the lower metal wiring and the analog capacitor lower electrode; After removing the second photoresist film, laminating an insulating nitride film on the resultant; Stacking a third photoresist film to block only the analog region after the step, and etching the insulating nitride film of the general circuit region to expose the lower metal wiring; After removing the third photoresist film after the step, it is achieved by providing a method for manufacturing an analog capacitor comprising the step of forming a top metal wiring and an analog capacitor upper electrode by embedding a metal in the exposed double contact hole.
상기 층간절연산화막을 화학기계적연마공정(CMP, Chemical Mechanical Polishing)으로 평탄화하도록 한다.The interlayer insulating oxide film is planarized by chemical mechanical polishing (CMP).
그리고, 상기 층간절연질화막은, PE-CVD방식으로 100 ∼ 500Å의 두께로 적층하도록 한다.In addition, the interlayer insulating nitride film is laminated with a thickness of 100 to 500 GPa by PE-CVD.
그리고, 상기 절연질화막은, CVD방법으로 50 ∼ 300Å의 두께로 적층하는 것이 바람직 하다.The insulating nitride film is preferably laminated in a thickness of 50 to 300 kPa by the CVD method.
그리고, 상기 상부금속배선 및 아날로그 커패시터 상부전극은 구리(Cu)이고, CVD방법으로 적층하도록 한다.The upper metal wiring and the analog capacitor upper electrode are copper (Cu), and are stacked by CVD.
한편, 다른 실시예로서, 본 발명의 목적은, 일반회로영역과 아날로그영역으로 이루어진 반도체장치에 있어서, 반도체기판 상에 일반회로영역에는 하부금속배선을 형성하고, 아날로그영역에는 아날로그 커패시터 하부전극을 형성한 후, 층간절연산화막 및 층간절연질화막을 적층하는 단계와; 상기 층간절연질화막 상에 제1감광막을 적층하여 패터닝한 후, 상기 층간절연질화막을 식각하여 콘택홀을 형성하는 단계와; 상기 결과물에서 층간절연산화막을 적층한 후, 상기 층간절연산화막 상에 제2감광막을 적층하여서 상기 하부금속배선 및 아날로그커패시터 하부전극이 노출되도록 식각을 진행하는 단계와; 상기 제2감광막을 제거한 후, 결과물 상에 절연질화막을 적층하는 단계와; 상기 단계 후에 아날로그 영역만 차단되도록 제3감광막을 적층한 후, 일반회로영역의 절연질화막을 식각하여서 하부금속배선을 노출하도록 하는 단계와; 상기 단계 후에 상기 제3감광막을 제거한 후, 노출된 이중콘택홀 내에 금속을 매립하여서 상부금속배선 및 아날로그 커패시터 상부전극을 형성하는 단계를 포함하여 이루어진 아날로그 커패시터 제조방법을 제공함으로써 달성된다.On the other hand, in another embodiment, an object of the present invention is to form a lower metal wiring in a general circuit region on a semiconductor substrate and an analog capacitor lower electrode in an analog region in a semiconductor device comprising a general circuit region and an analog region. Thereafter, laminating an interlayer dielectric oxide film and an interlayer dielectric nitride film; Stacking and patterning a first photoresist film on the interlayer dielectric nitride film, and etching the interlayer dielectric nitride film to form contact holes; Stacking an interlayer insulating oxide film on the resultant, and then laminating a second photoresist film on the interlayer insulating oxide film to etch the lower metal wiring and the analog capacitor lower electrode; After removing the second photoresist film, laminating an insulating nitride film on the resultant; Stacking a third photoresist film to block only the analog region after the step, and etching the insulating nitride film of the general circuit region to expose the lower metal wiring; After removing the third photoresist film after the step, it is achieved by providing a method for manufacturing an analog capacitor comprising the step of forming a top metal wiring and an analog capacitor upper electrode by embedding a metal in the exposed double contact hole.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 일 실시예에 대해 상세하게 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 6은 본 발명의 일실시예에 따른 아날로그커패시터의 제조방법을 순차적으로 보인 도면이다.1 to 6 are views sequentially showing a method of manufacturing an analog capacitor according to an embodiment of the present invention.
도 1에 도시된 바와 같이, 반도체기판(1) 상에 일반회로영역에는 하부금속배선(3)을 형성하고, 아날로그영역에는 아날로그 커패시터 하부전극(3a)을 형성한 후, 층간절연산화막(5), 층간절연질화막(7) 및 층간절연산화막(9)을 순차적으로 적층하도록 한다.As shown in FIG. 1, after forming the lower metal wiring 3 in the general circuit region on the semiconductor substrate 1 and the analog capacitor lower electrode 3a in the analog region, the interlayer insulating oxide film 5 is formed. The interlayer dielectric nitride film 7 and the interlayer dielectric oxide film 9 are sequentially stacked.
상기 층간절연산화막(5)을 화학기계적연마공정으로 평탄화하도록 한다.The interlayer insulating oxide film 5 is planarized by a chemical mechanical polishing process.
그리고, 상기 층간절연질화막(7)은, PE-CVD방식으로 100 ∼ 500Å의 두께로 적층하도록 한다.The interlayer dielectric nitride film 7 is laminated to a thickness of 100 to 500 kV by PE-CVD.
그리고, 도 2에 도시된 바와 같이, 상기 층간절연산화막(9) 상에 제1감광막 (11)을 적층하여 패터닝한 후, 상기 층간절연산화막(9) 및 층간절연질화막(7)을 순차적으로 식각하여 콘택홀(13)을 형성하도록 한다.As shown in FIG. 2, after the first photoresist layer 11 is stacked and patterned on the interlayer dielectric oxide layer 9, the interlayer dielectric oxide layer 9 and the interlayer dielectric nitride layer 7 are sequentially etched. To form the contact hole 13.
도 3에 도시된 바와 같이, 상기 결과물에서 제1감광막(11)을 제거한 후, 층간절연막(9) 상에 제2감광막(15)을 적층하여서 상기 하부금속배선(3) 및 아날로그커패시터 하부전극(3a)이 노출되도록 식각을 진행하도록 한다.As shown in FIG. 3, after the first photoresist layer 11 is removed from the resultant, a second photoresist layer 15 is laminated on the interlayer insulating layer 9 to form the lower metal wiring 3 and the analog capacitor lower electrode ( The etching is performed to expose 3a).
도 4에 도시된 바와 같이, 상기 제2감광막(15)을 제거한 후, 결과물 상에 절연질화막(19)을 적층하도록 한다.As shown in FIG. 4, after the second photosensitive film 15 is removed, the insulating nitride film 19 is stacked on the resultant.
도 5에 도시된 바와 같이, 상기 단계 후에 아날로그 영역만 차단되도록 제3감광막(21)을 적층한 후, 일반회로영역의 절연질화막(19)을 식각하여서 하부금속배선(3)을 노출하도록 하도록 한다.As shown in FIG. 5, after stacking the third photoresist film 21 so that only the analog region is blocked after the step, the insulating nitride film 19 of the general circuit region is etched to expose the lower metal wiring 3. .
상기 절연질화막(19)은, CVD방법으로 50 ∼ 300Å의 두께로 적층하도록 한다.The insulating nitride film 19 is laminated in a thickness of 50 to 300 kPa by the CVD method.
도 6에 도시된 바와 같이, 상기 단계 후에 상기 제3감광막(21)을 제거한 후, 노출된 이중콘택홀(17)내에 금속을 매립하여서 상부금속배선(23) 및 아날로그 커패시터 상부전극(23a)을 형성하도록 한다.As shown in FIG. 6, after the step, the third photoresist film 21 is removed, and then the upper metal wiring 23 and the analog capacitor upper electrode 23a are embedded by embedding a metal in the exposed double contact hole 17. To form.
상기 상부금속배선(23) 및 아날로그 커패시터 상부전극(23a)은 구리이고, CVD방법으로 적층하도록 한다.The upper metal wiring 23 and the analog capacitor upper electrode 23a are copper, and are stacked by CVD.
도 11 내지 도 17은 본 발명의 다른 실시예에 따른 아날로그 커패시터 제조방법을 보인 도면이다.11 to 17 illustrate an analog capacitor manufacturing method according to another embodiment of the present invention.
도 11에 도시돤 바와 같이, 반도체기판(101) 상에 일반회로영역에는 하부금속배선(103)을 형성하고, 아날로그영역에는 아날로그 커패시터 하부전극(103a)을 형성한 후, 층간절연산화막(105) 및 층간절연질화막(107)을 적층하도록 한다.As shown in FIG. 11, after the lower metal wiring 103 is formed in the general circuit region on the semiconductor substrate 101 and the analog capacitor lower electrode 103a is formed in the analog region, the interlayer insulating oxide film 105 is formed. And an interlayer insulating nitride film 107 are laminated.
그리고, 도 12에 도시된 바와 같이, 상기 층간절연질화막(107) 상에 제1감광막(111)을 적층하여 패터닝한 후, 상기 층간절연질화막(107)을 식각하여 콘택홀(113)을 형성하도록 한다.As shown in FIG. 12, after the first photoresist layer 111 is stacked and patterned on the interlayer dielectric nitride layer 107, the interlayer dielectric nitride layer 107 is etched to form a contact hole 113. do.
도 13 및 도 14에 도시된 바와 같이, 상기 결과물에서 층간절연산화막(109)을 적층한 후, 상기 층간절연산화막(109) 상에 제2감광막(115)을 적층하여서 상기 하부금속배선(103) 및 아날로그커패시터 하부전극(103a)이 노출되도록 식각을 진행하도록 한다.As shown in FIGS. 13 and 14, after the interlayer insulating oxide film 109 is stacked in the resultant product, a second photosensitive film 115 is laminated on the interlayer insulating oxide film 109 to form the lower metal wiring 103. And etching to expose the analog capacitor lower electrode 103a.
도 15에 도시된 바와 같이, 상기 제2감광막(115)을 제거한 후, 결과물 상에 절연질화막(119)을 적층하도록 한다.As shown in FIG. 15, after removing the second photoresist film 115, an insulating nitride film 119 is stacked on the resultant.
도 16에 도시된 바와 같이, 상기 단계 후에 아날로그 영역만 차단되도록 제3감광막(121)을 적층한 후, 일반회로영역의 절연질화막(109)을 식각하여서 하부금속배선(103)을 노출하도록 하도록 한다.As shown in FIG. 16, after stacking the third photoresist film 121 so that only the analog region is blocked after the step, the insulating nitride film 109 of the general circuit region is etched to expose the lower metal wiring 103. .
도 17에 도시된 바와 같이, 상기 단계 후에 상기 제3감광막(121)을 제거한 후, 노출된 이중콘택홀(117)내에 금속을 매립하여서 상부금속배선(123) 및 아날로그 커패시터 상부전극(123a)을 형성하도록 한다.As shown in FIG. 17, after removing the third photoresist layer 121 after the step, the upper metal wiring 123 and the analog capacitor upper electrode 123a are buried by filling a metal in the exposed double contact hole 117. To form.
상기한 바와 같이, 본 발명에 따른 아날로그커패시터 제조방법을 이용하게 되면, 반도체기판상의 일반회로영역 및 아날로그영역에 각각 하부금속배선 및 아날로그 커패시터 하부전극을 형성하고, IMD공정으로 산화막, 질화막 및 산화막으로 된 층간절연막을 형성하고, 듀얼 다마신공정으로 하부금속배선 및 아날로그 커패시터 하부전극이 노출되도록 하고, 노출된 이중콘택홀을 통하여서 절연질화막 및 구리 금속을 매립하여서 식각으로 상부금속배선 및 아날로그 커패시터 상부전극을 형성하므로 안정적이고, 신뢰성 있는 소자를 제조하도록 하는 매우 유용하고 효과적인 발명이다.As described above, when the analog capacitor manufacturing method according to the present invention is used, the lower metal wiring and the analog capacitor lower electrode are formed in the general circuit region and the analog region on the semiconductor substrate, and the oxide film, the nitride film and the oxide film are formed by the IMD process. The interlayer insulating film is formed, the lower metal wiring and the analog capacitor lower electrode are exposed by a dual damascene process, and the upper metal wiring and the analog capacitor upper electrode are etched by burying the insulating nitride film and copper metal through the exposed double contact hole. It is a very useful and effective invention which makes it possible to manufacture a stable and reliable device.
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