KR20030050718A - A fabricating method of semiconductor device - Google Patents
A fabricating method of semiconductor device Download PDFInfo
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- KR20030050718A KR20030050718A KR1020010081229A KR20010081229A KR20030050718A KR 20030050718 A KR20030050718 A KR 20030050718A KR 1020010081229 A KR1020010081229 A KR 1020010081229A KR 20010081229 A KR20010081229 A KR 20010081229A KR 20030050718 A KR20030050718 A KR 20030050718A
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- film
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- conductive layer
- plug
- semiconductor device
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- 238000000034 method Methods 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 230000004888 barrier function Effects 0.000 claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims description 13
- 239000012530 fluid Substances 0.000 claims description 11
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 4
- 229910052731 fluorine Inorganic materials 0.000 claims description 4
- 239000011737 fluorine Substances 0.000 claims description 4
- 239000010408 film Substances 0.000 description 44
- 239000010410 layer Substances 0.000 description 19
- 238000000151 deposition Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 3
- 230000009969 flowable effect Effects 0.000 description 3
- CTQNGGLPUBDAKN-UHFFFAOYSA-N O-Xylene Chemical compound CC1=CC=CC=C1C CTQNGGLPUBDAKN-UHFFFAOYSA-N 0.000 description 2
- 229910008484 TiSi Inorganic materials 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 235000013399 edible fruits Nutrition 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 239000008096 xylene Substances 0.000 description 2
- 244000025254 Cannabis sativa Species 0.000 description 1
- 235000012766 Cannabis sativa ssp. sativa var. sativa Nutrition 0.000 description 1
- 235000012765 Cannabis sativa ssp. sativa var. spontanea Nutrition 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 235000009120 camo Nutrition 0.000 description 1
- 235000005607 chanvre indien Nutrition 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000007806 chemical reaction intermediate Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011487 hemp Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자 제조 방법에 관한 것으로 특히, 반도체 소자의 플러그 형성 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a plug of a semiconductor device.
반도체 소자의 금속배선 형성시 콘택 저항을 낮추기 위해 플러그 물질로 텅스텐(W) 등을 사용하게 되었으며, 플러그 형성을 위해서는 평탄화 공정이 필수적인 바, 이 중 화학기계적연마(Chemical Mechanical Deposition; 이하 CMP라 함)에 비해 공정 단가가 저렴하고 산화막계열에 대한 선택비가 우수한 건식 전면식각을 많이 이용한다.Tungsten (W) is used as a plug material to reduce contact resistance when forming a metal wiring of a semiconductor device, and a planarization process is essential for forming a plug. Among them, chemical mechanical deposition (hereinafter referred to as CMP) Compared to other methods, dry front side etching is used in which the process cost is low and the selectivity for oxide series is excellent.
그러나, 건식 전면식각의 가장 큰 문제점 중의 하나가 바로 심(Seam)의 발생이라 할 수 있는 바, 식각 종말점(End Of Point; 이하 EOP라 함) 조절이 어려워 예컨대, 텅스텐 플러그 등을 형성할 때 심이 발생한다.However, one of the biggest problems of dry front etching is the generation of seam, which is difficult to control the end point (EOP), for example, when forming a tungsten plug or the like. Occurs.
이하, 종래의 플러그 형성 공정을 도시한 도 1a 내지 도 1c를 참조하여 종래기술의 문제점을 살펴 본다.Hereinafter, the problems of the prior art will be described with reference to FIGS. 1A to 1C illustrating a conventional plug forming process.
먼저, 도 1a에 도시된 바와 같이 전도층(10) 상의 절연막(11)을 선택적으로 식각하여 전도층(10) 표면을 노출시키는 오픈부(도시하지 않음)를 형성한 다음, 오픈부를 포함한 전체 프로파일을 따라 Ti, TiN, TiSi2, TiW, Ta, TaN 또는 TaW 등을 이용하여 다층의 배리어막(12a, 12b)을 형성한 다음, 전체 구조 상부에 W, Ti, TiN 또는 Al 등을 증착하여 플러그(13)를 형성한다.First, as illustrated in FIG. 1A, an insulating portion 11 on the conductive layer 10 is selectively etched to form an open portion (not shown) exposing the surface of the conductive layer 10, and then the entire profile including the open portion. Along to form a multilayer barrier film (12a, 12b) using Ti, TiN, TiSi 2 , TiW, Ta, TaN or TaW, and then deposit W, Ti, TiN or Al on top of the entire structure (13) is formed.
다음으로, 도 1b에 도시된 바와 같이 절연막(11) 표면이 노출될 때까지 전면식각을 실시하여 평탄화 및 이웃하는 전극과 격리시킨다.Next, as shown in FIG. 1B, the entire surface is etched until the surface of the insulating film 11 is exposed to planarize and isolate from the neighboring electrodes.
한편, 전면식각 과정에서 전술한 바와 같이 중앙부의 심(15)을 따라 과도 식각이 일어나게 되며, 이에 따라 플러그(14)의 손실과 보이드(Void, 14)가 발생한다.On the other hand, as described above, the over-etching occurs along the shim 15 in the center as described above, thereby causing loss of the plug 14 and voids (Void, 14).
이는 후속의 금속막 증착시 피복 특성을 열화시키는 문제를 야기시키는 바, 도 1c에 도시된 바와 같이, Al, Cu, Ti, TiN, W, WN, TiW 및 TaW로 이루어지는 그룹으로 부터 선택된 적어도 하나를 이용하여 금속막(16)을 형성할 때, 전술한 보이드 및 심 등에 의해 소자의 특성은 더욱 열화된다.This causes a problem of deterioration of coating properties in subsequent metal film deposition, as shown in FIG. 1C, at least one selected from the group consisting of Al, Cu, Ti, TiN, W, WN, TiW and TaW. When the metal film 16 is formed by use, the characteristics of the device are further deteriorated by the above-described voids, shims, and the like.
한편, 전술한 공정과 동일하게 진행하되, 전면식각시 그 종말점 즉, 에치 타겟을 배리어막(12)으로 하게 되면, 전술한 경우보다 더욱 심하게 특성이 열화된다.On the other hand, the same process as described above, but when the end surface, that is, the etching target when the etch target to the barrier film 12 during the entire surface etching, the characteristics are worse than the above-described case.
상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 본 발명은, 플러그 형성시 심과 보이드 생성을 방지하기에 적합한 반도체 소자 제조 방법을 제공하는 것을 그 목적으로 한다.The present invention proposed to solve the problems of the prior art as described above, the object of the present invention is to provide a method for manufacturing a semiconductor device suitable for preventing the formation of seams and voids when forming a plug.
도 1a 내지 도 1c는 종래기술에 따른 플러그 형성 공정을 도시한 단면도,1a to 1c is a cross-sectional view showing a plug forming process according to the prior art,
도 2a 내지 도 2c는 본 발명의 일실시예에 따른 플러그 형성 공정을 도시한 단면도.2a to 2c are cross-sectional views showing a plug forming process according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
20 : 전도층21 : 절연막20 conductive layer 21 insulating film
22 : 배리어막23 : 플러그22 barrier film 23 plug
25 : 유동성 절연막25: fluid insulating film
상기와 같은 문제점을 해결하기 위해 본 발명은, 전도층 상에 상기 전도층을 오픈하는 오픈부를 갖는 절연막을 형성하는 단계; 상기 오픈부가 형성된 전체 프로파일을 따라 배리어막을 형성하는 단계; 상기 배리어막 상에 상기 오픈부를 충분히 매립하도록 전도막을 형성하는 단계; 상기 전도막 상에 유동성 절연막을 형성하여 상기 전도막 상의 오목부를 매립 및 평탄화하는 단계; 및 상기 배리어막이 노출될 때까지 상기 유동성 절연막과 상기 전도막을 전면식각하여 상기 오픈부에 매립되며 그 상부가 평탄화된 플러그를 형성하는 단계를 포함하는 반도체 소자 제조 방법을제공한다.The present invention to solve the above problems, forming an insulating film having an open portion for opening the conductive layer on the conductive layer; Forming a barrier film along the entire profile in which the open portion is formed; Forming a conductive film on the barrier film to sufficiently fill the open portion; Forming a fluid insulating film on the conductive film to fill and planarize the recess on the conductive film; And etching the entire surface of the flowable insulating layer and the conductive layer until the barrier layer is exposed to form a plug embedded in the open portion and having a flattened upper portion thereof.
또한, 상기와 같은 문제점을 해결하기 위해 본 발명은, 전도층 상에 상기 전도층을 오픈하는 오픈부를 갖는 절연막을 형성하는 단계; 상기 오픈부가 형성된 전체 프로파일을 따라 배리어막을 형성하는 단계; 상기 배리어막 상에 상기 오픈부를 충분히 매립하도록 전도막을 형성하는 단계; 상기 전도막 상에 유동성 절연막을 형성하여 상기 전도막 상의 오목부를 매립 및 평탄화하는 단계; 및 상기 절연막이 노출될 때까지 상기 유동성 절연막과 상기 전도막 및 상기 배리어막을 전면식각하여 상기 오픈부에 매립되며 그 상부가 평탄화된 플러그를 형성하는 단계를 포함하는 반도체 소자 제조 방법을 제공한다.In addition, the present invention to solve the above problems, forming an insulating film having an open portion for opening the conductive layer on the conductive layer; Forming a barrier film along the entire profile in which the open portion is formed; Forming a conductive film on the barrier film to sufficiently fill the open portion; Forming a fluid insulating film on the conductive film to fill and planarize the recess on the conductive film; And etching the entire surface of the flowable insulating film, the conductive film, and the barrier film until the insulating film is exposed to form a plug which is embedded in the open portion and has a flattened upper portion thereof.
본 발명은 플러그 평탄화 공정시 플러그 물질 증착 후 피복성 및 막평탄성이 우수한 APL(Advanced Planalization Layer) 즉, 유동성 절연막을 증착하여 심이 형성되는 플러그 상부의 오목부를 채움으로써, 평탄화 공정에 따른 심 형성을 유동성 절연막에 의해 억제함으로써, 플러그의 손실을 방지하는 것을 기술적 특징으로 한다.The present invention fills the recesses in the upper part of the plug where the seam is formed by depositing an APL (Advanced Planalization Layer), that is, an excellent planarization layer (APL), that is, an excellent fluidity and film flatness after the deposition of the plug material during the plug planarization process. It is a technical feature to prevent loss of a plug by suppressing by an insulating film.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 첨부한 도면을 참조하여 상세하게 설명하는 바, 도 2a 내지 도 2c는 본 발명의 일실시예에 따른 플러그 형성 공정을 도시한 단면도이다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may more easily implement the present invention. 2c is a cross-sectional view illustrating a plug forming process according to an embodiment of the present invention.
먼저, 도 2a에 도시된 바와 같이 전도층(20) 상의 절연막(21)을 선택적으로 식각하여 전도층(20) 표면을 노출시키는 오픈부(도시하지 않음)를 형성한 다음, 오픈부를 포함한 전체 프로파일을 따라 Ti, TiN, TiSi2, TiW, Ta, TaN 또는 TaW 등을 이용하여 다층의 배리어막(22; 22a, 22b)을 형성한 다음, 전체 구조 상부에 W, Ti, TiN 또는 Al 등을 CVD(화학기상증착; 이하 CVD라 함)법을 이용하여 증착함으로써 플러그(23)를 형성한다.First, as shown in FIG. 2A, an insulating portion 21 on the conductive layer 20 is selectively etched to form an open portion (not shown) exposing the surface of the conductive layer 20, and then the entire profile including the open portion. As a result, a multilayer barrier layer 22 (22a, 22b) is formed using Ti, TiN, TiSi 2 , TiW, Ta, TaN, or TaW, and then CVD W, Ti, TiN, or Al on the entire structure. The plug 23 is formed by vapor deposition using a (chemical vapor deposition; CVD) method.
여기서, 전도층(10)은 소스/드레인 접합, 비트라인 또는 금속배선 등을 모두 포함한다.In this case, the conductive layer 10 includes all of the source / drain junction, the bit line or the metal wiring.
계속해서, 플러그(23) 상부의 오목부(A)를 매립하도록 피복성과 막평탄성이 우수한 APL막 즉, 유동성 절연막(25)을 형성하는 바, 0.1㎛ 이하의 선폭을 갖는 반도체 소자 기술에서는 절연산화막의 갭-필(Gap-fill) 특성에 있어서 콘택홀 등의 스페이스가 감소하고 종횡비(Aspect ratio)가 점점 증가함에 따라 완전한 필링(Filling, 채움)이 불가능하여, 보이드(Void)가 생기는 문제점이 발생하는 바, 이러한 문제점을 해결하기 위해 플로우 특성을 갖는 절연막 즉, 유동성 절연막을 형성하는 기술인 APL막에 대한 연구가 활발히 진행되고 있다.Subsequently, an APL film having excellent coating property and film flatness, that is, a fluid insulating film 25, is formed so as to fill the recess A in the upper portion of the plug 23. In the semiconductor device technology having a line width of 0.1 mu m or less, an insulating oxide film is used. In the gap-fill characteristic of the device, as the space of the contact hole is reduced and the aspect ratio is gradually increased, full filling is impossible and voids occur. In order to solve this problem, researches on an APL film, which is a technology of forming an insulating film having flow characteristics, that is, a fluid insulating film, have been actively conducted.
이러한, APL 박막 기술 중 자기 평탄화 CVD막은 상당히 유동성이 높은 반응 중간체를 형성하는 것으로, 막 형성을 할 때 우수하게 채움 평탄화를 실현할 수 있다. 그 때문에 평탄화된 층간절연막 형성을 단일한 공정으로 할 수 있어서 종래의 복잡한 공정에 비해서 공정 비용을 효과적으로 줄일 수 있는 바, 자기 평탄화 CVD막은 저압화학기상증착(Low Pressure Chemical Vapor Deposition; 이하 LPCVD라 함)법을 이용하여 반응소스로 과수(H2O2)와 사일렌(SiH4)을 이용하여 형성하며, 자체적인 플로우 특성을 갖고 있어 갭-필 특성이 우수한 장점이 있다.In such APL thin film technology, the self-planarizing CVD film forms a highly flowable reaction intermediate, which can achieve excellent fill planarization when forming the film. Therefore, the planarized interlayer insulating film can be formed as a single process, and the process cost can be effectively reduced as compared with the conventional complicated process. It is formed by using fruit tree (H 2 O 2 ) and xylene (SiH 4 ) as a reaction source by the method, and has an advantage of excellent gap-fill characteristics because it has its own flow characteristics.
전술한 유동성 절연막의 장점을 요약하면 다음과 같다.The advantages of the above-described fluid insulating film is summarized as follows.
가. 갭-필 특성이 우수하다.end. Good gap-fill characteristics.
나. 막 안정성이 높다.I. Membrane stability is high.
다. 크랙(Crack)과 들뜸(Lifting) 형상이 발생하지 않는다.All. Cracks and lifting shapes do not occur.
라. 650℃ 이하의 온도에서 증착하므로 열경비(Thermal budget)가 낮다.la. The thermal budget is low due to deposition at temperatures below 650 ° C.
마. 1000℃ 이상의 온도에 대한 내성이 있다.hemp. It is resistant to temperatures of at least 1000 ° C.
바. 강한 케미컬에 대한 내성과 평탄성을 갖는다.bar. Strong chemical resistance and flatness.
따라서, 유동성 절연막(25)은 플러그(23) 상의 오목부(A)를 완전히 매립한다.Therefore, the fluid insulating film 25 completely fills the recess A on the plug 23.
한편, 전술한 유동성 절연막(25)은 과수(H2O2)와 사일렌(SiH4)에 의해 형성된 막 뿐만아니라 유동성이 뛰어난 SOG(Spin On Glass)와 SOD(Spin On Dielectric)도 포함할 수 있다.Meanwhile, the above-described fluid insulating layer 25 may include not only a film formed by fruit tree (H 2 O 2 ) and xylene (SiH 4 ) but also excellent spin flow (SOG) and spin on dielectric (SOD). have.
다음으로, 도 2b에 도시된 바와 같이 배리어막(22) 표면이 노출될 때까지 전면식각을 실시하여 플러그(23)를 평탄화 및 이웃하는 전극과 격리시키는 비, 오목부(25)에 잔류하는 유동성 절연막(23)에 의해 오목부(A) 하부로의 심 발생을 억제할 수 있다.Next, as shown in FIG. 2B, the entire surface is etched until the surface of the barrier layer 22 is exposed to planarize and isolate the plug 23 from the neighboring electrodes, and the fluidity remaining in the recess 25 is maintained. By the insulating film 23, the generation of seams below the recess A can be suppressed.
여기서, 전면식각시 식각 타겟을 절연막(21)이 노출되는 시점으로 할 수도 있다.Here, the etching target may be a time point at which the insulating layer 21 is exposed during the entire surface etching.
여기서, 식각가스로는 불소계 가스를 이용하는 바, SF6를 사용하는 것이 바람직하며, 이 때 식각 프로파일을 개선하기 위해 CHF3, Ar 또는 N2등의 가스를 더 첨가한다.Here, as the etching gas, a fluorine-based gas is used, and SF 6 is preferably used. At this time, a gas such as CHF 3 , Ar, or N 2 is further added to improve the etching profile.
따라서, 플러그(23)의 상부는 평탄도가 우수하며 도 2c에 도시된 바와 같이, Al, Cu, Ti, TiN, W, WN, TiW 및 TaW로 이루어지는 그룹으로 부터 선택된 적어도 하나를 이용하여 금속막(24)을 형성할 때, 전술한 보이드에 의해 소자의 특성 열화를 방지할 수 있다..Therefore, the upper portion of the plug 23 is excellent in flatness and as shown in Fig. 2c, a metal film using at least one selected from the group consisting of Al, Cu, Ti, TiN, W, WN, TiW and TaW. When forming 24, the above-mentioned voids can prevent the deterioration of characteristics of the device.
전술한 본 발명은 플러그 형성시 전면식각 과정에서 플러그 상부에 유동성 절연막을 형성함으로써, 이를 식각 배리어 역할을 하도록 함으로써, 플러그 내의 심 발생을 억제하며 보이드 등을 방지할 수 있음을 실시예를 통해 알아 보았다.The present invention described above has been found through the embodiment to form a fluid insulating film on the top of the plug during the front surface etching process to form a plug, thereby acting as an etch barrier, to suppress the generation of seams in the plug and to prevent voids, etc. .
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
전술한 본 발명은, 박막평탄도를 향상시켜 공정 마진을 향상시킬 수 있으며, 소자의 전기적 특성 열화를 최소화할 수 있어, 궁극적으로 반도체 소자의 수율을 향상시킬 수 있는 탁월한 효과를 기대할 수 있다.The present invention described above, the process margin can be improved by improving the flatness of the thin film, it is possible to minimize the deterioration of the electrical characteristics of the device, it can be expected to have an excellent effect that can ultimately improve the yield of the semiconductor device.
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