CN112885812A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN112885812A CN112885812A CN201911198495.2A CN201911198495A CN112885812A CN 112885812 A CN112885812 A CN 112885812A CN 201911198495 A CN201911198495 A CN 201911198495A CN 112885812 A CN112885812 A CN 112885812A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53276—Conductive materials containing carbon, e.g. fullerenes
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Abstract
The invention relates to a semiconductor structure and a forming method thereof, which can improve the reliability and stability of a semiconductor device using an interconnection layer. The semiconductor structure includes: a substrate; a first device layer and a second device layer sequentially formed over the substrate; a dielectric layer formed between the first device layer and the second device layer, wherein a metal layer is embedded in the dielectric layer, and a first end and a second end of the metal layer are respectively exposed out of the upper bottom surface and the lower bottom surface of the dielectric layer; and a barrier layer is formed on the outer surface of the metal layer to wrap the metal layer so as to prevent electromigration among metal ions in the metal layer, the first device layer, the second device layer and the dielectric layer.
Description
Technical Field
The invention relates to the field of semiconductor structures, in particular to a semiconductor structure and a forming method thereof.
Background
With the rapid development of semiconductor device manufacturing technology, semiconductor devices have a deep submicron structure, and electrical connection between device layers in a semiconductor device can be realized by means of an interconnection layer formed between the device layers. The interconnection layer comprises a dielectric layer and a metal layer embedded in the dielectric layer, and the metal layer is connected with the conductive area of the device layer so as to form electric connection between the device layers at different heights.
In the prior art, when an interconnection layer is adopted to connect an upper device layer and a lower device layer in a semiconductor device, faults such as unstable current and the like are easy to occur in the using process, and the reliability and the stability of the semiconductor device using the interconnection layer are influenced.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can improve the reliability and stability of a semiconductor device using an interconnection layer.
In order to solve the above technical problem, the following provides a semiconductor structure comprising: a substrate; a first device layer and a second device layer sequentially formed over the substrate; a dielectric layer formed between the first device layer and the second device layer, wherein a metal layer is embedded in the dielectric layer, and a first end and a second end of the metal layer are respectively exposed out of the upper bottom surface and the lower bottom surface of the dielectric layer; and a barrier layer is formed on the outer surface of the metal layer to wrap the metal layer so as to prevent electromigration among metal ions in the metal layer, the first device layer, the second device layer and the dielectric layer.
Optionally, the metal layer comprises a copper layer.
Optionally, the barrier layer includes a first sub-layer formed on the top surface, the bottom surface, and the sidewall of the metal layer.
Optionally, the barrier layer further includes a second sublayer, and the second sublayer is formed on a surface of the first sublayer.
Optionally, the second sub-layer includes at least a first portion formed under the metal layer, and at least a second portion formed between the first sub-layer and the dielectric layer.
Optionally, the first sublayer comprises a graphene layer.
Optionally, the second sub-layer includes at least one of a tantalum layer or a tantalum nitride layer.
In order to solve the above technical problem, the following further provides a method for forming a semiconductor structure, including the steps of: providing a substrate, wherein a first device layer is formed above the substrate; forming a dielectric layer on the upper surface of the first device layer; forming an opening in the dielectric layer, wherein the opening penetrates through the dielectric layer in the direction vertical to the surface of the substrate; forming a barrier layer on the upper surface of the first device layer exposed by the opening and the surface of the side wall of the opening; forming a metal layer in the opening where the barrier layer is formed; forming the barrier layer on the upper surface of the metal layer; and forming a second device layer on the upper surface of the barrier layer.
Optionally, when the barrier layer is formed on the upper surface of the first device layer exposed by the opening and the sidewall surface of the opening, a second sub-layer of the barrier layer is formed on the upper surface of the first device layer exposed by the opening and the sidewall of the opening, and then a first sub-layer of the barrier layer is formed on the surface of the second sub-layer.
Optionally, the barrier layer formed on the upper surface of the metal layer includes a first sub-layer.
According to the semiconductor structure and the forming method thereof, the dielectric layer embedded with the metal layer is arranged between the two device layers needing to be interconnected, and the barrier layer is arranged on the periphery of the metal layer, so that the phenomenon that air bubbles are generated in the metal layer due to unexpected electromigration between the metal and the dielectric layer and between the first device layer and the second device layer can be prevented, the influence of the air bubbles in the metal layer on the reliability and stability of the finally formed semiconductor device is avoided, and the preparation yield of the semiconductor device is effectively improved. Further, since the first sublayer includes the graphene layer, conductivity between the metal layer and the device layer may be improved.
Drawings
FIG. 1 is a cross-sectional view of a semiconductor structure according to an embodiment of the present invention.
FIG. 2 is a flow chart illustrating a method of forming a semiconductor structure formed in accordance with one embodiment of the present invention.
Fig. 3a to 3g are schematic views of a semiconductor structure corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Detailed Description
Research finds that in the prior art, when the interconnection layer is used for connecting two device layers at different heights in the semiconductor device, faults such as unstable current and the like are easy to occur, and the reliability and the stability are low.
A semiconductor structure and a method for forming the same according to the present invention are described in further detail below with reference to the accompanying drawings and the detailed description.
Fig. 1 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the invention.
In this particular embodiment, a semiconductor structure is provided, comprising: a substrate 100; a first device layer 101 and a second device layer 102 sequentially formed over the substrate 100; a dielectric layer 103 formed between the first device layer 101 and the second device layer 102, a metal layer 105 embedded in the dielectric layer 103, wherein a first end and a second end of the metal layer 105 are respectively exposed on an upper bottom surface and a lower bottom surface of the dielectric layer 103; a barrier layer 104 is formed on the outer surface of the metal layer 105 to wrap the metal layer 105, so as to prevent electromigration between metal ions in the metal layer 105 and the first device layer 101, the second device layer 102 and the dielectric layer 103.
In this embodiment, the dielectric layer 103 inlaid with the metal layer 105 is disposed between two device layers to be interconnected in the semiconductor structure, and the barrier layer 104 is disposed on the periphery of the metal layer 105 to wrap the metal layer 105, so that bubbles generated in the metal layer 105 due to unexpected electromigration between the metal and the dielectric layer 103, and between the first device layer 101 and the second device layer 102 can be prevented, the bubbles in the metal layer 105 are prevented from affecting the reliability and stability of the finally formed semiconductor device, and the preparation yield of the semiconductor device is effectively improved.
Referring to fig. 1, the first device layer 101 and the second device layer 102 have conductive devices, which are in direct contact or indirect contact with the finally formed metal layer 105, so as to realize the current flow between the two device layers.
In one embodiment, the dielectric layer 103 comprises a low-k dielectric layer, such as fluorosilicate glass. The low-dielectric-constant dielectric layer with the inlaid metal is used as the interconnection layer between the two device layers, so that the speed of a finally produced semiconductor chip can be increased, the power consumption and the cost of the semiconductor chip can be reduced, the electromigration resistance can be improved, and the like.
In this embodiment, the barrier layer 104 can block the metal layer 105 from electromigration toward the dielectric layer 103, so as to avoid void defects caused by electromigration in the metal layer 105, which affects reliability and stability of the finally formed semiconductor structure.
In one embodiment, the metal layer 105 comprises a copper layer. In fact, the metal layer 105 may also be made of a conductive metal such as aluminum, but copper has better resistivity and can have smaller parasitic capacitance when forming an interconnection line, the metal layer 105 has lower power consumption when passing the same amount of current, and copper has better electrical mobility than aluminum. Therefore, the copper is adopted as the interconnection metal, so that the finally formed semiconductor device has higher reliability.
In one embodiment, the barrier layer 104 includes a first sublayer 1042 formed on the top, bottom, and sidewalls of the metal layer 105. The first sub-layer 1042 can be used to isolate the undesired electromigration between the metal layer 105 and the first device layer 101, between the metal layer 105 and the second device layer 102, and between the metal layer 105 and the dielectric layer 103, thereby effectively reducing the formation of voids in the metal layer 105.
In one embodiment, the barrier layer 104 further includes a second sublayer 1041, and the second sublayer 1041 is formed on the surface of the first sublayer 1042. The two sub-layers are provided to further improve the electromigration resistance of the barrier layer 104.
In one embodiment, the second sub-layer 1041 includes at least a first portion formed under the metal layer 105 and a second portion formed between at least the first sub-layer 1042 and the dielectric layer 103. In this embodiment, only one first sublayer 1042 is disposed on the upper surface of the metal layer 105, which can effectively simplify the processing procedure, and actually, one second sublayer 1041 may be further disposed on the upper surface of the first sublayer 1042 according to the requirement.
In one embodiment, the first sublayer 1042 comprises a graphene layer. In this particular embodiment, the graphene layer may promote conductivity between the metal layer 105 and the first device layer 101. In fact, other materials may be disposed as the first sublayer 1042 according to the requirement, and it should be noted that the first sublayer 1042 has a blocking function, so as to prevent the metal layer 105 from electromigration or oxidation, improve the adhesion between the metal layer 105 and the dielectric layer, and prevent the conductivity of the metal layer 105 from being deteriorated.
In this embodiment, the thickness of the first sub-layer 1042 is 5nm, and in fact, as long as the thickness of the first sub-layer 1042 is within a range of 1 nm to 10nm, better electromigration resistance can be achieved.
In a specific embodiment, the second sub-layer 1041 includes at least one of a tantalum layer or a tantalum nitride layer. In a specific embodiment, the thickness of the second sub-layer 1041 is 50nm, and in fact, as long as the thickness range of the second sub-layer 1041 is within a range of 20 nm to 80nm, better electromigration resistance can be achieved.
In one embodiment, a plurality of methods such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, sputtering process, etc. may be used to form the first sublayer 1042 and the second sublayer 1041. In this embodiment, the first sublayer 1042 and the second sublayer 1041 are formed by chemical vapor deposition at about 1000 ℃, under normal pressure and with a carbon source of CH4The carrier gas is Ar, H2Used as a catalyst.
Referring to fig. 1, 2, and 3a to 3g, fig. 2 is a schematic flow chart illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention, and fig. 3a to 3g are schematic views illustrating semiconductor structures corresponding to the steps of the method for forming a semiconductor structure according to an embodiment of the present invention.
In this embodiment, there is also provided a method of forming a semiconductor structure, comprising: s21 providing a substrate 100, a first device layer 101 is formed on the substrate 100, please refer to fig. 3 a; s22 forming a dielectric layer 103 on the upper surface of the first device layer 101, please refer to fig. 3 b; s23 forming an opening 301 in the dielectric layer 103 through the dielectric layer 103 in a direction perpendicular to the surface of the substrate 100, see fig. 3 c; s24 forming a barrier layer 104 on the upper surface of the first device layer 101 exposed by the opening 301 and the sidewall surface of the opening 301, please refer to fig. 3d, e; s25 forming a metal layer 105 in the opening 301 formed with the barrier layer 104, please refer to fig. 3 f; s26 forming the barrier layer 104 on the upper surface of the metal layer 105, please refer to fig. 3 g; s27, a second device layer 102 is formed on the barrier layer 104, as shown in fig. 1.
As can be seen from fig. 1 and 3, the interconnection layer formed by the dielectric layer 103 and the metal layer 105 can connect the conductive devices in the first device layer 101 and the second device layer 102.
In the specific embodiment, in the method for forming the semiconductor structure, the dielectric layer 103 embedded with the metal layer 105 is arranged between two device layers to be interconnected, and the barrier layer 104 is arranged on the periphery of the metal layer 105, so that bubbles in the metal layer 105 caused by unexpected electromigration between the metal and the dielectric layer 103 and between the first device layer 101 and the second device layer 102 can be prevented, the reliability and stability of a finally formed semiconductor device are prevented from being influenced by the bubbles in the metal layer 105, and the preparation yield of the semiconductor device is effectively improved.
In one embodiment, when the barrier layer 104 is formed on the upper surface of the first device layer 101 exposed by the opening 301 and on the sidewall surface of the opening 301, the second sub-layer 1041 of the barrier layer 104 is formed on the upper surface of the first device layer 101 exposed by the opening 301 and on the sidewall of the opening 301, and then the first sub-layer 1042 of the barrier layer 104 is formed on the surface of the second sub-layer 1041.
The first sublayer 1042 formed here is finally sandwiched by the metal layer 105 and the second sublayer 1041. In one embodiment, the first sublayer 1042 comprises a graphene layer. The graphene layer may promote conductivity between the metal layer 105 and the first device layer 101. In fact, other materials may be disposed as the first sublayer 1042 according to the requirement, and it should be noted that the first sublayer 1042 has a blocking function, so as to prevent the metal layer 105 from electromigration or oxidation, improve the adhesion between the metal layer 105 and the dielectric layer, and prevent the conductivity of the metal layer 105 from being deteriorated.
In this embodiment, the thickness of the first sub-layer 1042 is 5nm, and in fact, as long as the thickness of the first sub-layer 1042 is within a range of 1 nm to 10nm, better electromigration resistance can be achieved.
In a specific embodiment, the second sub-layer 1041 includes at least one of a tantalum layer or a tantalum nitride layer. In a specific embodiment, the thickness of the second sub-layer 1041 is 50nm, and in fact, as long as the thickness range of the second sub-layer 1041 is within a range of 20 nm to 80nm, better electromigration resistance can be achieved.
In one embodiment, a plurality of methods such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, sputtering process, etc. may be used to form the first sublayer 1042 and the second sublayer 1041. In this embodiment, the first sublayer 1042 and the second sublayer 1041 are formed by physical vapor deposition.
In one embodiment, the opening 301 is formed in the dielectric layer 103 by a directional dry etch.
In one embodiment, when the opening 301 is formed, an etch stop layer needs to be formed at the bottom of the dielectric layer 103, i.e., between the dielectric layer 103 and the first device layer 101, so as to prevent the first device layer 101 from being etched when the opening 301 is formed by etching, which causes the substance in the first device layer 101 to be sputtered into the newly formed opening 301, resulting in the failure of the finally formed device.
In forming the opening 301, the shape of the opening 301 is set as needed. In a specific embodiment, a dual damascene-process metal interconnect is to be formed between the first device layer 101 and the second device layer 102, and the dual damascene-process metal interconnect is composed of a metal layer 105 in a dielectric layer 103. In forming the opening 301 into which the metal layer 105 is filled, it is first determined that the opening 301 into which the metal layer 105 is filled should have two parts, i.e., a via hole, and a trench disposed above the via hole. In this embodiment, it is necessary to form two dielectric layers 103, and form vias and trenches in the two dielectric layers 103, respectively. It should be noted that the through holes and the trenches are communicated.
Specifically, first, a first dielectric layer 103 is formed on the upper surface of the first device layer 101, and then an etching stop layer is formed on the upper surface of the first dielectric layer 103 for determining the etching depth. Then, a second dielectric layer 103 is formed on the upper surface of the etching stop layer.
When forming the opening 301, a first photoresist layer is formed on the second dielectric layer 103. In some embodiments, an Organic Anti-Reflective Coating (oar) or the like is further disposed between the first photoresist layer and the second dielectric layer 103 to ensure a photolithography effect. After the first photoresist layer is formed, photoetching the first photoresist layer to form a pattern which is consistent with the cross section pattern of the through hole on the surface of the first photoresist layer, wherein the projection of the pattern on the surface of the substrate 100 is superposed with the projection of the through hole on the surface of the substrate 100. And then, transferring the pattern to a second photoresist layer and a first photoresist layer in sequence, and forming a required through hole in the first photoresist layer.
Then, after removing the first photoresist layer and the oar c organic anti-reflective coating, a second photoresist layer and an oar c organic anti-reflective coating are formed on the surface of the second dielectric layer 103. In this embodiment, the second photoresist layer is photo-etched to form a pattern on the surface of the second photoresist layer, which is consistent with the cross-sectional pattern of the trench, and the projection of the pattern on the surface of the substrate 100 is coincident with the projection of the trench on the surface of the substrate 100. And then, transferring the pattern to the second photoresist layer to form a groove in the second photoresist layer.
To ensure that the through hole is the same as the trench, it is only necessary to ensure that the projection of the pattern formed by patterning the first photoresist layer and the second photoresist layer on the surface of the substrate 100 has an overlapping region. In one embodiment, the pattern formed by patterning the first photoresist layer is completely covered by the pattern formed by patterning the second photoresist layer.
In this embodiment, the via hole is communicated with the trench, and the metal filling can be completed at one time when the metal layer 105 is formed by filling the metal.
In one embodiment, the barrier layer 104 formed on the upper surface of the metal layer 105 includes a first sublayer 1042.
In one embodiment, when forming the metal layer 105 in the opening 301 where the barrier layer 104 is formed, a copper seed is first formed on the barrier layer 104 formed on the upper surface of the first device layer 101, and then electrochemical copper plating is performed.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A semiconductor structure, comprising:
a substrate;
a first device layer and a second device layer sequentially formed over the substrate;
a dielectric layer formed between the first device layer and the second device layer, wherein a metal layer is embedded in the dielectric layer, and a first end and a second end of the metal layer are respectively exposed out of the upper bottom surface and the lower bottom surface of the dielectric layer;
the device is characterized in that a barrier layer is formed on the outer surface of the metal layer to wrap the metal layer so as to prevent electromigration from occurring between metal ions in the metal layer and the first device layer, the second device layer and the dielectric layer.
2. The semiconductor structure of claim 1, wherein the metal layer comprises a copper layer.
3. The semiconductor structure of claim 1, wherein the barrier layer comprises a first sublayer formed on a top surface, a bottom surface, and sidewalls of the metal layer.
4. The semiconductor structure of claim 3, wherein the barrier layer further comprises a second sublayer formed on a surface of the first sublayer.
5. The semiconductor structure of claim 4, wherein the second sub-layer comprises at least a first portion formed under the metal layer and at least a second portion formed between the first sub-layer and the dielectric layer.
6. The semiconductor structure of claim 3, wherein the first sublayer comprises a graphene layer.
7. The semiconductor structure of claim 4, wherein the second sublayer comprises at least one of a tantalum layer or a tantalum nitride layer.
8. A method for forming a semiconductor structure, comprising:
providing a substrate, wherein a first device layer is formed above the substrate;
forming a dielectric layer on the upper surface of the first device layer;
forming an opening in the dielectric layer, wherein the opening penetrates through the dielectric layer in the direction vertical to the surface of the substrate;
forming a barrier layer on the upper surface of the first device layer exposed by the opening and the surface of the side wall of the opening;
forming a metal layer in the opening where the barrier layer is formed;
forming the barrier layer on the upper surface of the metal layer;
and forming a second device layer on the upper surface of the barrier layer.
9. The method as claimed in claim 8, wherein the barrier layer is formed on the upper surface of the first device layer exposed by the opening and the sidewall of the opening, a second sub-layer of the barrier layer is formed on the upper surface of the first device layer exposed by the opening and the sidewall, and a first sub-layer of the barrier layer is formed on the surface of the second sub-layer.
10. The method of claim 8, wherein the barrier layer formed on the top surface of the metal layer comprises a first sub-layer.
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