KR20030049585A - Method for forming etch monitoring box in dual damascene process - Google Patents
Method for forming etch monitoring box in dual damascene process Download PDFInfo
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- KR20030049585A KR20030049585A KR1020010079827A KR20010079827A KR20030049585A KR 20030049585 A KR20030049585 A KR 20030049585A KR 1020010079827 A KR1020010079827 A KR 1020010079827A KR 20010079827 A KR20010079827 A KR 20010079827A KR 20030049585 A KR20030049585 A KR 20030049585A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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Abstract
Description
본 발명은 듀얼 다마신 공정을 이용한 금속배선 형성방법에 관한 것으로, 특히, 금속막의 연마후에 다층 구조로 이루어진 층간절연막의 손실 정도를 신뢰성있게 측정하기 위한 식각 모니터링 박스 형성방법에 관한 것이다.The present invention relates to a metal wiring forming method using a dual damascene process, and more particularly, to an etching monitoring box forming method for reliably measuring the degree of loss of an interlayer insulating film having a multilayer structure after polishing the metal film.
주지된 바와 같이, 금속배선은 RIE(Reaction Ion Etching) 공정, 즉, 금속막 상에 마스크 패턴을 형성한 후, RIE 공정으로 상기 금속막을 직접 식각하는 방법으로 형성되어져 왔다. 그런데, 상기 RIE 공정을 이용한 방법은 금속배선의 임계 치수(critical dimension)가 감소되고 있는 추세에서, 그 전기적 특성의 확보가 어려운 문제점이 있는 바, 새로운 방식의 금속배선 공정이 필요하게 되었다.As is well known, metal wiring has been formed by a method of directly etching the metal film by a Reaction Ion Etching (RIE) process, that is, after forming a mask pattern on the metal film. However, the method using the RIE process has a problem that it is difficult to secure the electrical characteristics in the trend that the critical dimension of the metal wiring is reduced, a new method of metal wiring is required.
그 하나의 방법으로서 다마신(Damascene) 공정이 제안되었다. 상기 다마신 공정은 RIE 공정에 의한 금속배선 형성방법 보다 상대적으로 우수한 전기적 특성을 얻을 수 있기 때문에 반도체 소자의 고집적화 추세에서 그 이용이 확대되리라 예상된다. 특히, 금속배선의 재질이 기존의 알루미늄에서 텅스텐 또는 구리로 변경되는 추세에서, 기존의 식각 공정으로는 구리막의 식각 매우 어렵기 때문에 상기 다마신 공정의 적용은 필수가 될 것으로 예상된다.As one method, the damascene process has been proposed. The damascene process is expected to expand its use in the trend of high integration of semiconductor devices because it can obtain relatively superior electrical properties than the metallization method by the RIE process. In particular, in the trend that the material of the metal wiring is changed from conventional aluminum to tungsten or copper, it is expected that the application of the damascene process is required because the etching of the copper film is very difficult with the conventional etching process.
이러한 다마신 공정을 이용한 다층금속배선 형성방법을 간략하게 설명하면 다음과 같다.Brief description of the method for forming a multi-layer metal wiring using the damascene process is as follows.
먼저, 소정의 하부패턴들이 형성된 반도체 기판 상에 확산방지막을 포함한 하층의 구리 금속배선을 형성한 상태에서, 상기 반도체 기판의 전 영역 상에 제1층간절연막을 형성하고, 그런다음, 상기 구리 금속배선이 노출되도록 제1층간절연막에 대한 CMP(Chemical Mechanical Polishing) 공정을 수행한다.First, a first interlayer insulating film is formed over the entire area of the semiconductor substrate in a state in which a lower copper metal wiring including a diffusion barrier film is formed on a semiconductor substrate on which predetermined lower patterns are formed. Then, the copper metal wiring A chemical mechanical polishing (CMP) process is performed on the first interlayer insulating film so as to expose it.
다음으로, 상기 제1층간절연막 상에 제1식각정지막, 제1절연막, 제2식각정지막 및 제2절연막의 다층 구조로 이루어진 제2층간절연막을 형성한 상태에서, 2회의 마스킹 및 식각 공정을 수행하여 상기 제1층간절연막 내에 하층의 구리 금속배선을노출시키는 비아홀을 포함한 상층의 금속배선 형성 영역을 한정하는 트렌치를 형성한다. 여기서, 상기 제1 및 제2식각정지막은 통상 실리콘질화막으로 형성되며, 상기 제1 및 제2절연막은 통상 저유전율(low-k) 물질로 형성된다.Next, two masking and etching processes are performed on the first interlayer insulating film in a state in which a second interlayer insulating film having a multilayer structure of a first etch stop film, a first insulating film, a second etch stop film, and a second insulating film is formed. A trench is formed in the first interlayer insulating film to define an upper metal wiring forming region including a via hole for exposing a lower copper metal wiring. Here, the first and second etch stop layers are usually formed of silicon nitride, and the first and second insulating layers are usually formed of a low-k material.
그 다음, 상기 비아홀 및 트렌치 표면에 확산방지막을 증착하고, 이어서, 상기 비아홀 및 트렌치 내에 구리막을 증착한 후, 이에 대한 CMP를 수행하여 상층의 구리 금속배선을 형성한다.Next, a diffusion barrier film is deposited on the via hole and the trench surface, and a copper film is then deposited in the via hole and the trench, and then CMP is performed to form an upper copper metal wiring.
여기서, 상기 상층의 구리 금속배선을 형성하기 위한 CMP시에는 필연적으로 층간절연막의 손실이 발생하게 된다. 따라서, 균일한 공정 유지를 위해서는 상기 층간절연막의 손실 정도를 정확하게 측정하는 것이 필수적이다.In this case, a loss of an interlayer insulating film is inevitably generated during CMP for forming the upper copper metal wiring. Therefore, in order to maintain a uniform process, it is essential to accurately measure the degree of loss of the interlayer insulating film.
그러나, 듀얼 다마신 공정에 적용되는 층간절연막은 저유전율 물질과 실리콘질화막의 다층 구조로 구성되기 때문에, 이렇게 다층으로 구성된 층간절연막의 경우, 엘립소미터(ellipsometer)와 같은 광학 측정장비로는 그 두께 측정에 대한 정확도가 떨어져서 그 값을 신뢰할 수 없고, 그래서, 다층배선 구조에서 다마신 공정에 따른 층간절연막의 두께 균일도를 유지하는데 어려움이 있다.However, since the interlayer insulating film applied in the dual damascene process is composed of a multi-layer structure of a low dielectric constant material and a silicon nitride film, the thickness of the interlayer insulating film composed of such multilayers is not limited to the optical measuring equipment such as an ellipsometer. The accuracy of the measurement is poor and its value is not reliable, and therefore, there is a difficulty in maintaining the thickness uniformity of the interlayer insulating film according to the damascene process in the multilayer wiring structure.
또한, 최근에는 하층 및 상층 금속배선들간의 저항 측정을 통해 층간절연막의 두께를 간접적으로 측정하거나, 또는, 소나(sonar) 방식의 측정장비를 사용하여 층간절연막의 두께를 직접적으로 측정하기도 하는데, 전자의 방법은 정확한 값을 얻지 못함은 물론 재현성이 떨어진다는 단점이 있고, 후자의 방법은 측정 장비의 가격이 매우 비싸다는 단점이 있는 바, 실질적으로 그 이용에 어려움이 있다.In recent years, the thickness of the interlayer insulating film may be indirectly measured by measuring the resistance between the lower and upper metal wires, or the thickness of the interlayer insulating film may be directly measured by using a sonar measuring instrument. The method has the disadvantage of not obtaining the correct value as well as the poor reproducibility, the latter method has the disadvantage that the price of the measuring equipment is very expensive, practically difficult to use.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 다층 구조의 층간절연막 두께를 신뢰성있게 모니터링할 수 있는 듀얼 다마신 공정에서의 식각 모니터링 박스(Etch monitoring Box) 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, to provide a method for forming an etching monitoring box in the dual damascene process that can reliably monitor the thickness of the interlayer insulating film of a multi-layer structure. There is a purpose.
도 1은 듀얼 다마신 공정에서의 다층 구조의 층간절연막을 도시한 단면도.1 is a cross-sectional view showing an interlayer insulating film of a multilayer structure in a dual damascene process.
도 2는 본 발명의 실시예에 따라 형성된 듀얼 다마신 공정에서의 식각 모니터링 박스를 도시한 단면도.2 is a cross-sectional view illustrating an etch monitoring box in a dual damascene process formed in accordance with an embodiment of the invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
11 : 반도체 기판 12 : 제1층간절연막11 semiconductor substrate 12 first interlayer insulating film
13 : 확산방지막 14 : 구리 금속배선13 diffusion barrier 14 copper metal wiring
15 : 제2층간절연막 15a : 제1식각정지막15: second interlayer insulating film 15a: first etch stop film
15b : 제1절연막 15c : 제2식각정지막15b: first insulating film 15c: second etch stop film
15d : 제2절연막 16 : 절연막15d: second insulating film 16: insulating film
상기와 같은 목적을 달성하기 위한 본 발명의 듀얼 다마신 공정에서의 식각 모니터링 박스 형성방법은, 듀얼 다마신 공정에서 금속막의 연마후에 다층 구조로 이루어진 층간절연막의 손실 정도를 측정하기 위한 식각 모니터링 박스 형성방법에 있어서, 하층의 금속배선이 형성된 반도체 기판 상에 식각방지막과 저유전율막이 순차로 적층된 다층 구조의 층간절연막을 형성하는 단계; 상기 층간절연막을 식각하여 상기 하층의 금속배선을 노출시키는 콘택홀을 형성하는 단계; 상기 콘택홀이 매립되도록 단일층의 절연막을 증착하는 단계; 및 상기 절연막과 다층 구조의 층간절연막간의 단차가 제거되도록 상기 절연막을 연마하는 단계를 포함하며, 여기서, 상기 절연막은 저유전율(low-k) 물질, USG, TEOS, FSG, SOG 및 HSQ로 이루어지는 그룹으로부터 선택되는 어느 하나로 이루어진다.Etch monitoring box forming method in the dual damascene process of the present invention for achieving the above object, forming an etching monitoring box for measuring the degree of loss of the interlayer insulating film of a multi-layer structure after polishing the metal film in the dual damascene process. A method comprising: forming an interlayer insulating film having a multilayer structure in which an etch stop film and a low dielectric constant film are sequentially stacked on a semiconductor substrate on which a lower metal wiring is formed; Etching the interlayer insulating film to form a contact hole exposing the metal wiring of the lower layer; Depositing a single layer of insulating film to fill the contact hole; And polishing the insulating film so that a step between the insulating film and the interlayer insulating film of the multilayer structure is removed, wherein the insulating film is a group consisting of a low-k material, USG, TEOS, FSG, SOG, and HSQ. It is made of any one selected from.
본 발명에 따르면, 실질적인 듀얼 다마신 공정을 진행하기 전에 다층 구조로 이루어진 층간절연막의 일부분을 식각한 후, 식각 부분에 단일층의 절연막을 매립시키고, 아울러, CMP를 통해 상기 절연막과 다층 층간절연막간의 표면 단차를 제거함으로써, 상기 단일 절연막의 두께 측정을 통해 다층 층간절연막의 두께를 신뢰성있게 측정할 수 있다.According to the present invention, a portion of the interlayer insulating film having a multi-layer structure is etched prior to performing the dual dual damascene process, and then a single layer of insulating film is embedded in the etching portion, and between the insulating film and the multilayer interlayer insulating film through CMP. By removing the surface step, it is possible to reliably measure the thickness of the multilayer interlayer insulating film by measuring the thickness of the single insulating film.
(실시예)(Example)
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
전술한 바와 같이, 종래의 듀얼 다마신 공정은 다층 구조의 층간절연막을 형성하는 공정과, 상기 층간절연막의 식각을 통해 비아홀 및 트렌치 형성하는 공정, 상기 비아홀 및 트렌치를 매립하도록 금속막을 증착하는 공정, 및 상기 금속막의 CMP하는 공정의 순으로 진행된다.As described above, the conventional dual damascene process includes forming an interlayer insulating film having a multilayer structure, forming a via hole and a trench through etching the interlayer insulating film, depositing a metal film to fill the via hole and the trench, And the step of CMPing the metal film.
여기서, 상기 금속막의 CMP시에는 필연적으로 층간절연막의 식각 손실이 발생하게 되는데, 본 발명의 이러한 층간절연막의 식각 손실 정도를 정확하게 측정하기 위해 다음과 같은 방법으로 식각 모니터링 박스를 형성한다.Here, in the CMP of the metal film, an etch loss of the interlayer insulating film is inevitably generated. In order to accurately measure the etch loss of the interlayer insulating film of the present invention, an etching monitoring box is formed by the following method.
도 2는 본 발명의 실시예에 따라 형성된 듀얼 다마신 공정에서의 식각 모니터링 박스를 도시한 단면도로서, 이를 참조하여 그 형성방법을 설명하도록 한다.FIG. 2 is a cross-sectional view illustrating an etching monitoring box in a dual damascene process formed according to an exemplary embodiment of the present invention, and a method of forming the same is described below.
먼저, 반도체 기판(11) 상에 제1층간절연막(12)과 확산방지막(13)을 구비한 하층의 구리 금속배선(14)을 형성한 상태에서, 상기 반도체 기판(1)의 전 영역 상에 공지의 듀얼 다마신 공정에 따라 제1식각정지막(15a), 제1절연막(15b), 제2식각정지막(15c) 및 제2절연막(15d)을 차례로 형성하여 다층 구조의 제2층간절연막(15)을 형성한다.First, in a state where the lower copper metal wiring 14 including the first interlayer insulating film 12 and the diffusion barrier film 13 is formed on the semiconductor substrate 11, on the entire region of the semiconductor substrate 1. According to a known dual damascene process, the first etch stop film 15a, the first insulating film 15b, the second etch stop film 15c, and the second insulating film 15d are sequentially formed to form a second interlayer insulating film having a multilayer structure. (15) is formed.
여기서, 상기 하층의 구리 금속배선(14)은 실제 셀 영역에 형성된 것이 아니며, 식각 모니터링 박스의 형성을 위해서, 예컨데, 다이(die) 내의 특정 영역이나 웨이퍼의 스크라이브 라인 영역에 형성시킨 더미(dummy) 금속배선이다. 따라서, 도2에 도시된 다층 구조의 제2층간절연막(15)은 실제 상층의 구리 금속배선이 형성될 기판 영역이 아닌, 식각 모니터링 박스 형성 영역에 도포된 부분을 도시한 것으로 이해될 수 있다.Here, the lower copper metallization 14 is not actually formed in the cell area, and for forming an etch monitoring box, for example, a dummy formed in a specific area in a die or a scribe line area of a wafer. Metal wiring. Accordingly, it may be understood that the second interlayer insulating film 15 of the multilayer structure shown in FIG. 2 shows a portion applied to the etching monitoring box forming region, not the substrate region where the copper metal wiring of the upper layer is to be formed.
계속해서, 실제 듀얼 다마신 공정의 경우에는 상기 제2층간절연막(15)에 대한 2회의 마스킹 및 식각 공정을 수행하여 비아홀 및 트렌치를 형성하지만, 본 발명의 경우에는 상기 비아홀 및 트렌치의 형성 이전에, 식각 모니터링 박스 형성 영역의 제2층간절연막 부분을 식각하여 더미로 형성된 상기 하층의 금속배선(14)을 노출시키는 콘택홀을 형성한다. 그런다음, 상기 콘택홀이 매립되도록 결과물 상에 단일층의 절연막(16)을 증착한다. 여기서, 상기 절연막(16)은 저유전율(low-k)의 물질로 형성하거나, 또는, USG, TEOS, FSG, SOG 및 HSQ 중에서 어느 하나로 형성한다.Subsequently, in the case of the dual damascene process, via holes and trenches are formed by performing two masking and etching processes on the second interlayer insulating layer 15, but in the present invention, the via holes and trenches are formed before the formation of the via holes and trenches. The second interlayer insulating film portion of the etch monitoring box forming region is etched to form a contact hole exposing the metal wiring 14 of the lower layer formed as a dummy. Then, a single layer of insulating film 16 is deposited on the resultant to fill the contact hole. In this case, the insulating layer 16 is formed of a low-k material, or formed of any one of USG, TEOS, FSG, SOG, and HSQ.
이어서, 상기 절연막(16)과 다층 구조로 이루어진 제2층간절연막(15)간의 단차가 제거되도록 상기 절연막(16)을 CMP 공정으로 연마하고, 이 결과로, 본 발명의 식각 모니터링 박스를 완성한다.Subsequently, the insulating film 16 is polished by a CMP process so that the step between the insulating film 16 and the second interlayer insulating film 15 having a multilayer structure is removed. As a result, the etching monitoring box of the present invention is completed.
전술한 바와 같은 본 방법으로 식각 모니터링 박스를 형성하게 되면, 단일층의 절연막과 다층의 제2층간절연막이 동일한 두께를 갖는 것으로 인해, 상기 단일층의 절연막 두께를 측정하는 것으로 상기 다층의 제2층간절연막의 두께를 유추할 수 있고, 이때, 상기 단일층의 절연막은 기존의 광학 측정장비를 이용해서 그 두께를 용이하고, 신뢰성있게 측정할 수 있는 바, 결국, 후속하는 듀얼 다마신 공정에서 금속막의 CMP에 의한 제2층간절연막의 손실이 발생되었을 경우, 상기 절연막의두께 측정을 통해서 제2층간절연막의 손상 정도를 용이하고도 신뢰성있게 측정할 수 있게 된다.When the etching monitoring box is formed by the present method as described above, since the single layer insulating film and the multilayer second interlayer insulating film have the same thickness, the thickness of the single layer insulating layer is measured by measuring the thickness of the single layer insulating film. The thickness of the insulating film can be inferred. In this case, the single-layer insulating film can be easily and reliably measured by using an existing optical measuring device, and as a result, in the subsequent dual damascene process, When the loss of the second interlayer insulating film due to CMP occurs, the degree of damage of the second interlayer insulating film can be easily and reliably measured by measuring the thickness of the insulating film.
이상에서와 같이, 본 발명은 듀얼 다마신 공정에서의 층간절연막의 손상 정도를 측정할 수 있는 식각 모니터링 박스를 형성해 줌으로써, 기존의 측정장비를 이용하면서도 상기 층간절연막의 손상 정도를 신뢰성있게 측정할 수 있으며, 이에 따라, 균일한 공정 유지가 가능하여 제조수율을 향상시킬 수 있음은 물론, 소자의 신뢰성도 향상시킬 수 있다.As described above, the present invention forms an etch monitoring box that can measure the degree of damage of the interlayer insulating film in the dual damascene process, so that the degree of damage of the interlayer insulating film can be reliably measured using existing measuring equipment. As a result, a uniform process can be maintained, thereby improving the manufacturing yield and improving the reliability of the device.
기타, 본 발명은 그 요지가 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.
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CN113809048A (en) * | 2021-08-26 | 2021-12-17 | 联芯集成电路制造(厦门)有限公司 | Semiconductor device with a plurality of semiconductor chips |
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JPH07249667A (en) * | 1994-03-08 | 1995-09-26 | Matsushita Electron Corp | Film thickness measurement method of interlayer film in multilayer wiring |
US5900644A (en) * | 1997-07-14 | 1999-05-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Test site and a method of monitoring via etch depths for semiconductor devices |
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US6323047B1 (en) * | 1999-08-03 | 2001-11-27 | Advanced Micro Devices, Inc. | Method for monitoring second gate over-etch in a semiconductor device |
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CN113809048A (en) * | 2021-08-26 | 2021-12-17 | 联芯集成电路制造(厦门)有限公司 | Semiconductor device with a plurality of semiconductor chips |
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