KR20030049568A - method for fabricating a conductive plug - Google Patents

method for fabricating a conductive plug Download PDF

Info

Publication number
KR20030049568A
KR20030049568A KR1020010079810A KR20010079810A KR20030049568A KR 20030049568 A KR20030049568 A KR 20030049568A KR 1020010079810 A KR1020010079810 A KR 1020010079810A KR 20010079810 A KR20010079810 A KR 20010079810A KR 20030049568 A KR20030049568 A KR 20030049568A
Authority
KR
South Korea
Prior art keywords
silicon layer
impurities
doped
forming
amorphous silicon
Prior art date
Application number
KR1020010079810A
Other languages
Korean (ko)
Inventor
손호민
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020010079810A priority Critical patent/KR20030049568A/en
Publication of KR20030049568A publication Critical patent/KR20030049568A/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

PURPOSE: A method for forming a conductive plug in a semiconductor device is provided to be capable of preventing orientation misfit and dislocation generated at the interface between a substrate and the conductive plug. CONSTITUTION: An interlayer dielectric(202) having a contact hole(203) is formed on a semiconductor substrate(200). An undoped amorphous silicon layer is formed on the interlayer dielectric(202) at the temperature of 450-500°C. A doped polysilicon layer is formed on the undoped amorphous silicon layer at the temperature of 530-600°C. By annealing the resultant structure at the temperature of 700-1000°C, the undoped amorphous silicon layer is transformed into the doped polysilicon layer. The doped polysilicon layer is planarized to expose the interlayer dielectric(202), thereby forming a conductive plug.

Description

도전 플러그 형성방법{method for fabricating a conductive plug}Method for fabricating a conductive plug

본 발명은 반도체장치의 제조방법에 관한 것으로, 보다 상세하게는 디램(DRAM:Dynamic Random Acsess Memory) 소자의 특성을 개선할 수 있는 도전 플러그(conductive plug) 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a conductive plug capable of improving the characteristics of a DRAM (DRAM) device.

디램이 고집적화되고 디자인(design rule)이 작아짐에 따라 배선 등의 도전층과 도전층 사이를 직접 콘택(contact)하기 보다는 도전 플러그 등을 이용하여 간적적으로 연결시키는 경우가 많아지고 있다.As DRAMs become more integrated and design rules become smaller, they are increasingly connected using conductive plugs or the like rather than directly contacting conductive layers such as wiring and the conductive layers.

도 1은 종래 기술에 따른 도전 플러그 형성을 보인 공정단면도이다.1 is a process cross-sectional view showing the formation of a conductive plug according to the prior art.

종래 기술에 따른 도전 플러그 형성방법은, 도 1에 도시된 바와 같이, 반도체기판(100) 상에 BPSG(BPSG:BoroPhosphorSilicate Glass) 등의 절연막(102)을 증착한 후, 포토리쏘그라피 공정에 의해 상기 절연막을 선택 식각하여 콘택홀(103)을 형성한다. 이때, 상기 콘택홀(103) 형성 공정은 플라즈마를 이용한 건식 식각 방식에 의해 진행된다.In the method of forming a conductive plug according to the related art, as illustrated in FIG. 1, an insulating film 102 such as BPSG (BoroPhosphorSilicate Glass) is deposited on a semiconductor substrate 100, and then the photolithography process is performed. The insulating layer is selectively etched to form the contact hole 103. In this case, the contact hole 103 forming process is performed by a dry etching method using plasma.

이어, 상기 층간절연막(102) 상에 콘택홀(103)을 덮도록 불순물이 도핑되지 않은 비정질 실리콘층(106) 및 불순물이 도핑된 다결정 실리콘층(108)을 차례로 증착한다. 이때, 상기 증착 공정은 530∼570℃의 온도에서 진행된다.Subsequently, an amorphous silicon layer 106 which is not doped with impurities and a polycrystalline silicon layer 108 which is doped with impurities are sequentially deposited on the interlayer insulating layer 102 to cover the contact hole 103. At this time, the deposition process is carried out at a temperature of 530 ~ 570 ℃.

그 다음, 상기 불순물이 도핑된 다결정 실리콘층과 불순물이 도핑되지 않은 비정질 실리콘층에 화학적-기계적 연마(Chemical Mechanical Polishing) 공정을 진행하여 콘택홀(103)을 채우는 도전 플러그(미도시)를 형성한다. 이때, 상기 도전 플러그는 비정질 실리콘과 다결정이 혼재되어 있는 상을 가진다.Thereafter, a chemical mechanical polishing process is performed on the polycrystalline silicon layer doped with impurities and the amorphous silicon layer doped with impurities to form a conductive plug (not shown) filling the contact hole 103. . In this case, the conductive plug has a phase in which amorphous silicon and polycrystal are mixed.

종래 기술에서는 플라즈마를 이용한 콘택홀의 건식 식각 공정에서, 기판 표면은 플라즈마에 의한 데미지(demage)를 받아서 비정질화된 상태가 된다.In the prior art, in the dry etching process of a contact hole using plasma, the surface of the substrate is damaged by plasma and is in an amorphous state.

따라서, 도전 플러그 형성용 물질층을 다결정(poly crystal)이 함유된 결정상태로 증착하게 되면, 기판과 만나는 경계 부분에서 기판의 원자와 상기 물질층의 실리콘(Si) 원자 사이에서 방위 이탈(orientation misfit) 및 전위(dislocation)가 생기게 되어 정션(junction) 리키지(leakage)가 발생되는 문제점이 있었다.Therefore, when the conductive plug forming material layer is deposited in a crystalline state containing poly crystal, an orientation misfit between the atoms of the substrate and the silicon (Si) atoms of the material layer at the boundary portion that meets the substrate ) And dislocations, resulting in junction leaks.

이에 본 발명은 상기 종래의 문제점을 해결하기 위해 안출된 것으로, 도전플러그의 실리콘 원자와 기판의 원자 사이에서 발생되는 방위 이탈 및 전위를 방지할 수 있는 도전 플러그 형성방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a conductive plug that can prevent the deviation and dislocation generated between silicon atoms of a conductive plug and atoms of a substrate.

도 1은 종래 기술에 따른 도전 플러그 형성을 보인 공정단면도.1 is a process cross-sectional view showing the formation of a conductive plug according to the prior art.

도 2a 내지 도 2c는 본 발명에 따른 도전 플러그 형성을 보인 공정단면도.Figures 2a to 2c is a cross-sectional view showing the formation of a conductive plug according to the present invention.

도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings

200. 반도체기판 202. 층간절연막200. Semiconductor substrate 202. Interlayer insulating film

203. 콘택홀 210, 22, 230. 열처리203. Contact holes 210, 22, 230. Heat treatment

206. 불순물이 도핑되지 않은 비정질 실리콘층206. Amorphous Silicon Layer Doped with Impurities

208. 불순물이 도핑된 다결정 실리콘층208. Polycrystalline Silicon Layer Doped with Impurities

상기 목적을 달성하기 위한 본 발명의 도전 플러그 형성방법은 반도체 기판 상에 기판의 일부분을 노출시키는 콘택홀을 가진 층간절연막을 형성하는 단계와, 450∼500℃ 온도 하에서, 층간절연막 상에 불순물이 도핑되지 않은 비정질 실리콘층을 형성하는 단계와, 530∼600℃ 온도 하에서, 불순물이 도핑되지 않은 비정질 실리콘층 상에 불순물이 도핑된 다결정 실리콘층을 형성하는 단계와, 상기 결과물에 700∼1000℃ 온도의 열처리를 진행하여 불순물이 도핑되지 않은 비정질 실리콘층을 불순물이 도핑된 다결정 실리콘층으로 변환시키는 단계와, 실리콘층을 식각하여 콘택홀을 채우는 도전 플러그를 형성하는 단계를 포함한 것을 특징으로 한다.The conductive plug forming method of the present invention for achieving the above object is to form an interlayer insulating film having a contact hole for exposing a portion of the substrate on a semiconductor substrate, and doped with impurities on the interlayer insulating film at a temperature of 450 ~ 500 ℃ Forming a non-crystalline amorphous silicon layer, forming a polycrystalline silicon layer doped with impurities on an amorphous silicon layer that is not doped with impurities under a temperature of 530 to 600 ° C., and a temperature of 700 to 1000 ° C. in the resultant product. Performing a heat treatment to convert the amorphous silicon layer not doped with impurities into a polycrystalline silicon layer doped with impurities, and forming a conductive plug to etch the silicon layer to fill the contact hole.

이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2c는 본 발명에 따른 도전 플러그 형성을 보인 공정단면도이다.2A to 2C are cross-sectional views illustrating a process of forming a conductive plug according to the present invention.

본 발명의 도전 플러그 형성방법은, 도 2a에 도시된 바와 같이, 먼저, 반도체기판(200) 상에 BPSG 등의 절연막(202)을 증착한 후, 포토리쏘그라피 공정에 의해 상기 절연막을 선택 식각하여 콘택홀(203)을 형성한다. 이때, 상기 콘택홀(203) 형성 공정은 플라즈마를 이용한 건식 식각 방식에 의해 진행된다.In the conductive plug forming method of the present invention, as shown in FIG. 2A, first, an insulating film 202 such as BPSG is deposited on a semiconductor substrate 200, and then the insulating film is selectively etched by a photolithography process. The contact hole 203 is formed. In this case, the contact hole 203 forming process is performed by a dry etching method using plasma.

이어서, 상기 층간절연막(102) 상에 콘택홀(103)을 덮도록 300∼700Å두께의 불순물이 도핑되지 않은 비정질 실리콘층(206)을 형성한다. 이때, 상기 불순물이 도핑되지 않은 비정질 실리콘층(206)(a-Si) 증착 공정은 CVD챔버(Chemical Vapor Deposition chamber)(미도시) 내에서 화학기상증착 방식에 의해 진행되며, 증착 조건은 450∼500℃ 온도의 제 1열처리(210)를 실시하고, 0.5∼2.0 토르(Torr)의 압력을 유지하며, SiH4가스를 500∼2000 sccm으로 공급한다. 또한 상기 압력 조건에 의해 상기 불순물이 도핑되지 않은 비정질 실리콘층(206)은 1분당 10∼15Å두께만큼 빠른 속도로 증착된다.Subsequently, an amorphous silicon layer 206 which is not doped with a thickness of 300 to 700 Å is formed on the interlayer insulating film 102 to cover the contact hole 103. In this case, the deposition process of the amorphous silicon layer 206 (a-Si) without doping the impurities is performed by a chemical vapor deposition method in a chemical vapor deposition chamber (CVD), and the deposition conditions are 450 to The first heat treatment 210 is performed at a temperature of 500 ° C., and a pressure of 0.5 to 2.0 Torr is maintained, and SiH 4 gas is supplied at 500 to 2000 sccm. In addition, the amorphous silicon layer 206 which is not doped with impurities due to the pressure conditions is deposited at a speed as fast as 10 to 15 Å thickness per minute.

그 다음, 도 2b에 도시된 바와 같이, 상기 불순물이 도핑되지 않은 비정질 실리콘층(202) 상에 1700∼2300Å 두께의 불순물이 도핑된 다결정 실리콘층(208)을 형성한다. 이때, 상기 불순물이 도핑된 다결정 실리콘층(208) 증착 공정은 상기 불순물이 도핑되지 않은 비정질 실리콘층(206) 형성과 동일 CVD챔버 내에서 화학기상증착 방식에 의해 진행되며, 증착 조건은 530∼600℃ 온도의 제 2열처리(220) 실시 하에서 0.5∼1.0 토르의 압력으로 SiH4및 PH3가스를 공급한다. 상기 SiH4: PH3의 가스 비율은 10:1∼8:1이 되며, 상기 SiH4가스는 500∼2000 SCCM 의 유속으로 유입시킨다.Next, as shown in FIG. 2B, a polycrystalline silicon layer 208 doped with an impurity having a thickness of 1700 to 2300 μs is formed on the amorphous silicon layer 202 which is not doped with the impurity. At this time, the deposition process of the doped polycrystalline silicon layer 208 is performed by chemical vapor deposition in the same CVD chamber as the amorphous silicon layer 206 is not doped with impurities, the deposition conditions are 530 ~ 600 SiH 4 and PH 3 gas are supplied at a pressure of 0.5 to 1.0 Torr under the second heat treatment 220 at a temperature of ℃. The gas ratio of SiH 4 : PH 3 is 10: 1 to 8: 1, and the SiH 4 gas is introduced at a flow rate of 500 to 2000 SCCM.

이 후, 도 2c에 도시된 바와 같이, 상기 결과물 상에 빠른 열처리 공정(Rapid Thermal Process)(230)을 진행하여 상기 불순물이 도핑된 다결정 실리콘층(208) 내의 불순물(P)을 하부의 불순물이 도핑되지 않은 비정질 실리콘층(202)으로 확산시키고 결정화시킨다. 따라서, 전체가 불순물이 도핑된 다결정 실리콘층(210)으로 바뀌게 된다. 이때, 상기 빠른 열처리 공정(230)은 700∼1000℃ 온도에서 진행된다.After that, as shown in FIG. 2C, a rapid thermal process 230 is performed on the resultant to remove impurities P in the polycrystalline silicon layer 208 doped with impurities. Diffusion and crystallization into the undoped amorphous silicon layer 202. Thus, the entirety is changed to the polycrystalline silicon layer 210 doped with impurities. At this time, the rapid heat treatment process 230 is performed at a temperature of 700 ~ 1000 ℃.

이 후, 상기 불순물이 도핑된 다결정 실리콘층(210)에 화학적-기계적 연마 공정을 진행하여 콘택홀(203)을 채우는 도전 플러그(미도시)를 형성한다. 이때, 상기 도전 플러그는 불순물이 도핑된 다결정 실리콘 하나의 상을 가진다.Thereafter, a chemical-mechanical polishing process is performed on the impurity-doped polycrystalline silicon layer 210 to form a conductive plug (not shown) filling the contact hole 203. In this case, the conductive plug has one phase of polycrystalline silicon doped with impurities.

이상에서와 같이, 본 발명에서는 도전 플러그 형성용 물질층을 증착하는 데 있어서, 기판과 접촉하고 있는 경계면에 완전한 형태의 비정질 실리콘층을 형성시킴으로써, 결정 방위 이탈에 의한 손상을 감소시키고 전위에 의한 디바이스 손상을 방지할 수 있다.As described above, in the present invention, in forming a conductive plug-forming material layer, by forming a complete amorphous silicon layer on the interface in contact with the substrate, it is possible to reduce damage due to deviation of crystal orientation and device by dislocations. Damage can be prevented.

또한, 불순물이 도핑되지 않은 비정질 실리콘층을 저온 및 고압에서 증착함으로써, 증착속도가 빨라지게 되어 공정시간이 단축된다.In addition, by depositing an amorphous silicon layer that is not doped with impurities at low temperature and high pressure, the deposition speed is increased to shorten the process time.

기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (6)

반도체 기판 상에 상기 기판의 일부분을 노출시키는 콘택홀을 가진 층간절연막을 형성하는 단계와,Forming an interlayer insulating film having a contact hole exposing a portion of the substrate on a semiconductor substrate; 450∼500℃ 온도 하에서, 상기 층간절연막 상에 불순물이 도핑되지 않은 비정질 실리콘층을 형성하는 단계와,Forming an amorphous silicon layer that is not doped with impurities on the interlayer insulating film at a temperature of 450 to 500 ° C., 530∼600℃ 온도 하에서, 상기 불순물이 도핑되지 않은 비정질 실리콘층 상에 불순물이 도핑된 다결정 실리콘층을 형성하는 단계와,Forming a polycrystalline silicon layer doped with impurities on the amorphous silicon layer that is not doped with impurities under a temperature of 530 to 600 ° C, 700∼1000℃ 온도에서 상기 결과물에 열처리를 진행하여 상기 불순물이 도핑되지 않은 비정질 실리콘층을 불순물이 도핑된 다결정 실리콘층으로 변환시키는 단계와,Heat-treating the resultant at a temperature of 700 to 1000 ° C. to convert the amorphous silicon layer not doped with impurities into a polycrystalline silicon layer doped with impurities; 상기 실리콘층을 식각하여 상기 콘택홀을 채우는 도전 플러그를 형성하는 단계를 포함한 것을 특징으로 하는 도전 플러그 형성방법.And etching the silicon layer to form a conductive plug filling the contact hole. 제 1항에 있어서, 상기 불순물이 도핑되지 않은 비정질 실리콘층 형성 공정은 SiH4가스를 500∼2000 sccm으로 공급하는 것을 특징으로 하는 도전 플러그 형성방법.The method of claim 1, wherein the forming of the amorphous silicon layer without doping with impurities supplies SiH 4 gas at 500 to 2000 sccm. 제 1항에 있어서, 상기 불순물이 도핑되지 않은 비정질 실리콘층 형성 공정은 0.5∼2.0토르의 압력을 유지하는 것을 특징으로 하는 도전 플러그 형성방법.The method of claim 1, wherein the forming of the amorphous silicon layer without doping the impurities maintains a pressure of 0.5 to 2.0 Torr. 제 1항에 있어서, 상기 불순물이 도핑된 다결정 실리콘층 형성 공정은 SiH4및 PH3가스를 500∼2000 sccm으로 공급하는 것을 특징으로 하는 도전 플러그 형성방법.The method of claim 1, wherein the impurity doped polycrystalline silicon layer forming process supplies SiH 4 and PH 3 gas at 500 to 2000 sccm. 제 1항에 있어서, 상기 불순물이 도핑된 다결정 실리콘층 형성 공정은 0.5∼1.0토르의 압력을 유지하는 것을 특징으로 하는 도전 플러그 형성방법.The method of claim 1, wherein the impurity doped polycrystalline silicon layer forming process maintains a pressure of 0.5 to 1.0 Torr. 제 4항에 있어서, 상기 SiH4및 PH3가스 비율은 10:1∼ 8:1인 것을 특징으로 하는 도전 플러그 형성방법.The method of claim 4, wherein the SiH 4 and PH 3 gas ratio is 10: 1 to 8: 1.
KR1020010079810A 2001-12-15 2001-12-15 method for fabricating a conductive plug KR20030049568A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020010079810A KR20030049568A (en) 2001-12-15 2001-12-15 method for fabricating a conductive plug

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020010079810A KR20030049568A (en) 2001-12-15 2001-12-15 method for fabricating a conductive plug

Publications (1)

Publication Number Publication Date
KR20030049568A true KR20030049568A (en) 2003-06-25

Family

ID=29575365

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020010079810A KR20030049568A (en) 2001-12-15 2001-12-15 method for fabricating a conductive plug

Country Status (1)

Country Link
KR (1) KR20030049568A (en)

Similar Documents

Publication Publication Date Title
US7176109B2 (en) Method for forming raised structures by controlled selective epitaxial growth of facet using spacer
KR100406580B1 (en) Method for forming contact plug of semiconductor device
KR100596832B1 (en) Method and apparatus for minimizing diffusion in stacked capacitors formed on silicon plugs
KR20040002947A (en) Semiconductor integrated circuit device and production method thereof
KR20000017093A (en) Semiconductor device
US20070022941A1 (en) Method of forming a layer and method of manufacturing a semiconductor device using the same
KR19990001022A (en) Manufacturing Method of Semiconductor Device Having Hemispherical Grain Silicon Film
KR20040025967A (en) Semiconductor device having contact plug using selective epitaxial growth and method of fabricating the same
KR100416376B1 (en) Method of fabricating a memory device
KR100407683B1 (en) Method of forming a contact plug in a semiconductor device
KR100505441B1 (en) Method for fabricating capacitor of semiconductor device
KR20030049568A (en) method for fabricating a conductive plug
KR100364813B1 (en) Method for Forming Epitaxial Layer of Semiconductor Device
KR100524800B1 (en) Method for making contact plug having double doping distribution in semiconductor device
KR100372640B1 (en) Method for forming contact plug using selective epitaxial growth
KR100431302B1 (en) Method of manufacturing system on chip device
JPH01187847A (en) Forming method for capacitor
KR100494127B1 (en) Method for forming plug in semiconductor device
KR100522420B1 (en) Method for forming capacitor having mps grain with improved doping efficiency
KR100335328B1 (en) Method for manufacturing a semiconductor device
CN114695249A (en) Method for manufacturing contact part, bit line, storage node and DRAM
KR100499406B1 (en) method for fabricating capacitor
KR20020050521A (en) Capacitor in semiconductor device and method for manufacturing the same
KR20000043619A (en) Method for fabricating semiconductor device
KR20040096341A (en) Method of manufacturing semicondutor device

Legal Events

Date Code Title Description
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid