KR20030049204A - A method for forming a capacitor of a semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a capacitor of a semiconductor device is provided to be capable of securing the predetermined surface of the storage electrode by carrying out an etching process using the difference of selectivity ratio. CONSTITUTION: A lower insulating layer(11) having a contact plug(13) is formed on a semiconductor substrate. After forming an oxide layer(17) on the resultant structure, a trench is formed by selectively etching the oxide layer using a photolithography process for exposing the contact plug. An HSG(Hemispherical Shaped Glass) type silicon layer(23) is then formed on the resultant structure. A sacrificial layer(25) is formed on the resultant structure for completely filling the trench. After exposing the silicon layer formed on the oxide layer by etching the sacrificial layer, the exposed silicon layer is removed by carrying out a wet etching process using the selectivity ratio difference between the oxide layer and the sacrificial layer.

Description

A method for forming a capacitor of a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a capacitor of a semiconductor device, and more particularly, to prevent deterioration of device characteristics when forming a storage electrode of a capacitor having a metal-insulator-silicon (MIS) structure and using a high-k dielectric film. It's about technology.

As semiconductor devices are highly integrated and cell size is reduced, it is difficult to secure a capacitance that is proportional to the surface area of the storage electrode.

In particular, in a DRAM device having a unit cell composed of one MOS transistor and a capacitor, it is important to reduce the area while increasing the capacitance of a capacitor, which occupies a large area on a chip, which is an important factor for high integration of the DRAM device.

Thus, the capacitance of the capacitor represented by (Eo × Er × A) / T (wherein Eo is the vacuum dielectric constant, Er is the dielectric constant of the dielectric film, A is the area of the capacitor and T is the thickness of the dielectric film) is increased. In order to increase the surface area of the storage electrode, which is a lower electrode, a capacitor was formed.

When the ruthenium film is used as the storage electrode, a capacitor is formed in a concave type in order to secure capacitance.

Although not shown, a method of forming a capacitor of a semiconductor device according to the related art is as follows.

First, a lower insulating layer is formed on a semiconductor substrate.

In this case, the lower insulating layer is formed by forming an isolation layer, a word line, and a bit line, and planarizing an upper portion thereof.

Here, the lower insulating layer is formed of an insulating material having excellent fluidity such as boro phospho silicate glass (BPSG).

A storage electrode contact hole is then formed to expose a predetermined portion of the semiconductor substrate.

In this case, the storage electrode contact hole is formed by etching the lower insulating layer by a photolithography process using a storage electrode contact mask to expose the semiconductor substrate.

A storage electrode contact plug is then formed to fill the storage electrode contact hole.

In this case, the storage electrode contact plug is formed in a stacked structure of a polysilicon film / diffusion prevention film to fill the contact hole.

Here, the diffusion barrier is formed of Ti / TiN.

Next, an oxide layer for a storage electrode is formed on the lower insulating layer, and a storage electrode region for exposing the contact plug is defined by a photolithography process using a storage electrode mask.

Then, a conductive layer for a storage electrode connected to the contact plug is formed on the entire surface. In this case, the storage electrode conductive layer is formed of a silicon film formed with hemispherical polysilicon.

Then, the entire upper surface is coated with an oxide film or a photoresist film to make it planarized, and the substrate is flattened and etched to expose the storage electrode oxide film. Then, the photoresist film of the storage electrode region is removed to form a concave storage electrode.

Here, the CMP method or the etch back method is used as the planarization etching process.

In the CMP method, since a dishing phenomenon occurs in a portion where a cell density is higher in a wafer during a CMP process than a CMP target, surface area is reduced due to a decrease in cell height. In addition, the hemispherical polysilicon acts as a particle to cause a bridge between neighboring cells.

In the etchback method, when the hemispherical polysilicon on the storage electrode oxide film is removed, the storage electrode oxide is etched and the storage electrode silicon film on the sidewall of the storage electrode region is simultaneously etched to decrease the cell height, thereby reducing the surface area. There is a problem coming.

In particular, when the photoresist film is used, the strip process is performed in a plasma environment after the silicon film on the storage electrode oxide film is removed. Thus, the silicon film inside the trench is oxidized by the strip gas during the photoresist film removal process. There is a problem that is significantly reduced.

In order to solve the problems according to the prior art as described above, the present invention effectively prevents the reduction of the height of the storage electrode, secures the stability of the silicon film for the storage electrode, improves the leakage current characteristics, and simultaneously increases the area of the storage electrode. It is an object of the present invention to provide a method for forming a capacitor of a semiconductor device which can secure a process margin of a highly integrated DRAM and can significantly lower a product defect.

1A to 1H are cross-sectional views illustrating a method of forming a capacitor of a semiconductor device in accordance with an embodiment of the present invention.

<Description of Symbols for Major Parts of Drawings>

11: lower insulating layer 13: contact plug

15 etch stop foil 17 oxide film for storage electrode

19: storage electrode region 21: silicon film for the storage electrode

23: hemispherical polysilicon 25: sacrificial oxide film

27: dielectric film 29: upper electrode, plate electrode

In order to achieve the above object, a method of forming a capacitor of a semiconductor device according to the present invention,

Forming a lower insulating layer provided with a contact plug on the semiconductor substrate;

Forming an oxide film for a storage electrode on the lower insulating layer;

Defining a storage electrode region of a trench structure in which the contact plug is exposed by etching the oxide film for the storage electrode by a photolithography process using a storage electrode mask;

Forming a silicon film for a storage electrode on the entire surface including the storage electrode region;

Forming a sacrificial insulating film filling the storage electrode region on the entire surface;

Performing a planarization etching of the sacrificial insulating film to expose the storage electrode silicon film on the storage electrode oxide film, without excessive etching;

Removing the storage electrode silicon film on the storage electrode oxide film by a wet method using an etching selectivity difference between the storage electrode oxide film and the sacrificial insulating film;

Removing the sacrificial insulating film in the storage electrode region to form a storage electrode with a silicon film for storage electrode provided on the surface of the storage electrode region;

A subsequent step of forming a dielectric film and a plate electrode;

The storage electrode oxide film may be formed of a silicon oxide film or a TEOS oxide film formed by a CVD method.

The stacked structure of the oxide film for the storage electrode is formed to a thickness of 6000 ~ 20000 Å,

The storage electrode silicon film may be formed of a stacked structure of a doped silicon film and an undoped silicon film or a single layer structure of an undoped silicon film, and a hemispherical polysilicon may be formed on a surface thereof.

The laminated structure and the single layer structure is formed to 100 ~ 1000 ∼ thickness,

The hemispherical polysilicon is formed by surface treatment of the laminated structure or single layer structure by using a silicon-based gas such as SiH4 and Si2H6 gas as a seeding gas under argon and nitrogen gas atmosphere at 500 to 800 ° C. for 1 to 1000 seconds. To do that,

A CVD oxide film or a photosensitive film is used as the sacrificial insulating film,

The CVD oxide film is formed of any one selected from the group consisting of PSG, BSG, BPSG, AsSG, Al2O3, and combinations thereof, and has a thickness of 1000 to 10000 mm 3,

The photosensitive film is formed to a thickness of 1000 to 20000 mm 3,

The wet etching process may be performed by using an etching selectivity difference between the storage electrode oxide layer, the sacrificial insulating layer, and the storage electrode silicon layer, using a mixed solution having a volume ratio of HF: HNO 3 = 1: 1 to 1000. 2 to 3600 seconds at a temperature of 80 ℃,

The dielectric layer may be formed of ONO (Si-oxide / Si-nitride / Si-oxide), NO, BST ((Ba, Sr) TiO 3), PST ((Pb, Sr) TiO 3), Ta 2 O 5, TaON, TiO 2, Al 2 O 3 and their Forming using any one selected from the group consisting of a combination,

The plate electrode is formed by using a sputtering method, a CVD method or an atomic layer deposition method to form any one selected from TiN, Ru or polysilicon to a thickness of 500 ~ 3000 Å.

Meanwhile, the principle of the present invention is to easily remove only the storage electrode silicon film on the storage electrode oxide film through wet etching.

In more detail, as follows.

The inside of the storage electrode region is filled with a CVD oxide film, that is, a sacrificial oxide film, which has a significantly faster wet etching rate than other oxide films, and is planarized. In this case, the planarization etching process is performed so that the storage electrode silicon film is exposed by the CMP process, but without accompanying excessive etching. In addition, the storage solution may be selectively removed by removing a storage electrode silicon layer on the storage electrode oxide layer with a chemical solution capable of selectively removing only the storage electrode silicon layer having a selectivity difference between the sacrificial oxide layer and the storage electrode oxide layer. The storage electrode is formed of a silicon film without height reduction. In this case, the storage electrode silicon film is provided with hemispherical polysilicon.

In this case, the chemical solution is carried out using a HF / HNO 3 mixed solution, polysilicon is etched 1333 당 per minute, HDP oxide 67 Å per minute in a solution mixed in a volume ratio of HF: HNO3 = 1: 100 at room temperature The photoresist film is not removed.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1A to 1H are cross-sectional views illustrating a method of forming a capacitor of a semiconductor device in accordance with an embodiment of the present invention, which illustrates the formation of a concave capacitor.

Referring to FIG. 1A, a lower insulating layer 11 is formed on a semiconductor substrate (not shown).

In this case, the lower insulating layer 11 is formed by forming an isolation layer (not shown), a word line (not shown), and a bit line (not shown) and planarizing an upper portion thereof.

Here, the lower insulating layer 11 is formed of an insulating material having excellent fluidity, such as BPSG.

Next, a predetermined portion of the lower insulating layer 11 is etched by using a photolithography process using a storage electrode contact mask (not shown) to form a contact hole (not shown) exposing the semiconductor substrate 11 and filling it. A contact plug 13 is formed.

In this case, the contact plug 13 is formed of a laminated structure of polysilicon, a titanium silicide layer, and a titanium nitride film.

Next, an etch stop layer 15 is formed on the entire surface including the lower insulating layer 11, and an oxide layer 17 for a storage electrode is formed thereon.

In this case, the etch stop layer 15 is formed of a silicon nitride layer, and the storage layer oxide layer 17 is formed of a silicon oxide layer or a TEOS oxide layer formed by a CVD method.

The etch stop film 15 and the stacked structure of the oxide film 17 for the storage electrode are formed to a thickness of 6000 ~ 20000 Å.

Referring to FIG. 1B, the storage electrode region 19 exposing the contact plug by etching the storage electrode oxide layer 17 and the etch stop layer 17 by a photolithography process using a storage electrode mask (not shown). Form. In this case, the storage electrode region 19 is provided in the form of a trench in which the contact plug is provided at the bottom.

Referring to FIG. 1C, a storage electrode silicon film 21, which is a lower electrode, is formed on the entire surface including the storage electrode region 19 to a thickness of 100 to 1000 부 에 on the entire surface. In this case, the storage electrode silicon film 21 may be formed in a stacked structure of a doped silicon film and an undoped silicon film connected to the contact plug, or a stacked structure of an undoped silicon film.

Referring to FIG. 1D, a silicon film 23 having hemispherical polysilicon formed on the surface of the storage electrode silicon film 21 is formed.

At this time, the hemispherical polysilicon formed silicon film 23 is formed by surface treatment of the silicon film 21 for 1 to 1000 seconds in an argon and nitrogen gas atmosphere of 500 ~ 800 ℃. Here, the seeding gas of the silicon film 23 in which the hemisphere polysilicon is formed uses a silicon-based gas such as SiH 4 and Si 2 H 6 gas.

Referring to FIG. 1E, a planarized sacrificial insulating film 25 filling the storage electrode region 19 is formed in a CVD method.

In this case, the sacrificial insulating film 25 is formed of an oxide insulating material having excellent fluidity, such as PSG, to have a thickness of 1000 to 10000 μs.

The sacrificial insulating film 23 may be formed of any one selected from the group consisting of BSG, BPSG, AsSG, Al 2 O 3, and a combination thereof.

Here, in the case of using the photosensitive film as the sacrificial insulating film 23, it is formed to a thickness of 1000 ~ 20000 Å.

Referring to FIG. 1F, the sacrificial insulating layer 23 is planarized to expose the silicon layer 23. In this case, the planar etching process is performed by a CMP process, but without excessive etching.

Referring to FIG. 1G, the storage electrode oxide layer 17 is formed by using an etching selectivity difference between the storage electrode oxide layer 17, the sacrificial insulating layer 25, and the silicon layer 23 including the hemispherical polysilicon. The silicon film 23 on which the hemispherical polysilicon is formed is removed.

At this time, the removal process of the silicon film 23 is immersed in a mixed solution having a mixing ratio of HF: HNO3 = 1: 1 to 1000 for 2 to 3600 seconds at a temperature of 4 to 80 ℃.

Next, the sacrificial insulating film 25 inside the storage electrode region 19 is removed to form a concave storage electrode using the silicon film 23 having the hemispherical polysilicon formed thereon.

In this case, the sacrificial insulating film 25 may be removed by using HF solution when the sacrificial insulating film 25 is a CVD oxide film, and removed by a plasma environment or a wet etching method when the sacrificial insulating film 25 is a photosensitive film.

1H forms the dielectric film 27 and the plate electrode 29 on the surface of the storage electrode. At this time, the plate electrode 29 is any selected from the group consisting of ONO, NO, BST ((Ba, Sr) TiO 3), PST ((Pb, Sr) TiO 3), Ta 2 O 5, TaON, TiO 2, Al 2 O 3, and combinations thereof. Form using one of

The plate electrode 29 is formed on the surface of the dielectric film 27. At this time, the plate electrode 33 is formed by a sputtering method, a CVD method or an atomic layer deposition method of any one selected from TiN, Ru or silicon film to a thickness of 500 ~ 3000 Å.

As described above, in the method of forming a capacitor of a semiconductor device according to the present invention, a storage electrode having a predetermined size is formed by preventing the damage of the oxide film for the storage electrode and the damage of the silicon film for the storage electrode by an etching process using an etching selectivity difference. The effect of forming a capacitor having a capacitance sufficient for high integration of a semiconductor device is provided.

Claims (12)

Forming a lower insulating layer provided with a contact plug on the semiconductor substrate; Forming an oxide film for a storage electrode on the lower insulating layer; Defining a storage electrode region of a trench structure in which the contact plug is exposed by etching the oxide film for the storage electrode by a photolithography process using a storage electrode mask; Forming a silicon film for a storage electrode on the entire surface including the storage electrode region; Forming a sacrificial insulating film filling the storage electrode region on the entire surface; Performing a planarization etching of the sacrificial insulating film to expose the storage electrode silicon film on the storage electrode oxide film, without excessive etching; Removing the storage electrode silicon film on the storage electrode oxide film by a wet method using an etching selectivity difference between the storage electrode oxide film and the sacrificial insulating film; Removing the sacrificial insulating film in the storage electrode region to form a storage electrode with a silicon film for storage electrode provided on the surface of the storage electrode region; A method for forming a capacitor of a semiconductor device comprising the step of forming a dielectric film and a plate electrode in a subsequent step. The method of claim 1, And the oxide film for the storage electrode is formed of a silicon oxide film or a TEOS oxide film formed by a CVD method. The method of claim 1, And the stacked structure of the oxide film for the storage electrode is formed to have a thickness of 6000 to 20000 GPa. The method of claim 1, Wherein the storage electrode silicon film is formed of a stacked structure of a doped silicon film and an undoped silicon film or a single layer structure of an undoped silicon film, and has a hemispherical polysilicon formed on a surface thereof. The method of claim 4, wherein And the laminated structure and the single layer structure are formed to have a thickness of 100 to 1000 GPa. The method of claim 4, wherein The hemispherical polysilicon is formed by surface treatment of the laminated structure or single layer structure using a silicon-based gas such as SiH 4, Si 2 H 6 gas as a seeding gas for 1 to 1000 seconds under an argon and nitrogen gas atmosphere at 500 to 800 ° C. A method of forming a capacitor of a semiconductor device, characterized in that. The method of claim 1, And a CVD oxide film or a photosensitive film as said sacrificial insulating film. The method of claim 7, wherein The CVD oxide film is a capacitor forming method of a semiconductor device, characterized in that formed by any one selected from the group consisting of PSG, BSG, BPSG, AsSG, Al2O3 and a combination of 1000 to 10000 Å thickness. The method of claim 7, wherein The method of forming a capacitor of a semiconductor device, characterized in that the photosensitive film is formed by a thickness of 1000 ~ 20000 Å. The method of claim 1, The wet etching process may be performed by using an etching selectivity difference between the storage electrode oxide layer, the sacrificial insulating layer, and the storage electrode silicon layer, using a mixed solution having a volume ratio of HF: HNO 3 = 1: 1 to 1000. A method for forming a capacitor of a semiconductor device, characterized in that carried out for 2 to 3600 seconds at a temperature of 80 ℃. The method of claim 1, The dielectric film is formed using any one selected from the group consisting of ONO, NO, BST ((Ba, Sr) TiO 3), PST ((Pb, Sr) TiO 3), Ta 2 O 5, TaON, TiO 2, Al 2 O 3, and a combination thereof. A method of forming a capacitor of a semiconductor device, characterized in that. The method of claim 1, The plate electrode is a capacitor forming method of a semiconductor device, characterized in that any one selected from TiN, Ru or polysilicon to a thickness of 500 ~ 3000 Å by using a sputtering method, a CVD method or an atomic layer deposition method.