KR20030048894A - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- KR20030048894A KR20030048894A KR1020010078941A KR20010078941A KR20030048894A KR 20030048894 A KR20030048894 A KR 20030048894A KR 1020010078941 A KR1020010078941 A KR 1020010078941A KR 20010078941 A KR20010078941 A KR 20010078941A KR 20030048894 A KR20030048894 A KR 20030048894A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 125000006850 spacer group Chemical group 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 12
- 239000011229 interlayer Substances 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 7
- 230000007423 decrease Effects 0.000 description 6
- 238000002955 isolation Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는, 지아이디엘(GIDL : Gate Induced Drain Leakage) 커런트를 개선시킬 수 있는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of improving a gate induced drain leakage (GIDL) current.
반도체 소자의 집적도가 증가됨에 따라, 회로 내에 구비되는 패턴들의 크기가 감소되고 있고, 이러한 경향에 부합해서 우수한 소자 특성을 얻기 위한 다양한 공정 기술들이 적용 및 개발되고 있다.As the degree of integration of semiconductor devices is increased, the size of patterns included in a circuit is reduced, and various process technologies are being applied and developed to obtain excellent device characteristics in accordance with this trend.
그런데, 반도체 소자의 고집적화에 따라 게이트 전극의 선폭 감소가 진행되고 있는 추세에서, 상기 게이트 전극의 선폭 감소는 채널 길이의 감소를 초래하게 되어 문턱 전압(Vt)이 급격하게 줄어드는 단채널효과(Short Channel Effect)를 유발하게 되고, 이로 인해, 트랜지스터 및 소자 특성의 저하가 야기된다. 따라서, 반도체 소자의 고집적화를 위해서는 상기 단채널효과의 방지가 반듯이 해결되어야 할 과제이다. 이러한 단채널효과의 유발을 방지하기 위해 다양한 공정 기술들이 개발되고 있으며, LDD(Lightly Doped Drain) 영역의 형성은 그 좋은 예이다.However, as the line width of the gate electrode decreases as the semiconductor device is highly integrated, the decrease of the line width of the gate electrode causes a decrease in the channel length, thereby shortening the threshold voltage Vt. Effect), which causes deterioration of transistor and device characteristics. Therefore, the prevention of the short channel effect must be solved for high integration of semiconductor devices. Various process technologies are being developed to prevent the occurrence of such a short channel effect, and the formation of a lightly doped drain (LDD) region is a good example.
도 1은 종래 기술에 따라 형성된 반도체 소자를 도시한 단면도로서, 이를 참조하여 그 제조방법을 설명하면 다음과 같다.1 is a cross-sectional view showing a semiconductor device formed according to the prior art, the method of manufacturing the same with reference to this as follows.
먼저, 반도체 기판(1)의 적소에 트렌치형의 소자분리막(2)을 형성한다. 그런다음, 이온주입 공정을 통해 기판(1) 내에 웰(3)을 형성하고, 이어, 게이트의 문턱전압 조절을 위한 이온주입을 행한다.First, a trench type device isolation film 2 is formed in place of the semiconductor substrate 1. Then, the well 3 is formed in the substrate 1 through an ion implantation process, and then ion implantation is performed to adjust the threshold voltage of the gate.
다음으로, 소자분리막(2)이 구비된 반도체 기판(1) 상에 산화막(4a)과 폴리실리콘막(4b)을 차례로 형성하고, 이어, 상기 막들을 패터닝하여 게이트 전극(4)을 형성한다. 그런다음, 상기 결과물에 대해 LDD(Lightly Doped Drain) 이온주입을 행하여 기판 표면에 LDD 영역(5)을 형성한다.Next, an oxide film 4a and a polysilicon film 4b are sequentially formed on the semiconductor substrate 1 provided with the device isolation film 2, and then the films are patterned to form a gate electrode 4. Then, LDD (Lightly Doped Drain) ion implantation is performed on the resultant to form the LDD region 5 on the substrate surface.
그 다음, 상기 결과물 상에 산화막 및 질화막의 증착한 후, 이들을 블랭킷 식각하여 게이트 전극(4)의 측벽에 게이트 스페이서(6)를 형성하고, 이어, 고농도 불순물 이온주입을 행하여 노출된 기판 표면에 소오스/드레인 영역(7)을 형성한다.Then, after depositing an oxide film and a nitride film on the resultant, they are blanket-etched to form a gate spacer 6 on the sidewall of the gate electrode 4, followed by high concentration impurity ion implantation to expose the source to the exposed substrate surface. The drain region 7 is formed.
다음으로, 상기 단계까지의 결과물 상에 평탄화된 층간절연막(8)을 형성하고, 그런다음, 상기 층간절연막(8)의 소정 부분들을 선택적으로 식각하여 기판(1)의 일부분을 노출시키는 콘택홀들을 형성한 후, 각 콘택홀 내에 도전막을 매립시켜 콘택플러그(9)를 형성한다. 그리고나서, 상기 층간절연막(8) 상에 금속막을 증착한 후, 이를 패터닝하여 각각의 콘택플러그(8)와 콘택되는 금속배선(10)을 형성한다.Next, contact holes for forming a planarized interlayer insulating film 8 on the resultant up to the step, and then selectively etching certain portions of the interlayer insulating film 8 to expose a portion of the substrate 1 After formation, a contact plug 9 is formed by filling a conductive film in each contact hole. Then, a metal film is deposited on the interlayer insulating film 8 and then patterned to form a metal wiring 10 in contact with each contact plug 8.
이후, 도시하지는 않았으나, 공지의 후속 공정을 진행하여 소망하는 반도체 소자를 완성한다.Thereafter, although not shown in the figure, a subsequent known process is carried out to complete the desired semiconductor device.
그러나, 종래 기술에 따른 반도체 소자는 LDD 영역의 형성을 통해 단채널효과를 어느 정도 개선할 수 있지만, 게이트 전극과 드레인 영역간의 오버랩 영역에서 발생되는 GIDL(Gate Induced Drain Leakage) 커런트를 개선하는데 한계가 있는 바, 그 특성 확보가 어려운 문제점이 있다. 특히, 채널 길이가 감소될수록 상기 GIDL 커런트 문제가 심화될 것으로 예상된다.However, although the semiconductor device according to the related art can improve the short channel effect to some extent through the formation of the LDD region, there is a limit in improving the gate induced drain leakage (GIDL) generated in the overlap region between the gate electrode and the drain region. There is a problem that is difficult to secure the characteristics. In particular, as the channel length is reduced, the GIDL current problem is expected to deepen.
또한, 고집적화에 따라 셀 면적이 감소되고 있는 추세에서, 게이트 스페이서의 형성으로 인해 콘택 면적이 감소됨으로써, 콘택 공정 마진의 확보가 어려운 문제점이 있다.In addition, as the cell area decreases due to high integration, the contact area decreases due to the formation of the gate spacer, thereby making it difficult to secure a contact process margin.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 게이트 형성 공정의 변경을 통해 GIDL 거런트를 개선시킬 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of improving the GIDL current through changing the gate forming process, which is devised to solve the above problems.
또한, 본 발명은 게이트 스페이서에 의한 콘택 면적의 감소를 방지할 수 있는 반도체 소자의 제조방법을 제공함에 그 다른 목적이 있다.Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing a reduction in contact area caused by a gate spacer.
도 1은 종래 기술에 따라 형성된 형성된 반도체 소자를 도시한 단면도.1 is a cross-sectional view showing a formed semiconductor device formed according to the prior art.
도 2a 내지 도 2f는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도.2A through 2F are cross-sectional views of processes for describing a method of manufacturing a semiconductor device, according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
11 : 반도체 기판 12 : 소자분리막11 semiconductor substrate 12 device isolation film
13 : 웰 14 : 희생막 패턴13: well 14: sacrificial film pattern
15 : 희생 스페이서 16 : LDD 영역15 sacrificial spacer 16 LDD region
17 : 감광막 패턴 18 : 트렌치17 photosensitive film pattern 18: trench
19 : 게이트 스페이서 20 : 산화막19 gate spacer 20 oxide film
21 : 게이트용 도전막 22 : 게이트 전극21: conductive film for gate 22: gate electrode
23 : 소오스/드레인 영역 24 : 층간절연막23 source / drain region 24 interlayer insulating film
25 : 콘택플러그 26 : 금속배선25: contact plug 26: metal wiring
상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 제조방법은, 반도체 기판 상에 양측벽에 희생 스페이서를 갖는 희생막 패턴을 형성하는 단계; 상기 희생막 패턴 양측의 기판 표면 내에 LDD 영역을 형성하는 단계; 상기 희생막 패턴과 그 하부의 기판 영역을 식각하여 트렌치를 형성하는 단계; 상기 트렌치의 내벽 및 상기 희생 스페이서의 측벽 상에 산화막 재질의 게이트 스페이서를 형성하는 단계; 상기 트렌치의 저부를 포함한 기판 표면 상에 산화막을 형성하는 단계; 상기 트렌치 내부에 도전막을 매립시켜 트렌치형의 게이트 전극을 형성하는 단계; 상기 희생 스페이서와 그 측벽의 게이트 스페이서 부분을 제거하는 단계; 및 상기 트렌치형의 게이트 전극 양측의 기판 표면 내에 LDD 영역을 갖는 소오스/드레인 영역을 형성하는 단계를 포함한다.A method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of: forming a sacrificial film pattern having sacrificial spacers on both side walls on a semiconductor substrate; Forming LDD regions in the substrate surfaces on both sides of the sacrificial layer pattern; Forming a trench by etching the sacrificial layer pattern and a substrate region below the sacrificial layer pattern; Forming a gate spacer of an oxide film on an inner wall of the trench and a sidewall of the sacrificial spacer; Forming an oxide film on a surface of the substrate including the bottom of the trench; Embedding a conductive film in the trench to form a trench type gate electrode; Removing the sacrificial spacers and gate spacer portions of the sidewalls thereof; And forming a source / drain region having an LDD region in the substrate surface on both sides of the trench-type gate electrode.
본 발명에 따르면, 게이트 전극을 트렌치형으로 형성함으로써, 상기 게이트 전극과 드레인 영역의 오버랩 면적을 제거할 수 있으며, 이에 따라, GIDL 커런트를 개선할 수 있으며, 아울러, 트렌치 내에 게이트 스페이서를 형성함에 따라 콘택 공정의 마진을 확보할 수 있다.According to the present invention, by forming the gate electrode in a trench shape, the overlap area between the gate electrode and the drain region can be removed, thereby improving the GIDL current and forming a gate spacer in the trench. The margin of the contact process can be secured.
(실시예)(Example)
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2f는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도이다.2A through 2F are cross-sectional views of processes for describing a method of manufacturing a semiconductor device, according to an embodiment of the present invention.
도 2a를 참조하면, 반도체 기판(11)의 적소에 공지의 STI(Shallow Trench Isolation) 공정에 따라 액티브 영역을 한정하는 트렌치형의 소자분리막들을 형성하고, n형 및 p형 불순물의 이온주입을 차례로 행하여 기판(11) 내에 n형 및 p형의 웰(13)을 형성하고, 연이어, 후속에서 형성될 게이트 전극의 문턱전압(Vt)을 조절하기 위한 이온주입을 행한다.Referring to FIG. 2A, trench-type device isolation films that define an active region are formed in a proper position of the semiconductor substrate 11 by a known shallow trench isolation (STI) process, and ion implantation of n-type and p-type impurities is sequentially performed. Then, n-type and p-type wells 13 are formed in the substrate 11, followed by ion implantation for adjusting the threshold voltage Vt of the gate electrode to be formed subsequently.
도 2b를 참조하면, 반도체 기판(11)의 전 영역 상에 희생막을 증착한 상태에서, 이를 패터닝하여 후속에서 게이트가 형성될 기판 영역 상에 희생막 패턴(14)을 형성한다. 여기서, 상기 희생막은 폴리실리콘막으로 형성함이 바람직하다. 이어서, 질화막이 증착 및 이에 대한 블랭킷 식각을 수행하여 상기 희생막 패턴(14)의 측벽에 희생 스페이서(15)를 형성하고, 이어, 상기 희생 스페이서(15)를 포함 희생막 패턴(14)을 이온주입 마스크로하는 저농도 불순물 이온주입을 수행하여 상기 희생 스페이서(15)를 포함하는 희생막 패턴(14) 양측의 기판 영역 내에 LDD 영역(16)을 형성한다.Referring to FIG. 2B, in the state in which the sacrificial film is deposited on the entire region of the semiconductor substrate 11, the sacrificial layer pattern 14 is formed on the substrate region where the gate is to be subsequently formed. Here, the sacrificial film is preferably formed of a polysilicon film. Subsequently, a nitride film is deposited and a blanket etch is performed to form a sacrificial spacer 15 on the sidewall of the sacrificial layer pattern 14, and then ionize the sacrificial layer pattern 14 including the sacrificial spacer 15. The LDD region 16 is formed in the substrate regions on both sides of the sacrificial layer pattern 14 including the sacrificial spacer 15 by performing low concentration impurity ion implantation using the implantation mask.
도 2c를 참조하면, 상기 단계까지의 결과물 상에 희생막 패턴을 노출시키는 감광막 패턴(17)을 형성한다. 그런다음, 상기 노출된 희생막 패턴을 제거한 상태에서, 상기 희생막 패턴의 제거로 인해 노출된 기판 영역을 소정 두께만큼 식각하여, 트렌치(18)를 형성한다.Referring to FIG. 2C, the photoresist layer pattern 17 exposing the sacrificial layer pattern is formed on the resultant layer. Then, in the state in which the exposed sacrificial layer pattern is removed, the trench 18 is formed by etching the exposed substrate region due to the removal of the sacrificial layer pattern by a predetermined thickness.
도 2d를 참조하면, 식각마스크로 이용된 감광막 패턴을 제거한 상태에서, 산화막의 증착 및 이에 대한 블랭킷 식각을 수행하여 상기 트렌치(18) 및 희생 스페이서(15)의 측벽에 게이트 스페이서(19)를 형성한다. 그런다음, 이 결과물에 대해 산화 공정을 수행하여 트렌치의 저부를 포함한 기판(11) 표면 상에 산화막(20)을 형성하고, 그리고나서, 상기 트렌치(18) 내에 게이트용 도전막, 예컨데, 폴리실리콘막(21)을 매립시킨다.Referring to FIG. 2D, the gate spacer 19 is formed on the sidewalls of the trench 18 and the sacrificial spacer 15 by depositing an oxide film and performing a blanket etching on the oxide film while removing the photoresist pattern used as an etching mask. do. Then, an oxidation process is performed on the resultant to form an oxide film 20 on the surface of the substrate 11 including the bottom of the trench, and then a gate conductive film, such as polysilicon, in the trench 18. The film 21 is embedded.
도 2e를 참조하면, 희생 스페이서 및 이 측면에 형성된 게이트 스페이서 부분을 식각 제거하고, 이 결과로서, 기판(11) 내에 트렌치형의 게이트 전극(22)을 형성한다. 그런다음, 상기 단계까지의 결과물에 대해 고농도의 불순물 이온주입을 행하여 게이트 스페이서(19)를 포함한 게이트 전극(22) 양측의 기판(11) 영역 내에 소오스/드레인 영역(23)을 형성한다.Referring to FIG. 2E, the sacrificial spacer and the gate spacer portion formed on the side surface are etched away, and as a result, a trench type gate electrode 22 is formed in the substrate 11. Then, a high concentration of impurity ions are implanted into the resultant up to this step to form source / drain regions 23 in the region of the substrate 11 on both sides of the gate electrode 22 including the gate spacer 19.
도 2f를 참조하면, 상기 결과물의 전 영역 상에 표면 평탄화가 이루어진 층간절연막(24)을 형성한 상태에서, 상기 층간절연막(24)의 소정 부분들을 선택적으로 식각하여 기판 영역, 즉, 소오스/드레인 영역(23)을 각각 노출시키는 콘택홀들을 형성한 후, 각 콘택홀 내에 도전막을 매립시켜 콘택플러그들(25)을 형성하고, 그리고나서, 층간절연막(24) 상에 금속막의 증착 및 이에 대한 패터닝을 차례로 수행하여 각각의 콘택플러그(25)와 개별적으로 콘택되는 금속배선(26)을 형성한다.Referring to FIG. 2F, in a state in which an interlayer insulating film 24 having surface planarization is formed on the entire region of the resultant, predetermined portions of the interlayer insulating film 24 are selectively etched to form a substrate region, that is, a source / drain. After forming the contact holes exposing the regions 23 respectively, embedding a conductive film in each contact hole to form the contact plugs 25, and then depositing and patterning the metal film on the interlayer insulating film 24. Are performed sequentially to form metal wirings 26 that are individually contacted with the respective contact plugs 25.
이후, 도시하지는 않았으나, 공지의 후속 공정을 수행하여 본 발명의 반도체소자를 완성한다.Thereafter, although not shown, the semiconductor device of the present invention is completed by performing a well-known subsequent process.
상기와 같은 공정에 따라 반도체 소자를 제조하게 되면, 우선, 게이트 전극이 트렌치형으로 형성되기 때문에 상기 게이트 전극과 드레인 영역간의 오버랩 영역이 제거되며, 따라서, 상기 오버랩 영역에 기인하는 GIDL 커런트가 개선되어 소자 특성이 확보된다. 또한, 게이트 스페이서가 트렌치의 내벽에 형성되므로, 상기 게이트 스페이서에 의한 콘택 면적의 감소는 유발되지 않으며, 따라서, 콘택 면적의 감소에 따른 콘택 저항의 증가 등은 초래되지 않는 바, 결국, 콘택 공정 마진을 확보할 수 있게 된다.When the semiconductor device is manufactured according to the above-described process, first, since the gate electrode is formed in the trench type, the overlap region between the gate electrode and the drain region is removed, so that the GIDL current due to the overlap region is improved. Device characteristics are secured. In addition, since the gate spacer is formed on the inner wall of the trench, the reduction of the contact area caused by the gate spacer does not occur, and thus, the increase of the contact resistance due to the decrease of the contact area does not occur. Can be secured.
이상에서와 같이, 본 발명은 게이트 전극과 드레인 영역의 오버랩 영역이 감소 또는 제거되도록 상기 게이트 전극을 트렌치형으로 형성함으로써, GIDL 커런트를 개선시킬 수 있으며, 아울러, 게이트 스페이서를 트렌치 내벽에 형성함으로써, 후속하는 콘택 공정의 공정 마진을 확보할 수 있다.As described above, the present invention can improve the GIDL current by forming the gate electrode in the trench so that the overlap region of the gate electrode and the drain region is reduced or eliminated, and by forming the gate spacer on the inner wall of the trench, Process margins for subsequent contact processes can be ensured.
따라서, 본 발명은 반도체 소자의 고집적화를 이룰 수 있으며, 아울러, 특성 저하가 없는 소자를 제조할 수 있다.Therefore, the present invention can achieve high integration of semiconductor devices, and can manufacture devices without deterioration of properties.
기타, 본 발명은 그 요지가 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.
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| KR100539244B1 (en) * | 2003-10-10 | 2005-12-27 | 삼성전자주식회사 | Method for forming recess channel trench pattern, method for fabricating recess channel transistor and recess channel transistor fabricated by the same |
| US7361537B2 (en) | 2003-10-22 | 2008-04-22 | Samsung Electronics Co., Ltd. | Method of fabricating recess channel array transistor |
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| JPH05343676A (en) * | 1992-06-05 | 1993-12-24 | Nec Corp | Field-effect transistor and manufacturing method thereof |
| JPH07106560A (en) * | 1993-09-29 | 1995-04-21 | Ricoh Co Ltd | Groove type semiconductor device and manufacture of the same |
| KR19990056737A (en) * | 1997-12-29 | 1999-07-15 | 김영환 | Semiconductor device and manufacturing method |
| KR20000003980A (en) * | 1998-06-30 | 2000-01-25 | 김영환 | Transistor of semiconductor devices and method thereof |
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| KR100539244B1 (en) * | 2003-10-10 | 2005-12-27 | 삼성전자주식회사 | Method for forming recess channel trench pattern, method for fabricating recess channel transistor and recess channel transistor fabricated by the same |
| US7361537B2 (en) | 2003-10-22 | 2008-04-22 | Samsung Electronics Co., Ltd. | Method of fabricating recess channel array transistor |
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