KR20030047517A - Mos transistor having elevated source/drain region and method for fabricating the same - Google Patents

Abstract

PURPOSE: A MOS transistor having an elevated source/drain region and a fabricating method thereof are provided to form easily the elevated source/drain region by etching selectively a gate forming region. CONSTITUTION: A semiconductor substrate(200) has a main surface. A recessed region is formed on a predetermined region of the semiconductor substrate. A surface of the recessed region is lower than the main surface of the semiconductor substrate. A gate insulating layer(220) and a gate electrode(225a) are stacked on the recessed region. An elevated source and drain(230,240) are formed on the semiconductor substrate of both sides of the gate electrode. The elevated source and drain are formed on the main surface of the semiconductor substrate adjacent to the recessed region. A gate spacer(235a) is formed on a sidewall of the gate electrode. A lightly doped source and a lightly doped drain are formed on a lower end of the gate spacer.

Description

A MOS transistor having an elevated source and drain region and a method of manufacturing the same MOS TRANSISTOR HAVING ELEVATED SOURCE / DRAIN REGION AND METHOD FOR FABRICATING THE SAME

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a MOS transistor having an elevated source and drain (elevated source / drain) structure and a method of manufacturing the same.

As the degree of integration of semiconductor devices increases, the scale-down of MOSFETs, which is one of the important elements constituting the device, is also accelerated. This reduction in size causes short channel effects, such as drain induced barrier lowering (DIBL) or punch through, which interferes with the normal operation of the device.

In general, to improve the short channel effect, a shallow junction that forms a thin source and drain region is used.

However, as the source and drain junctions become shallower, not only problems such as increase of parasitic resistance and deterioration of device performance occur, but also depth of junction decreases, so that subsequent contact holes are difficult to form, and a salicide layer is formed in the source and drain regions. The problem arises that the formation of the.

In order to improve this, a MOS field effect transistor having an elevated source and an elevated source drain has been manufactured. The method of forming the elevated source and drain structures is mainly done by using the selective epitaxial growth method to grow epitaxial layers in the source and drain regions without using ultra-low energy implantation. It can effectively form a shallow junction.

1 is a cross-sectional view illustrating a field effect transistor having an elevated source and drain structure by conventional selective epitaxial growth.

Referring to FIG. 1, a gate insulating film 110, a gate electrode 115, and a gate spacer 120 are formed on a semiconductor substrate 100 on which an isolation layer 105 is formed by a shallow trench isolation (STI) device isolation process. The pattern is formed, and the silicon epitaxial layer 125 formed by selective epitaxial growth is formed on the semiconductor substrate 100 on both sides of the gate pattern. Impurity ions are implanted into the silicon epitaxial layer 125 to form a source and a drain, and a heat treatment is performed to form a source and drain region 130 having a shallow junction. Next, a metal salicide process is performed on the silicon epitaxial layer 125.

The elevated source and drain regions described above have the advantage of improving the short channel effect by solving the problems of increased parasitic resistance and poor bonding when forming a junction by implementing a shallow source and drain junction structure.

On the other hand, in the process of selectively forming the silicon epitaxial layer 125, an island-type silicon film is formed at a position other than the silicon epitaxial layer 125 due to a selectivity loss, so that the gate electrode and the gate electrode may be formed in a subsequent salicide process. There is a high possibility that an electrical short may occur between the source and the drain, and the manufacturing cost increases as the manufacturing process is complicated.

In addition, when the silicon epitaxial layer 125 is formed, the electrical characteristics of the semiconductor device may be degraded in the ion implantation and heat treatment processes for subsequent source and drain region formation due to the naturally occurring epitaxial edge facet. to occur.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a MOS transistor having an elevated source and drain region in which the manufacturing process is simple and the electrical characteristics are not degraded.

1 is a cross-sectional view showing a MOS field effect transistor of an elevated source and drain structure by conventional selective epitaxial growth;

2A to 2H are cross-sectional views illustrating a method of manufacturing a MOS transistor according to a first embodiment of the present invention;

3A to 3G are cross-sectional views illustrating a method of manufacturing a MOS transistor according to a second embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

200,300: semiconductor substrate 220,320: gate insulating film

225,325 gate electrode conductive film235,335 spacer insulating film

240,340 Source and Drain

A MOS transistor having an elevated source and drain region of the present invention for achieving the above object forms a recessed region by etching a semiconductor substrate in a region where a gate electrode is to be formed. The gate electrode is formed on the recessed region so that the lower portion of the gate electrode is lower than the lower portion of the source and drain regions.

That is, in the related art, when the silicon epitaxial layer is grown in the source and drain regions to form a shallow junction by ion implantation through the silicon epilayer, the present invention provides a shallow junction by forming the gate electrode lower than the source and drain regions. will be.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2H and 3G show the structure of a MOS transistor completed by an embodiment of the present invention.

2H and 3G, the MOS transistor of the present invention includes a semiconductor substrate 200 and 300 having a major surface and a recessed region having a lower surface than the main surface, and a gate insulating layer 220 and 320 stacked on the recessed region. ) And gate electrodes 225a and 325a, and raised sources and drains 240 and 340 formed on semiconductor substrates on either side of the gate electrode, wherein the source and drain are surfaces of the semiconductor substrate adjacent to the recessed region. Is formed.

Preferably, the MOS transistor of the present invention may include gate spacers 235a and 335a formed on sidewalls of the gate electrodes 225a and 325a and low doping sources and drains 230 and 330 formed under the gate spacers.

Hereinafter, the manufacturing method for forming the MOS transistor structure of this invention is demonstrated.

Example 1

In the first embodiment, an ion implantation process is performed in a region where a gate electrode is to be formed (hereinafter referred to as a 'gate electrode formation region'), and is oxidized to form an oxide film. The ion-implanted region is oxidized faster than the non-ion implanted region by damage, and after etching the oxide film and forming the gate electrode, the gate electrode has a lower structure than the source and drain.

2A to 2H are cross-sectional views illustrating a method of manufacturing a MOS transistor having an elevated source and drain region according to a first embodiment of the present invention.

Referring to FIG. 2A, an isolation layer 205 is formed in a predetermined region of the semiconductor substrate 200 to define an active region. Next, a photoresist pattern 210a for ion implantation is formed in the gate electrode formation region to open the gate electrode formation region, which is larger than the region where the actual gate electrode is to be formed. Subsequently, ion implantation is performed using the photoresist pattern 210a as an ion implantation mask. The dopant used for ion implantation uses at least one selected from N, In, As, P, Ar, B, BF ₂ and O ₂ .

Referring to FIG. 2B, the semiconductor substrate is thermally oxidized after the photoresist pattern 210a is removed. In the ion implanted gate electrode formation region, oxidation proceeds more rapidly due to damage of the substrate due to ion implantation, and thus, compared to other regions. A thicker oxide film is formed.

Referring to FIG. 2C, a wet etch is performed on the entire surface of the substrate to remove the thermal oxide layer 215. When wet etching is performed to remove all of the thermal oxide layer 215, the gate electrode forming region is formed with a recessed region A having a lower surface than the main surface B because a thicker oxide layer is formed.

Referring to FIG. 2D, a gate insulating film 220 and a gate electrode conductive film 225 are sequentially stacked on a substrate including the recessed region A. FIG. The gate insulating layer 220 may use at least one selected from the group consisting of a thermal oxide film, a silicon nitride film, a titanium oxide film, a silicon oxynitride film, and a tantalum pentaoxide film. The gate electrode conductive layer 225 uses at least one selected from the group consisting of polyside, cobalt (Co), tungsten (W), titanium (Ti), and nickel (Ni).

Referring to FIG. 2E, the gate electrode conductive layer 225 is selectively etched to form a gate electrode 225a on the recessed region A. Referring to FIG. When etching the gate electrode conductive layer 225, all of the lower gate insulating layer 220 may be etched or partially left. In the figures all are shown as being etched.

Next, an impurity is implanted into the entire surface of the semiconductor substrate by using the gate electrode 225a as an ion implantation mask, and then lightly doped drain (LDD) is applied to the substrates on both sides of the gate electrode 225a. The low concentration source and the low concentration drain 230 may be formed to form.

Referring to FIG. 2F, a spacer insulating layer 235 may be formed on the entire surface of the substrate. The spacer insulating layer 235 may be formed of a silicon nitride layer or a silicon oxide layer.

Referring to FIG. 2G, a gate spacer 235a may be formed on the side of the gate electrode 225a by etching back the spacer insulating layer 235.

Referring to FIG. 2H, impurities are implanted into the entire surface of the substrate using the gate electrode 225a and the gate spacer 235a as ion implantation masks, and a heat treatment process is performed to perform substrates on both sides of the gate electrode 225a. A high concentration source and drain region 240 is formed in this. The source and drain regions 230 and 240 are formed on the semiconductor substrate adjacent to the recessed region A. FIG. Accordingly, the completed MOS transistor has a structure in which the lower portion of the gate electrode 225a is lower than the surfaces of the source and drain regions 230 and 240.

Example 2

In the second embodiment, the substrate of the gate electrode formation region is etched before the gate electrode is formed, and then the gate electrode is patterned to form the elevated source and drain regions.

3A to 3G are cross-sectional views illustrating an elevated source and drain structure according to a second embodiment of the present invention.

Referring to FIG. 3A, an isolation layer 305 defining an active region is formed in a predetermined region of the semiconductor substrate 300. Next, the photosensitive film pattern 310a which opens the gate electrode forming region is formed.

Referring to FIG. 3B, the semiconductor substrate is selectively etched using the photoresist pattern 310a as an etch barrier. Then, a recessed region A in which the gate electrode forming region has a surface lower than the main surface B is formed. In this case, the etching may be performed by dry etching or wet etching. The depth at which the recessed region A is etched is then adjusted to form a shallow junction, depending on the type of dopant in the source and drain regions.

The subsequent steps are the same as those in the first embodiment and will be described briefly.

Referring to FIG. 3C, a gate insulating layer 320 and a gate electrode conductive layer 325 are formed on the semiconductor substrate 300 including the recessed region A. Referring to FIG.

Referring to FIG. 3D, the gate electrode conductive layer 325 is selectively etched to form the gate electrode 325a. Next, an impurity is implanted into the entire surface of the semiconductor substrate by using the gate electrode 325a as an ion implantation mask to lightly doped drain (LDD) to the substrates on both sides of the gate electrode 325a. Low concentration source and low concentration drain 330 are formed to form.

Referring to FIG. 3E, a spacer insulating layer 335 may be formed on the entire surface of the substrate including the gate electrode 325a.

Referring to FIG. 3F, a gate spacer 335a may be formed on the side of the gate electrode 325a by etching back the spacer insulating layer 335.

Referring to FIG. 3G, the gate electrode 325a and the gate spacer 335a are used as ion implantation masks to ion implant and perform a heat treatment process to form a high concentration source and drain region 340. The source and drain regions 330 and 340 are formed on the semiconductor substrate adjacent to the recessed region A. FIG. Accordingly, the completed MOS transistor has a structure in which the lower portion of the gate electrode 325a is lower than the surfaces of the source and drain regions 330 and 340.

The difference between the first embodiment and the second embodiment differs in the method of forming the gate electrode forming region lower than that of the semiconductor substrate, and subsequent processes such as forming the gate electrode, forming the gate spacer, and forming the source and drain regions are the same. Do.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

The present invention made as described above, the process is simpler than the conventional process by selectively etching the gate formation region instead of the conventional method of forming the elevated source and drain region by the selective epitaxial growth, there is a fear of short circuit due to selectivity loss. Elevated source and drain regions can be formed.

In addition, the conventional selective epitaxial growth has a problem that the defect of the device due to the facet of the epilayer edge occurs, the present invention is because the ion implantation of the source and drain region is made on a flat semiconductor substrate, the performance of the device by the facet is deteriorated There is no problem to be effective.

Claims (7)

A semiconductor substrate having a major surface; A recessed region formed in a predetermined region of the semiconductor substrate and having a lower surface than the main surface; A gate insulating film and a gate electrode sequentially stacked on the recessed region; And And a raised source and a drain formed on the semiconductor substrates on both sides of the gate electrode, wherein the source and the drain are formed on a surface of the semiconductor substrate adjacent to the recessed region. The method of claim 1, The MOS transistor further comprises a gate spacer formed on the sidewall of the gate electrode and a low-doped source and drain formed on the bottom of the gate spacer. Forming a recessed region having a surface lower than a main surface of the semiconductor substrate in a predetermined region of the semiconductor substrate; Forming a gate insulating film and a gate electrode sequentially stacked on the recessed region; And And forming a source and a drain in the semiconductor substrates on both sides of the gate electrode, wherein the source and the drain are formed on a surface of the semiconductor substrate adjacent to the recessed region. The method of claim 3, wherein Forming the recessed region Forming a photoresist pattern on the semiconductor substrate; Ion implantation using the photoresist pattern as an ion implantation mask; Removing the photoresist pattern; Thermally oxidizing the semiconductor substrate to form a thermal oxide film thicker than the thermal oxide film grown around the ion implanted region, the thermal oxide film grown in the ion implanted region; And Removing the thermal oxide film Morse transistor manufacturing method comprising a. The method of claim 4, wherein The dopant used in the ion implantation method of MOS transistor, characterized in that using at least one selected from N, In, As, P, Ar, B, BF ₂ , O ₂ . The method of claim 3, wherein Forming the recessed region Forming a photoresist pattern on the semiconductor substrate; And And selectively etching the photoresist pattern as an etch barrier. The method of claim 3, wherein Forming the source and drain Implanting impurities into the entire surface of the substrate using the gate electrode as an ion implantation mask to form a low concentration source and a drain on the substrates on both sides of the gate electrode; Forming a gate spacer on sidewalls of the gate electrode; Implanting impurities into the entire surface of the substrate using the gate electrode and the gate spacer as ion implantation masks to form a high concentration source and a high concentration drain on both sides of the gate electrode; .