KR20030046934A - Stack package - Google Patents
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- KR20030046934A KR20030046934A KR1020010077272A KR20010077272A KR20030046934A KR 20030046934 A KR20030046934 A KR 20030046934A KR 1020010077272 A KR1020010077272 A KR 1020010077272A KR 20010077272 A KR20010077272 A KR 20010077272A KR 20030046934 A KR20030046934 A KR 20030046934A
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- package
- circuit
- fbga
- stack
- circuit board
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1064—Electrical connections provided on a side surface of one or more of the containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Abstract
Description
본 발명은 반도체 패키지에 관한 것으로서, 보다 구체적으로는 두 개 이상의 반도체 패키지를 적층하여 구성하는 스택 패키지에 관한 것이다.The present invention relates to a semiconductor package, and more particularly, to a stack package configured by stacking two or more semiconductor packages.
반도체 산업에서 집적회로 칩에 대한 패키징 기술은 소형화에 대한 요구 및 실장 신뢰성을 만족시키기 위해 지속적으로 발전하고 있다. 아울러, 전자 제품의 고성능화가 진행됨에 따라, 한정된 크기의 기판에 더 많은 수의 반도체 패키지를 실장하기 위한 노력들이 계속되고 있다. 이러한 노력의 일환으로 제안된 것이 소위 적층 패키지(Stack Package)이다. 적층 패키지는 하나의 패키지에 두 개 이상의 집적회로 칩을 내장하는 멀티 칩 패키지(Multi Chip Package)와 달리, 하나의 집적회로 칩을 내장하는 싱글 칩 패키지(Single Chip Package)를 두 개 이상 적층하는 방식이다.Packaging technology for integrated circuit chips in the semiconductor industry continues to evolve to meet the demand for miniaturization and mounting reliability. In addition, as the performance of electronic products increases, efforts are being made to mount a larger number of semiconductor packages on a limited size substrate. As part of this effort, what has been proposed is a stack package. Unlike a multi chip package in which two or more integrated circuit chips are embedded in one package, a stacked package is a method of stacking two or more single chip packages containing one integrated circuit chip. to be.
한편, 반도체 패키지의 표면실장 면적을 최소화하고 또한 전기접속 길이를 최소화하여 전기적 특성을 향상시킬 목적으로 솔더 볼(Solder Ball)을 외부 접속 단자로 사용하는 볼 그리드 어레이(Ball Grid Array; BGA) 패키지나 칩 규모 패키지(Chip Scale Package; CSP)에 대한 연구가 활발히 이루어지고 있다. 하지만, 이러한 유형의 패키지를 이용하여 용량을 증대시키기 위한 적층 기술은 패키지 구조상 구현하기가 매우 어렵다. 현재 주로 사용되는 적층 패키지의 유형은 TSOP(Thin Small Outline Package)에 한정되어 있는 실정이며, 따라서 BGA 패키지나 CSP에 대한 적층 기술이 요구되고 있다.Meanwhile, a Ball Grid Array (BGA) package that uses a solder ball as an external connection terminal for the purpose of minimizing the surface mounting area of the semiconductor package and minimizing the electrical connection length to improve electrical characteristics. Chip scale packages (CSPs) are being actively researched. However, stacking techniques for increasing capacity using this type of package are very difficult to implement due to the package structure. Currently, the type of stacked package mainly used is limited to Thin Small Outline Package (TSOP), and thus, a stacking technology for a BGA package or a CSP is required.
일반적으로 적층 기술은 적층 패키지를 위해 다른 형태의 패키지가 필요하고, 적층 패키지에 적용할 새로운 테스트 기반 시설에 대한 투자가 필요하며, 적층 패키지를 위해 다른 형태의 패키지를 다른 용도로 사용할 수 없는 여러 문제점들을 안고 있다.In general, stacking technologies require different types of packages for stacking packages, investment in new test infrastructure to apply to stacking packages, and many other issues that prevent the use of different types of packages for stacking packages. I am listening.
따라서, 본 발명은 이러한 종래기술에서의 문제점들을 해결하고 새로운 요구와 필요에 부응하기 위하여 안출된 것으로서, 본 발명의 목적은 미세 볼 그리드 어레이(Fine Ball Grid Array; FBGA) 형태의 새로운 적층 패키지를 제공하기 위한 것이다.Accordingly, the present invention has been made to solve the problems in the prior art and to meet new demands and needs, and an object of the present invention is to provide a new stacked package in the form of a fine ball grid array (FBGA). It is to.
도 1은 본 발명의 적층 패키지에 사용되는 단품 패키지를 개략적으로 나타내는 평면도.1 is a plan view schematically showing a one-piece package used in the laminated package of the present invention.
도 2는 도 1의 II-II 선을 따라 절단한 단면도.FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1. FIG.
도 3은 도 1의 III-III 선을 따라 절단한 단면도.3 is a cross-sectional view taken along the line III-III of FIG.
도 4는 본 발명의 실시예에 따른 적층 패키지를 개략적으로 나타내는 단면도.4 is a cross-sectional view schematically showing a laminated package according to an embodiment of the present invention.
도 5는 본 발명의 다른 실시예에 따른 적층 패키지를 개략적으로 나타내는 단면도.5 is a cross-sectional view schematically showing a laminated package according to another embodiment of the present invention.
도 6은 본 발명의 또 다른 실시예에 따른 적층 패키지를 개략적으로 나타내는 단면도.6 is a cross-sectional view schematically showing a laminated package according to another embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
10, 20, 30: 단품 패키지11: 반도체 칩10, 20, 30: single package 11: semiconductor chip
12: 본딩 패드13: 회로 기판12: bonding pad 13: circuit board
14: 회로 배선15: 연결 단자14: circuit wiring 15: connection terminal
16: 기판 홈32: 솔더 볼16: Substrate Groove 32: Solder Ball
40, 50: 연결 수단60: 스페이서40, 50: connection means 60: spacer
상기 목적을 달성하기 위하여 제공되는 본 발명의 적층 패키지는 다음과 같은 구성으로 이루어진다. 본 발명의 적층 패키지는 두 개 이상의 단품 패키지가 상하로 적층되며, 각각의 단품 패키지는, 상부면에 다수개의 본딩 패드가 형성되는 반도체 칩과, 본딩 패드의 위치에 대응하여 기판 홈이 형성되고 반도체 칩의 상부면에 접착되는 회로 기판과, 회로 기판의 상부면에 형성되고 기판 홈을 통하여 본딩 패드에 접합되는 다수개의 회로 배선을 포함한다. 특히, 본 발명의 적층 패키지는 상하로 적층된 단품 패키지의 각각의 회로 배선을 전기적으로 연결하는 연결 수단과, 하부에 위치한 단품 패키지에 형성되는 다수개의 솔더 볼을 포함한다.Laminated package of the present invention provided to achieve the above object consists of the following configuration. In the laminated package of the present invention, two or more single packages are stacked up and down, and each single package includes a semiconductor chip in which a plurality of bonding pads are formed on an upper surface thereof, a substrate groove is formed corresponding to the position of the bonding pads, and the semiconductor And a circuit board bonded to the upper surface of the chip, and a plurality of circuit wires formed on the upper surface of the circuit board and bonded to the bonding pad through the substrate groove. In particular, the laminated package of the present invention includes a connecting means for electrically connecting the respective circuit wiring of the single-piece package stacked up and down, and a plurality of solder balls formed in the single-piece package located below.
본 발명의 적층 패키지에 있어서, 회로 기판의 양측면에 각각의 회로 배선과연결되는 다수개의 연결 단자가 더 형성되며, 연결 수단은 상하로 적층된 단품 패키지의 각각의 연결 단자를 전기적으로 연결하는 것이 바람직하다.In the laminated package of the present invention, a plurality of connection terminals connected to respective circuit wires are further formed on both side surfaces of the circuit board, and the connection means is preferably electrically connected to each connection terminal of the single-piece package stacked up and down. Do.
또한, 본 발명의 적층 패키지에 있어서, 연결 수단은 회로 배선 또는 연결 단자에 대응하는 회로 패턴이 형성되어 있는 테이프 또는 피시비인 것이 바람직하며, 연결 단자는 반으로 절단된 형태의 비아 홀에 전도성 물질이 도금되어 형성되는 것이 바람직하다.In addition, in the laminated package of the present invention, the connecting means is preferably a tape or a PCB in which a circuit pattern corresponding to a circuit wiring or a connecting terminal is formed, and the connecting terminal is formed of a conductive material in a via-hole cut in half. It is preferably formed by plating.
아울러, 본 발명에 따른 적층 패키지의 연결 수단은 열압착 또는 솔더링에 의하여 회로 배선 또는 연결 단자에 연결되는 것이 바람직하며, 연결 수단 사이에는 스페이서가 형성될 수 있다. 본 발명의 적층 패키지에 사용되는 각각의 단품 패키지는 미세 볼 그리드 어레이 패키지인 것이 바람직하다.In addition, the connection means of the laminated package according to the present invention is preferably connected to the circuit wiring or the connection terminal by thermocompression bonding or soldering, a spacer may be formed between the connection means. Each single package used in the laminated package of the present invention is preferably a fine ball grid array package.
이하, 첨부 도면을 참조하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1은 본 발명의 적층 패키지에 사용되는 단품 패키지를 개략적으로 나타내는 평면도이며, 도 2와 도 3은 도 1의 II-II 선과 III-III 선을 따라 각각 절단한 단면도이다.1 is a plan view schematically showing a one-piece package used in the laminated package of the present invention, Figures 2 and 3 are cross-sectional views taken along the line II-II and III-III of FIG.
도시된 바와 같이, 본 발명의 적층 패키지에 사용되는 단품 패키지(10)는 소위 미세 볼 그리드 어레이(Fine Ball Grid Array; FBGA) 형태로 이루어진다. 단품 패키지(10)는 반도체 칩(11)과 그 상부면에 접착된 회로 기판(13)으로 구성된다. 반도체 칩(11)의 상부면 중앙에는 다수개의 본딩 패드(12)가 형성되며, 그에 대응하는 위치의 회로 기판(13)에는 기판 홈(16)이 형성된다. 회로 기판(13)의 상부면에는 다수개의 회로 배선(14)이 형성되어 기판 홈(16)을 통하여 노출된 본딩 패드(12)와 접합된다.As shown, the unit package 10 used in the laminated package of the present invention is made in the form of a so-called fine ball grid array (FBGA). The single package 10 is composed of a semiconductor chip 11 and a circuit board 13 bonded to an upper surface thereof. A plurality of bonding pads 12 are formed in the center of the upper surface of the semiconductor chip 11, and a substrate groove 16 is formed in the circuit board 13 at a position corresponding thereto. A plurality of circuit wires 14 are formed on the upper surface of the circuit board 13 and bonded to the bonding pads 12 exposed through the substrate grooves 16.
특히, 회로 기판(13)의 양측면에는 각각의 회로 배선(14)과 연결되는 연결 단자(15)가 형성된다. 연결 단자(15)는 반으로 절단된 형태의 비아 홀(Via Hole)에 전도성 물질이 도금되어 형성된다. 한편, 도 1 내지 도 3에 도시된 단품 패키지(10)에는 일반적으로 외부 접속 단자로서 사용되는 솔더 볼이 제거되어 있지만, 솔더 볼이 제거되지 않고 남아 있을 수도 있다. 또한, 필요한 경우, 연결 단자(15) 대신에 회로 배선(14) 자체가 연결 단자(15)의 역할을 수행할 수도 있다.In particular, connecting terminals 15 connected to the respective circuit wirings 14 are formed on both side surfaces of the circuit board 13. The connection terminal 15 is formed by plating a conductive material in a via hole cut in half. On the other hand, although the solder ball generally used as the external connection terminal is removed from the single package 10 shown in FIGS. 1 to 3, the solder ball may remain without being removed. In addition, if necessary, the circuit wiring 14 itself may serve as the connection terminal 15 instead of the connection terminal 15.
이상 설명한 구성의 단품 패키지(10)를 두 개 이상 적층하여 본 발명의 적층 패키지를 구현한다. 도 4 및 도 5는 각각 두 개의 단품 패키지를 적층한 적층 패키지의 예를 도시하고 있으며, 도 6은 네 개의 단품 패키지를 적층한 적층 패키지의 예를 도시하고 있다.The laminated package of the present invention is implemented by stacking two or more unit packages 10 having the above-described configuration. 4 and 5 each show an example of a laminated package in which two single packages are stacked, and FIG. 6 shows an example of a laminated package in which four single packages are stacked.
도 4를 참조하면, 적층 패키지(100)는 앞서 설명한 두 개의 단품 패키지(20, 30)를 상하로 적층하여 구성된다. 도면에 도시되지는 않았지만 상하부 패키지(20, 30)를 적층시킬 때 에폭시(Epoxy)와 같은 접착제를 사용할 수 있다. 특히, 하부 패키지(30)에는 외부 접속 단자로서 사용되는 다수개의 솔더 볼(32, Solder Ball)이 형성된다. 또한, 상부 패키지(20)와 하부 패키지(30)의 측면에 각각 형성된 연결 단자(15)들은 연결 수단(40)에 의하여 전기적으로 연결된다. 연결 수단(40)으로는 테이프 또는 피시비(PCB) 형태가 모두 가능하며, 각 연결 수단(40)에는 연결 단자(15)들에 대응하는 회로 패턴이 형성되어 있음은 물론이다.Referring to FIG. 4, the stack package 100 is formed by stacking two single piece packages 20 and 30 described above up and down. Although not shown in the drawings, an adhesive such as epoxy may be used when stacking the upper and lower packages 20 and 30. In particular, the lower package 30 is provided with a plurality of solder balls 32 used as external connection terminals. In addition, the connection terminals 15 formed on the side surfaces of the upper package 20 and the lower package 30 are electrically connected by the connecting means 40. The connecting means 40 may be in the form of a tape or PCB (PCB), and each of the connecting means 40 is formed with a circuit pattern corresponding to the connecting terminals 15, of course.
한편, 본 발명의 다른 실시예의 경우, 적층 패키지는 연결 단자들이 형성되지 않은 단품 패키지들을 사용하여 구성할 수도 있다. 이러한 경우, 도 5에 도시된 바와 같이, 연결 수단으로서 표면에 솔더 도금이 되어 있는 테이프(50)를 사용하여 금 도금이 되어 있는 회로 배선(14)에 열압착시키거나 솔더링(Soldering)함으로써 상하부 패키지(20, 30)를 상호 연결한다.Meanwhile, in another embodiment of the present invention, the stack package may be configured using single packages in which connection terminals are not formed. In this case, as shown in FIG. 5, the upper and lower packages are formed by thermo-compression bonding or soldering to the gold-plated circuit wiring 14 using the tape 50 with solder plating on the surface as a connecting means. Interconnect (20, 30).
또한, 세 개 이상의 단품 패키지들을 적층할 경우, 도 6에 도시된 바와 같이, 연결 수단으로서 테이프(50)를 사용하되 각 테이프(50) 사이에 스페이서(60, Spacer)를 사용하여 테이프(50) 접합부의 강도를 높이고 신뢰성과 작업성을 향상시킬 수 있다.In addition, when stacking three or more single packages, as shown in Figure 6, using the tape 50 as a connecting means, but using a spacer 60 (Spacer) between each tape 50, the tape 50 It can increase the strength of the joint and improve the reliability and workability.
이상 설명한 바와 같이, 본 발명은 미세 볼 그리드 어레이 패키지가 가지고 있는 장점을 그대로 살리면서 적층 패키지를 구현할 수 있는 장점이 있다. 즉, 미세 볼 그리드 어레이 형태의 단품 패키지들을 사용함으로써 반도체 패키지의 표면실장 면적을 최소화하고 또한 전기접속 길이를 최소화하여 전기적 특성을 향상시킬 수 있을 뿐만 아니라, 적층 패키지를 구현함으로써 메모리 용량을 증가시킬 수 있다.As described above, the present invention has an advantage of implementing a laminated package while maintaining the advantages of the fine ball grid array package. That is, by using single-package packages in the form of fine ball grid arrays, the surface mounting area of the semiconductor package can be minimized and the electrical connection length can be minimized to improve the electrical characteristics, and the stack capacity can be implemented to increase the memory capacity. have.
또한, 테스트가 모두 완료된 단품 패키지를 이용하여 적층을 구현하기 때문에 신뢰성과 수율을 향상시킬 수 있으며, 필요에 따라 제품을 제조할 수 있기 때문에 시장의 요구에 쉽게 대처할 수 있는 장점도 있다.In addition, since the stacking is implemented using a single-piece package, all of which have been tested, reliability and yield can be improved, and the product can be manufactured as needed, so that it is easy to meet the market demand.
본 명세서와 도면에는 본 발명의 바람직한 실시예에 대하여 개시하였으며,비록 특정 용어들이 사용되었으나, 이는 단지 본 발명의 기술 내용을 쉽게 설명하고 발명의 이해를 돕기 위한 일반적인 의미에서 사용된 것이지, 본 발명의 범위를 한정하고자 하는 것은 아니다. 여기에 개시된 실시예 외에도 본 발명의 기술적 사상에 바탕을 둔 다른 변형예들이 실시 가능하다는 것은 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 자명한 것이다.In the present specification and drawings, preferred embodiments of the present invention have been disclosed. Although specific terms have been used, these are merely used in a general sense to easily explain the technical contents of the present invention and to help understanding of the present invention. It is not intended to limit the scope. It is apparent to those skilled in the art that other modifications based on the technical idea of the present invention can be carried out in addition to the embodiments disclosed herein.
Claims (8)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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KR1020010077272A KR20030046934A (en) | 2001-12-07 | 2001-12-07 | Stack package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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KR1020010077272A KR20030046934A (en) | 2001-12-07 | 2001-12-07 | Stack package |
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KR20030046934A true KR20030046934A (en) | 2003-06-18 |
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KR1020010077272A KR20030046934A (en) | 2001-12-07 | 2001-12-07 | Stack package |
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2001
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