KR20030045535A - Deinterleaving apparatus and method - Google Patents

Abstract

PURPOSE: A deinterleaving device and a method therefor are provided to read symbols stored in the first memory, and to store portions of the symbols of remaining input frames stored in the second memory in a shared region of the first memory during the reading time by using pause time, thereby reducing the size of the memories. CONSTITUTION: The first memory(51) has size of storing at least one frame. The second memory(52) has smaller size than the size of the first memory(51). A controller(53) reads symbols by deinterleaving the symbols written in the first memory(51) in a previous section of a predetermined time section, simultaneously writes portions of symbols of input frames in the second memory(52), and writes the rest symbols of the input frames in a shared region of the first memory(51) in a back section of the predetermined time section. The controller(53) reads the symbols by deinterleaving the symbols written in the shared region of the first memory(51) with the symbols written in the second memory(52) when symbols of the next frames are stored in the first memory(51).

Description

Deinterleaving apparatus and method {DEINTERLEAVING APPARATUS AND METHOD}

The present invention relates to a deinterleaving apparatus and method, and more particularly to an apparatus and method for reducing the memory of the deinterleaver.

In general, in a mobile communication system, an interleaver and a deinterleaver existing in a modem use a method of reducing the size of memory in order to reduce complexity. The interleaver and deinterleaver are used to reduce correlation between symbols by the channel and to obtain time diversity.

That is, the interleaver is a device that outputs the symbols to be transmitted in a predetermined time (frame) in a predetermined order, and the deinterleaver stores the symbols of one frame, which is a basic unit of interleaving, in memory in the order in which they are received, and then stores them in the original order. It is a device sorted accordingly. Therefore, the larger the data rate within a predetermined time (frame), the larger the memory size is required.

Hereinafter, the deinterleaver proposed by the 3GPP2 standard will be described as an example.

The deinterleaver stores demodulated symbols of a channel input in real time in a memory. Then, after the last symbol of the frame, which is a basic unit, is input, it is deinterleaved and output in synchronization with a request time of a subsequent block using the symbols. In this case, a decoder is generally a rear block of the deinterleaver.

In the case of a 3GPP2 rake receiver, the deinterleaver stores the symbols in units of frames from the combining. After the last symbol of the frame is input, it is notified to the channel decoder, and the symbols stored in the original order are transferred to the decoder in accordance with the request of the channel decoder. Here, while transmitting the symbols to the channel decoder, the deinterleaver receives the symbols corresponding to the next frame from the combiner. In this case, when the input symbols are stored in a memory that is currently being read, a new input symbol is overwritten to an address of a memory not yet read due to the characteristics of the deinterleaver. The memory to store the frame to be output and the frame to be input from the combiner are used separately.

Each of the memories is configured to correspond to the maximum number of symbols of one frame. The scheme of operating the two memories is that while one memory writes input symbols every frame, the other memory reads previously stored symbols. And, every frame, the roles of the two memories change. The structure thereof is shown in FIG.

As shown, the deinterleaver includes two memories 11 and 12 and a controller that writes a symbol to the two memories 11 and 12 and generates an address for reading symbols from the memories. 13, and a selector 14 for selecting the output of the memory. Herein, the controller 13 includes a chip select signal for controlling input speeds and output speeds of symbols as well as the address, a write enable signal for indicating a write operation, and the selector 14. Generates a selection signal for selecting the output of

2 is a diagram illustrating operations of the first memory 11 and the second memory 12 on the time axis. As shown in the drawing, the number of symbols in one frame is 8, and 1 → 2 → 3 → 4 → 5 → 6 → 7 → 8 symbols coming in the order of 1 → 8 → 5 → 4 → 3 → 6. The operation of outputting in the order of → 7 → 2 is explained. As described above, the first memory 11 and the second memory 12 alternately perform a write operation with each other, and the other memory 12 is stored while the write operation is performed in one particular memory 11. Read operation is performed on the previous frame. Note that the read operation is performed within a short time of the write operation. That is, the memory that performs the read wastes resources without any operation while other memories complete the write operation after completing the read operation.

The operation shown in FIG. 2 is performed by the selector of the selector generated by the controller 13, the address signal of the two memories, the chip select signal, and the write enable signal. A timing diagram of the signals is shown in FIG.

As shown, the Chip Select signal and the Write Enable signal are " active low signals " which are operated at a low edge, and the selection signal is selected. ) Reads symbols from the first memory 11 when '1' and reads symbols from the second memory 12 when '0'. That is, the memory for writing the symbols sequentially writes the input symbols in response to the write enable signal. Here, the recording speed is achieved in synchronization with the recording chip select signal. As shown, the write chip select signal and the write enable signal are generated with the same period. On the other hand, the memory for reading symbols deinterleaves the symbols stored in response to the read chip selection signal having a shorter period than the write chip selection signal by the address provided from the controller 13. This operation is shown in a flowchart as shown in FIG.

First, referring to the write operation, the controller 13 first checks whether the first memory 11 is to write symbols in step 401. If it is time for the first memory 11 to write symbols, the controller 13 proceeds to step 403 to operate the first memory 11 as a recording memory. Otherwise, the controller 13 proceeds to step 405. 2 Memory 12 is operated as a recording memory.

Next, referring to the read operation, the controller 13 first checks in step 411 whether the first memory 1 is ready to write symbols. If the first memory 11 is to write symbols, the controller 13 proceeds to step 415 to operate the second memory 12 as a read memory, otherwise proceeds to step 413. The first memory 11 is operated as a read memory.

Problems exhibited in the prior art described above are as follows.

In general, the symbol bits used in the deinterleaver are multi-bits. Therefore, the following memory size is required to store one frame period.

(bits per symbol) * (maximum number of symbols per frame) * (number of memory to alternate read / write) = (bits per symbol) * N * 2

For example, assuming that the receiver supports a data rate of 230.4kbps in the 3GPP2 standard forward and deinterleaver of a receiver composed of 6 bits per symbol, the maximum number of symbols per frame is 12,288. The required memory size is 6bit * 12,288 * 2 = 147,456 bits, which is a significant part of the hardware of the entire modem.

In addition, a channel decoder, which is a rear block of the deinterleaver, reads symbols stored in the deinterleaver for a short processing time for a short processing time. At this time, after the channel decoder reads out all the symbols, the read memory has no access until the symbols of the next input frame are recorded, as in the "No access time" shown in FIG. You will have unnecessary time. In other words, the symbols that have already been stored in the read memory have been read out during the "No access time" period shown by the diagonal line in FIG. 2, but they have been left unchanged even though new symbols can be recorded. In other words, the deinterleaver according to the related art has a problem of unnecessary waste of a large amount of memory in hardware.

Accordingly, an object of the present invention is to provide an apparatus and method for reducing the memory size of a deinterleaver in a mobile communication system.

According to a first aspect of the present invention for achieving the above object, a deinterleaving apparatus includes a first memory having a size capable of storing at least one frame, a second memory having a smaller size than the first memory, and a symbol. Reads the symbols stored in the first memory and stores some symbols of the remaining input frames in the second memory during the read time by using the remaining idle time after reading the symbols stored in the first memory. And a controller for controlling to store the data in the shared area.

According to a second aspect of the present invention, the first and second memories are accessed by a deinterleaver having a first memory having a size capable of storing at least one frame and a second memory having a smaller size than the first memory. The method deinterleaves and reads the symbols recorded in the first memory in the preceding section of the predetermined time period required to write the symbols of the frame, and simultaneously writes some symbols of the input frame into the second memory. And recording the remaining symbols of the input frame in a shared area of the first memory in a later section of the predetermined time interval, storing the symbols of the next frame of the input frame in the first memory, and simultaneously Interleaving and outputting symbols recorded in a shared area of the second memory and the first memory; The features.

1 is a block diagram of a deinterleaver having two memories of the same size according to the prior art.

2 illustrates the operation of a deinterleaver according to the prior art.

3 is a timing diagram showing control signals for controlling memory access in a deinterleaver according to the prior art.

4 is a diagram illustrating a control procedure for memory access in a deinterleaver according to the prior art.

5 is a block diagram of a deinterleaver having two memories of different sizes according to an exemplary embodiment of the present invention.

6 is a diagram illustrating an operation of a deinterleaver according to an embodiment of the present invention.

7 is a timing diagram showing control signals for controlling memory access in a deinterleaver according to an embodiment of the present invention.

8 is a diagram illustrating a control procedure for memory access in a deinterleaver according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In describing the present invention, if it is determined that the detailed description of the related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

5 illustrates a configuration of a deinterleaver according to an embodiment of the present invention. The structure of the deinterleaver according to the present invention is similar to that of the deinterleaver described in the prior art. If there is only a difference, the size of the second memory 52 is smaller than that of the first memory 51, and the operation of the controller 53 is different as the size of the second memory is reduced.

Referring to FIG. 5, the controller 53 includes an address signal for writing and reading symbols at a corresponding position, a chip select signal for enabling writing and reading, and a write enable. A signal is generated and provided to the first and second memories. The controller 53 provides the selector 54 with the selection signal for controlling the output of the selector 54. The first memory 51 and the second memory 52 sequentially store symbols input in response to various control signals from the controller 53, deinterleave the stored symbols, and read the symbols. The selector 54 receives the outputs of the first memory 51 and the second memory 52, and selects one of two inputs by a selection signal from the controller 53. The symbols thus output are input to a subsequent channel decoder.

Basically, in the present invention, some symbols of a frame currently being recorded in the second memory 52 are stored in the first memory 51 by using the time remaining until the next memory is written after the first memory 51 completes reading. It is characterized by recording in). This effectively uses the resources of the memory.

6 is a diagram illustrating operations of the first memory 51 and the second memory 52 according to an embodiment of the present invention on a time axis. As shown in the drawing, the number of symbols in one frame is 8, and 1 → 2 → 3 → 4 → 5 → 6 → 7 → 8 symbols coming in the order of 1 → 8 → 5 → 4 → 3 → 6. The operation of outputting in the order of → 7 → 2 is explained. Here, the case where the read time is smaller than 1/2 of a maximum of one frame is shown, and the first memory is shared by using the remaining access time after reading. In this case, in order to distinguish between a memory part to be shared and a part not to be shared, an inverse D of the specific gravity of an access time in one frame is defined as in Equation 1 below.

Since a factor of 1 or less is not considered in a hardware implementation, D is a maximum integer that satisfies the above equation. Thus, in the case of FIG. 6, the "D" becomes "2" because the access time for reading the symbol is smaller than half of the time of one frame.

For example, looking at the second frame section (the second frame boundary to the third frame boundary) in which the first memory 51 operates as a read memory, the symbols of the previous frame stored in the first memory 51 s1, s2, ..., s8 are read in the first half section of the frame, and some symbols s5, s6, s7, s8 of the currently input frame are recorded in the rear half section of the first memory 51 have. That is, the size of the memory is reduced by writing the symbols to be written in the second memory to the read memory 51 using the no access tme of the read memory.

In the third frame section (third frame boundary to fourth frame boundary), the symbols of the input frame are sequentially written to the first memory 51 and the symbols s8, s5, s6 of the previous middle frame are recorded. , s7 is read from the first memory 51. Here, the read symbols s8, s5, s6, and s7 are stored in the rear half section of the first memory 51, and are read in advance while the currently input symbols are sequentially stored in the front half section of the prem. Because of this, new symbols are not overwritten in the location where the previous symbols are stored. If a record and a read signal collide, the read signal is given priority. That is, in the third frame section, the symbols of the previous frame recorded in the first memory 51 and the second memory 52 are deinterleaved and read. That is, the symbols s5, s6, s7 and s8 are read from the first memory 51 and the symbols s1, s2, s3 and s4 are read from the second memory 52.

Here, the start signal of the idle time is defined, and when the start signal of the idle time is activated, the input symbols are always written to a larger memory (first memory) of two memories, and a large memory (first When reading from the first memory, the same operation as in the prior art is performed. When reading symbols from the small memory (second memory), some symbols of the frame are read from the large memory (first memory).

FIG. 7 illustrates timing of a select signal, an address signal, a chip select signal, and a write enable signal of a selector generated by the controller 53 according to an exemplary embodiment of the present invention. The figure is shown. As illustrated, the first memory 51 and the second memory 52 indicate an address indicating a symbol stored when the write enable signal is high and the chip select signal is low. Read from location. On the other hand, when the chip select signal and the write enable signal are both low, the input symbol is recorded at the position indicated by the address.

In the case of the first memory serving as a shared memory, after the completion of the reading in the section after the second frame, the currently input symbols are recorded, and the recorded symbols are read in the front section of the frame in the next third frame section. . In this case, in the preceding section of the third frame section, the first memory 51 performs a recording operation of a currently input frame and a read operation of a previously input frame. Thus, the chip select signal and the write enable signal are adjusted so that the two operations can occur without collision. When viewing the third frame section, the operation of the first memory 51 according to time is as follows.

Write symbol 0 of the current frame-> Read symbols 7 and 4 of the previous frame-> Write symbol 1 of the current frame-> Write symbol 2 of the current frame-> Read symbols 5 and 6 of the previous frame- > Record symbol 3 of current frame-> Record symbol 4, 5, 6, 7 of current frame

In addition, referring to the second memory 52, after reading the stored symbol 0, the processor waits until the symbols 7 and 4 are read from the first memory 51, and then reads the symbols 3 and 2. do. After waiting for the symbols 5 and 6 to be read from the first memory 51, the symbol 1 is read.

8 shows a control procedure of the controller 53 according to an embodiment of the present invention.

First, referring to the recording operation, first, when the recording of the input symbol is required, the controller 53 checks whether the first memory 51 is a recording memory for recording symbols in step 801. If the first memory is the write memory, the controller 53 proceeds to step 803 to check whether the first memory 51 is reading symbols. This is because the first memory 51 operates as a shared memory. That is, the symbol read operation occurring in the front half section of the third frame of FIG. 7 is detected. If the first memory 51 is being read, it waits until the reading is completed, and if not, the process proceeds to step 809 to sequentially write input symbols to the first memory 51.

On the other hand, if the first memory 51 is determined as the read memory in step 801, the controller 53 proceeds to step 805 to determine whether the write address generated corresponds to the address (hereinafter referred to as shared address) of the shared memory. Check it. In FIG. 7, a section in which the first memory 51 operates as the read memory is a second frame section. If the write memory is the second memory and the generated write address is the shared address, the controller 53 proceeds to step 809 to enter the position indicated by the write address in the first memory 51. Record the symbol. Meanwhile, the recorded symbols are symbols remaining after being recorded in the second memory 52. On the other hand, if the generated write address is not the shared address, the controller 51 proceeds to step 807 and sequentially writes the input symbols to the second memory 52. In the case of writing symbols in the second memory, if the addresses constituting the second memory 52 are not sequentially (for example, 0, 2, 5, 7), a process of concatenating them is necessary. Do. That is, 0, 2, 5, and 7 are mapped to 0, 1, 2, and 3 respectively.

Next, referring to the read operation, first, when the symbol read is required, the controller 53 checks whether the first memory 51 is a write memory to write symbols in step 811. If the first memory 51 is the write memory, the controller 53 proceeds to step 813. Otherwise, if it is a read memory, the controller 53 proceeds to step 817 to read the symbols stored in the first memory 51. In FIG. 7, a section in which the first memory operates as a read memory corresponds to a second frame section, and a section in which the first memory operates as a write memory corresponds to a first and third frame sections. On the other hand, the controller 53 checks whether the read address generated in step 813 is an address corresponding to the shared memory (4, 5, 6, 7 in FIG. 7). If the read memory is the second memory 52 and the generated read address is the shared address, the controller 53 proceeds to step 817 to read the symbol indicated by the read address in the first memory 51. . On the other hand, if the read address is not the shared address, the controller 53 proceeds to step 815 to read the symbol indicated by the read address in the second memory 52.

As described above, when a symbol of the shared memory is read out, a write operation is also performed. When the dual port is not used, a collision occurs when both writing and reading occur at the same time. If a conflict occurs, priority is given to reading.

In addition, when using the present invention, the memory ratio that is reduced compared to the prior art is defined as Equation 2 below. That is, the size of the memory can be reduced by the weight of idle time in one frame.

According to Equation 2, the present invention supports a 3GPP2 standard forward data rate of 230.4 kbps, uses 6 bits per symbol, and no access time is 1 / frame in one frame. When applied to a deinterleaver that occupies 2, the size of 147,456 bits of memory can be reduced by 3/4 to the size of 110,592 bits of memory.

Reducing hardware complexity is a critical issue for any system implementation. Especially in mobile communication systems, it is essential to reduce hardware complexity in terms of miniaturization and low power requirements. That is, it is very useful to reduce the size (memory size) of the interleaver / deinterleaver of the modem, which is a key element of the mobile communication system. In addition to the deinterleaver, the present invention is applicable to all memory access schemes in which output symbols and data are output faster than input symbols and data. Can be.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by those equivalent to the scope of the claims.

As described above, the present invention has the advantage of reducing the hardware size of the deinterleaver by reducing the size of the memory occupying the largest size in the deinterleaver.

Claims (5)

In the deinterleaving apparatus, A first memory having a size capable of storing at least one frame, A second memory having a smaller size than the first memory; Read and deinterleave the symbols recorded in the first memory in the front section of the predetermined time period, and simultaneously write some symbols of the input frame to the second memory, and input the data in the back section of the predetermined time section. The remaining symbols of the frame are recorded in the shared area of the first memory, and the symbols written in the second memory and the shared area of the first memory are stored simultaneously when the symbols of the next frame of the input frame are stored in the first memory. And a controller for controlling to deinterleave and read the symbols recorded in the apparatus. A method of accessing the first and second memories in a deinterleaver having a first memory having a size capable of storing at least one frame and a second memory having a size smaller than the first memory, Deinterleaving and reading symbols recorded in the first memory in a preceding section of a predetermined time period, and simultaneously writing some symbols of an input frame to the second memory; Recording the remaining symbols of the input frame in a shared area of the first memory in a later section of the predetermined time interval; Storing symbols of the next frame of the input frame in the first memory and simultaneously deinterleaving the symbols written in the second memory and the symbols recorded in the shared area of the first memory. Characterized in that the method. The method of claim 2, The preceding section of the predetermined time interval is characterized in that the access time (access time) The method of claim 2 The back section of the predetermined time interval is characterized in that the no access time (No access time) A method of accessing the memories in a device having a first memory and a memory having a smaller size than the first memory, Reading data recorded in the first memory at a faster speed than a recording speed in a preceding section of a predetermined time period, and simultaneously recording a portion of the data to be input into the second memory; Recording a remainder of the input data in a shared area of the first memory in a rear section of the predetermined time interval; And storing next input data in the first memory, and simultaneously reading symbols written in the second memory and data recorded in a shared area of the first memory.