KR20030045213A - Plasma display panel and driving method thereof - Google Patents

Abstract

PURPOSE: A plasma display panel and a method for driving the same are provided to prevent the occurrence of flicker by protecting the frequent change of the average picture level(APL) in a predetermined range. CONSTITUTION: A plasma display panel includes an average picture level(APL) block(34) for generating an APL value so as to control the number of the sustain pulses by receiving the video data from outside and an APL determination block(40) for comparing the illumination between the frames and for outputting the average value of the APL of the current frame and the previous frame when the flicker occurs by determining whether the occurrence of the flicker in response to the comparing result.

Description

Plasma display panel and its driving method {PLASMA DISPLAY PANEL AND DRIVING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel and a driving method thereof, and more particularly, to a plasma display panel and a driving method thereof capable of reproducing natural images by preventing flicker.

Plasma Display Panel (hereinafter referred to as "PDP") is a display device using visible light generated from a phosphor when ultraviolet light generated by gas discharge excites the phosphor. PDP is thinner and lighter than Cathode Ray Tube (CRT), which has been the mainstay of display means, and has the advantage of realizing high definition / large screen.

The PDP has an upper substrate and a lower substrate which are installed to face each other with partition walls therebetween. The upper substrate includes first and second electrodes formed in a direction crossing the partition wall. The lower substrate includes an address electrode formed in a direction parallel to the partition wall, and a dielectric layer formed to cover the address electrode. The discharge cell is positioned at the intersection of the address electrode, the first electrode, and the second electrode.

The PDP is driven by dividing one frame into several subfields having different emission counts in order to realize gray levels of an image. Each subfield is divided into a reset period for uniformly causing discharge, an address period for selecting a discharge cell, and a sustain period for implementing gray scale according to the number of discharges.

In the address period, scan pulses are supplied to the first electrode, and data pulses synchronized with the scan pulses are supplied to the address electrodes. At this time, an address discharge occurs in the discharge cell supplied with the scan pulse and the data pulse. After the scan pulses are supplied to all the first electrodes, the sustain pulses are alternately supplied to the first and second electrodes. When a sustain pulse is supplied to the first and second electrodes, sustain discharge occurs in the discharge cells in which the address discharge has occurred.

When the image is to be displayed in 256 gray levels, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields. Here, the reset period and the address period of each subfield are the same for each subfield, while the sustain period and the number of discharges thereof are 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield. , 8). As described above, since the sustain period is changed in each subfield, gray levels of an image can be realized.

1 is a view showing a driving apparatus of a conventional plasma display panel.

Referring to FIG. 1, a conventional PDP driving apparatus includes a first reverse gamma correction unit 2A, a gain control unit 4, an error diffusion unit 6, connected between an input line 1 and a PDP 18. A subfield mapping section 8 and a data sorting section 10; A second reverse gamma correction unit 2B, an APL (Avarage Picture Level) unit 14, and a waveform generator 16 connected between the input line 1 and the PDP 18 are provided.

The first and second inverse gamma correction units 2A and 2B perform inverse gamma correction on the gamma corrected video signal to linearly convert luminance values according to grayscale values of the video signal.

The APL unit 14 receives the video data corrected by the second inverse gamma correction unit 2B and generates an N-stage signal for adjusting the number of sustain pulses. The gain control section 4 amplifies the video data corrected by the first inverse gamma correction section 2A by the effective gain.

The error diffusion unit 6 finely adjusts the luminance value by diffusing an error component of the cell into adjacent cells. The subfield mapping unit 8 reallocates the video data corrected by the error diffusion unit 6 for each subfield.

The data aligning unit 10 converts the video data input from the subfield mapping unit 8 in accordance with the resolution format of the PDP 18 to form an address driving integrated circuit (IC) hereinafter of the PDP 18. Supply).

The waveform generator 16 generates a timing control signal based on the N-stage signal input from the APL unit 14, and converts the generated timing control signal into an address driving IC, a scan driving IC, and a sustain driving IC of the PDP 18. Supply.

In the conventional PDP driving apparatus, the APL unit 14 receives video data and calculates the APL step according to the video data. At this time, as shown in FIG. 2, the number of sustain pulses according to the steps of the APL is determined.

Referring to FIG. 2, the steps of the APL and the number of sustain pulses are inversely related. In other words, as the APL step is increased, the number of sustain pulses decreases, and as the APL step is decreased, the number of sustain pulses increases.

On the other hand, the step of the APL is determined by the video data input from the second inverse gamma correction unit 2B. Thus, if video data changes frequently, the APL stage also changes frequently. At this time, the number of sustain pulses whose number is determined by the APL step is changed as if oscillated, thereby causing a flicker phenomenon in the PDP.

This will be described in detail as follows. For example, if the APL step changes frequently between 30 and 40 steps, the number of sustain pulses will oscillate. In other words, if the APL changes frequently within a certain range, the number of sustain pulses changes as if they oscillate. In this way, if the number of sustain pulses that determines the brightness of the PDP changes vibratingly, flicker occurs in the PDP and a natural screen cannot be displayed.

Accordingly, it is an object of the present invention to provide a plasma display panel and a method of driving the same, which can prevent the occurrence of flicker to reproduce a natural image.

1 is a view showing a driving apparatus of a conventional plasma display panel.

2 is a graph showing the number of sustain pulses that change in response to a change in the APL step.

3 is a view showing a driving device of a plasma display panel according to an embodiment of the present invention;

FIG. 4 is a diagram illustrating details of an APL determination unit illustrated in FIG. 3.

<Description of Symbols for Main Parts of Drawings>

1,20: Input lines 2A, 2B, 22A, 22B: Inverse gamma correction unit

4,24: gain control section 6,26: error diffusion section

8,28: subfield mapping unit 10,30: data alignment unit

14,34: APL section 16,36: waveform generation section

18,38: PDP40: APL decision part

42: delay unit 44: subtractor

46: average value calculation unit 48: comparator

50: memory 52: MUX

In order to achieve the above object, the plasma display panel of the present invention comprises: an APL unit for generating an APL value for adjusting the number of sustain pulses by receiving video data from the outside; And comparing the luminance between frames, and determining whether flicker is generated according to the comparison result, and when flicker occurs, an AP decision unit for outputting an average value of April values of the current frame and the previous frame is provided.

The AP decision unit may include a delay unit for delaying the ALP value output from the ALP unit for one frame of time, and an AP of the previous frame output from the delay unit as the ALP value of the current frame output from the ALP unit. A control signal by comparing a subtractor for subtracting an EL value, a memory in which a maximum ALP value that can be changed without generating flicker between frames, and an ALP value output from the subtractor and an ALP value stored in the memory are compared. A comparator for outputting an average value calculating unit for calculating an average value of the April value of the current frame output from the ALP unit and the April value of the previous frame output from the delay unit, an average value calculating unit receiving a control signal, and And a multiplexer for outputting any one of the APL values of the APL.

The comparator generates a first control signal so that the multiplexer can output the April value input from the average value calculator if the April value input from the subtractor is greater than the April value stored in the memory.

The comparator generates a second control signal so that the multiplexer can output the ALP value input from the ALP unit when the ALP value input from the subtractor is smaller than the ALP value stored in the memory.

An absolute value converting section is further provided between the subtractor and the comparator.

The driving method of the plasma display panel according to the present invention comprises the steps of setting an April step for adjusting the number of sustain pulses by receiving video data, comparing the April step of the current frame with the April step of the previous frame, If the change value of the ALP step of the current frame and the ALP step of the previous frame is larger than the predetermined ALP step, the average ALP step value of the ALP step of the current frame and the APL step of the previous frame is output.

If the change value of the ALP step of the current frame and the ALP step of the previous frame is smaller than a predetermined ALP step, the ALP step of the current frame is output.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 3 to 4.

3 is a view showing a driving apparatus of a plasma display panel according to an embodiment of the present invention.

Referring to FIG. 3, the driving apparatus of the PDP according to the embodiment of the present invention includes a first reverse gamma correction unit 22A, a gain control unit 24, and an error diffusion connected between the input line 20 and the PDP 38. A section 26, a subfield mapping section 28, and a data sorting section 30; A second reverse gamma correction unit 22B, an APL unit 34, an APL determination unit 40, and a waveform generator 36 connected between the input line 20 and the PDP 38 are provided.

The first and second inverse gamma correction units 22A and 22B perform linear gamma correction on the gamma corrected video signal to linearly convert luminance values according to grayscale values of the video signal.

The APL unit 34 receives the video data corrected by the second inverse gamma correction unit 22B and generates an N-stage signal for adjusting the number of sustain pulses. The APL determiner 40 detects a change value of the N-stage signal between frames, and outputs a signal corresponding to the average value between the frames when the detected N-stage signal changes frequently.

The gain control unit 24 amplifies the video data corrected by the first inverse gamma correction unit 22A by the effective gain.

The error diffusion unit 26 finely adjusts the luminance value by diffusing an error component of a cell into adjacent cells. The subfield mapping unit 28 reallocates the video data corrected by the error diffusion unit 26 for each subfield.

The data aligning unit 30 converts the video data input from the subfield mapping unit 28 according to the resolution format of the PDP 38 to convert the address data into an address integrated circuit (IC) of the PDP 38. Supply).

The waveform generator 36 generates a timing control signal based on the N-stage signal input from the APL determiner 40, and generates the timing control signal by using the address driving IC, scan driving IC, and sustain driving IC of the PDP 38. To supply.

In the PDP driving apparatus according to the exemplary embodiment of the present invention, the APL determiner 40 receives an APL step corresponding to the current frame and the previous frame from the APL unit 34. The APL determination unit 40 receiving the APL step from the APL 34 unit checks whether the APL step changes within a predetermined range.

Thereafter, the APL determiner 40 outputs an APL step corresponding to an average value of the current frame and a previous frame when the APL step is changed within a predetermined range, and an APL corresponding to the current frame if the APL step is not changed within a predetermined range. Output the step.

4 is a diagram illustrating an APL determination unit in detail.

Referring to FIG. 4, the APL determiner 40 includes a delay unit 42, a subtractor 44, an average value calculator 46, and a comparator 48 connected between the APL unit 34 and the waveform generator 36. ), A memory 50 and a multiplexer (hereinafter referred to as "MUX") 52.

The delay unit 42 delays a signal of a predetermined step input from the APL unit 34 for one frame of time. The subtractor 44 receives the APL step of the current frame from the APL unit 34 and receives the APL step of the previous frame from the delay unit. Subtractor 44 then subtracts the APL step of the previous frame to the APL step of the current frame.

The average value calculator 46 calculates an average value of the APL stage of the current frame input from the APL unit 34 and the APL stage input from the delay unit 42.

The memory 50 stores an APL value that can be changed without generating flicker. In other words, assuming that the APL is set to 255 steps, if flicker does not occur in the PDP 38 when the inter-frame APL changes by more than ± 10 steps, a value of 10 is stored in the memory 50. As the memory 50, a ROM (Read Only Memory: ROM) is used.

On the other hand, the value stored in the memory 50 is determined by comparing the brightness between the frames, and determines whether the flicker occurs according to the comparison result. That is, the APL value at which flicker is not generated by comparing the luminance between frames is set, and the set APL converted value is stored in the memory 50. On the other hand, as a method of comparing the inter-frame luminance and determining whether flicker is generated according to the comparison result, a known technique generally used is used.

The comparator 48 compares the value input from the subtractor 44 with the value stored in the memory 50 to generate a predetermined control signal. The MUX 52 receiving the control signal from the comparator 48 receives the APL average value between the previous frame and the current frame input from the average value calculator 46 and the APL value of the current frame input from the APL unit 34. Output one.

The operation of the APL determination unit 40 will now be described in detail. First, the delay unit 42 delays an APL step input from the APL unit 34 by one frame and then supplies it to the subtractor 44. The subtractor 44 subtracts the APL signal of the previous frame input from the subtractor 44 in the APL step of the current frame input from the APL unit 34.

For example, if the APL step of the current frame is 250 and the APL step of the previous frame is 200, the subtractor 44 outputs a value of 50. On the other hand, the APL step output from the subtractor 44 may have a negative value. Therefore, an absolute value converting unit (not shown) may be further provided between the subtractor 44 and the comparator 48. The absolute value converting part converts the output value of the subtractor 44 into an absolute value and supplies it to the comparator 48.

The comparator 48 compares the value stored in the memory 50 with the value input from the subtractor 44 and outputs a control signal. For example, if a value of 50 is input from the subtractor 44 and a value of 30 is stored in the memory 50, the comparator 48 outputs a control signal of "0". On the other hand, the comparator 48 outputs a control signal of "1" if a value of 50 is input from the subtractor 44 and a value of 60 is stored in the memory 50.

The average value calculator 46 calculates the average APL step of the APL step of the current frame input from the APL unit 34 and the APL step of the previous frame input from the delay unit 42. The MUX 52 receives an APL step of the current frame from the APL unit 34 and an average APL step from the average value calculator 46. As such, the MUX 52 receiving the APL step and the average APL step of the current frame outputs any one of the APL step and the average APL step of the current frame according to a control signal input from the comparator 48.

For example, when a control signal of "0" is input from the comparator 48, the MUX 52 outputs the APL step of the current frame. In addition, when the control signal of "1" is input, the comparator 48 outputs the average APL step of the previous frame and the current frame.

That is, the driving apparatus of the PDP of the present invention outputs an APL step corresponding to the average of the previous frame and the current frame so that flicker does not occur when it changes within a predetermined range of the APL. Therefore, in the present invention, even if the APL step changes frequently within a predetermined range, the number of sustain pulses does not change rapidly, thereby preventing flicker generation.

As described above, according to the plasma display panel and the driving method thereof according to the present invention, it is possible to prevent the flickering by preventing the APL step from changing frequently within a predetermined range.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (7)

In the plasma display panel driven in a frame unit, An APL unit for receiving an input of video data from outside and generating an APL value for adjusting the number of sustain pulses; And comparing the luminance between the frames and determining whether flicker is generated according to the comparison result, and when the flicker occurs, an ALP determination unit outputting an average value of the ALP values of the current frame and the previous frame. . The method of claim 1, The April decision unit, A delay unit for delaying an ALP value output from the ALP unit for one frame of time; A subtractor for subtracting the April value of the previous frame output from the delay unit with the April value of the current frame output from the April unit; A memory in which a maximum ALP value that can change without generating the flicker between the frames is stored; A comparator for outputting a control signal by comparing the ALP value output from the subtractor with the ALP value stored in the memory; An average value calculation unit for calculating an average value of the April value of the current frame output from the April unit and the April value of the previous frame output from the delay unit; And a multiplexer configured to receive the control signal and output any one of the average value calculator and the APL value of the APL unit. The method of claim 2, The comparator generates a first control signal so that the multiplexer can output an ALP value input from the average value calculator when the ALP value input from the subtractor is smaller than an ALP value stored in the memory. Plasma display panel. The method of claim 2, The comparator generates a second control signal to output the APL value input from the APL unit when the ALP value input from the subtractor is greater than the ALP value stored in the memory. Plasma display panel. The method of claim 2, And an absolute value conversion unit is further provided between the subtractor and the comparator. In the plasma display panel in which the brightness between frames is compared and a predetermined ALP step in which flicker is not generated is set according to the comparison result. Setting the April step for adjusting the number of sustain pulses by receiving video data; Comparing the April step of the current frame with the April step of the previous frame; If the change value of the ALP step of the current frame and the ALP step of the previous frame is smaller than the predetermined ALP step, the average ALP step value of the ALP step of the current frame and the ALP step of the previous frame is output. And a plasma display panel driving method. The method of claim 6, And if the change value of the ALP step of the current frame and the ALP step of the previous frame is larger than the predetermined ALP step, the ALP step of the current frame is output.