JPH08223507A - Video signal amplitude limit circuit - Google Patents
Video signal amplitude limit circuitInfo
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- JPH08223507A JPH08223507A JP7030589A JP3058995A JPH08223507A JP H08223507 A JPH08223507 A JP H08223507A JP 7030589 A JP7030589 A JP 7030589A JP 3058995 A JP3058995 A JP 3058995A JP H08223507 A JPH08223507 A JP H08223507A
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- video signal
- apl
- coefficient
- multiplication coefficient
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は映像信号振幅制限回路に
係り、映像信号のＡＰＬ（平均輝度レベル）の変化が大
きい場合に表示器に印加される映像信号の振幅を徐々に
可変し、輝度の変化を目立たなくするものに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal amplitude limiting circuit, which gradually changes the amplitude of a video signal applied to a display when the APL (average brightness level) of the video signal changes greatly, For those that obscure changes in.
【０００２】[0002]
【従来の技術】表示器にプラズマディスプレイパネル
（ＰＤＰ）を使用する場合、ＰＤＰは点灯のためのプラ
ズマ放電によって温度が上昇し、性能が劣化するという
問題がある。このため、ＰＤＰの駆動回路にＡＰＣ（au
tomatic power control ）回路を設け、ＰＤＰの消費電
力を計測し、この値が所要値以上にならないように電流
制限を行っているが、ＰＤＰの消費電力は映像信号の表
示率（全白の映像信号の全画素の輝度レベルの積算値に
対する一画面の全画素の映像信号野輝度レベルの積算値
の比率）に略比例しているので、図３に示すように、入
力される映像信号の表示率が予め決められた値（例え
ば、40％）以上の場合に輝度／コントラストを制御し、
輝度を低下させ、消費電力を制限している。上述のよう
に、このＡＰＣ動作によって画面の輝度が変化する訳で
あるが、ＡＰＣ回路の追随動作が、例えば、数秒間をか
けて徐々に行われるため、映像信号の表示率が急激に大
幅に変化した場合、輝度の低下する様子が目視でも容易
に判り、違和感を呈するという問題がある。すなわち、
図２（イ）に示すａの特性のように、入力映像信号が全
黒（表示率・略０％）から全白（略100 ％）に変化した
場合、画面の輝度は、図２（ロ）に示すｂ特性のよう
に、映像信号が全白に変わった直後は輝度が急上昇し、
それから数秒の間に徐々に輝度が低下する。なお、上記
表示率は映像信号のＡＰＬで表すことができる。2. Description of the Related Art When a plasma display panel (PDP) is used as a display, there is a problem that the temperature of the PDP rises due to plasma discharge for lighting and the performance deteriorates. For this reason, the APC (au
A tomatic power control) circuit is provided to measure the power consumption of the PDP, and the current is restricted so that this value does not exceed the required value. The ratio of the integrated value of the video signal field luminance level of all the pixels of one screen to the integrated value of the luminance level of all the pixels is approximately proportional to the display rate of the input video signal as shown in FIG. Control the brightness / contrast when is above a predetermined value (eg 40%),
It reduces brightness and limits power consumption. As described above, the brightness of the screen changes due to this APC operation. However, since the follow-up operation of the APC circuit is gradually performed over, for example, several seconds, the display rate of the video signal sharply increases. When changed, there is a problem in that it is easy to visually recognize the manner in which the brightness is lowered, and a sense of discomfort is presented. That is,
When the input video signal changes from all black (display rate, approximately 0%) to all white (approximately 100%), as shown in the characteristic of a in FIG. ), The brightness sharply increases immediately after the video signal changes to all white,
Then, the brightness gradually decreases within a few seconds. The display rate can be represented by the APL of the video signal.
【０００３】[0003]
【発明が解決しようとする課題】本発明はこのような点
に鑑み、入力映像信号のフィールド間のＡＰＬを比較し
て変化を監視し、ＡＰＬの変化の大きさに応じて所要の
係数を算出し、この係数を映像信号に乗算することによ
り、画面の輝度の変化を緩やかにし、ＡＰＬの急変時の
画面の輝度の変化を目立たちにくくすることにある。In view of the above-mentioned problems, the present invention compares APLs between fields of an input video signal to monitor changes and calculates a required coefficient according to the magnitude of changes in APLs. However, by multiplying the video signal by this coefficient, the change in the brightness of the screen is moderated, and the change in the brightness of the screen at the time of the sudden change of the APL is made inconspicuous.
【０００４】[0004]
【課題を解決するための手段】本発明は上述の課題を解
決するため、入力される映像信号の平均輝度レベルを算
出するＡＰＬ算出部と、ＡＰＬ算出部よりのデータをホ
ールドするデータホールド部と、データホールド部にホ
ールドされたデータを取出し、データホールド部に次に
入力されるデータと比較してＡＰＬの差を出力するＡＰ
Ｌ比較部と、ＡＰＬ比較部よりのデータに基づいて所要
の係数を算出する乗算係数算出部と、乗算係数算出部よ
りの係数を前記映像信号に乗算する乗算器とからなり、
乗算器よりの映像信号を出力するようにした映像信号振
幅制限回路を提供するものである。In order to solve the above-mentioned problems, the present invention includes an APL calculating section for calculating an average luminance level of an input video signal, and a data holding section for holding data from the APL calculating section. AP that takes out the data held in the data holding unit, compares it with the data input next to the data holding unit, and outputs the difference in APL
An L comparison unit, a multiplication coefficient calculation unit that calculates a required coefficient based on the data from the APL comparison unit, and a multiplier that multiplies the video signal by the coefficient from the multiplication coefficient calculation unit,
A video signal amplitude limiting circuit for outputting a video signal from a multiplier is provided.
【０００５】[0005]
【作用】以上のように構成したので、本発明による映像
信号振幅制限回路においては、入力映像信号の各フィー
ルドのＡＰＬを前のフィールドのＡＰＬと比較し、差の
大きさに応じて相応する係数を算出し、この係数を乗算
器で映像信号に乗算して出力する。上記係数は、時間の
経過と共に徐々に１に近づける。With the above construction, in the video signal amplitude limiting circuit according to the present invention, the APL of each field of the input video signal is compared with the APL of the previous field, and the corresponding coefficient is determined according to the magnitude of the difference. Is calculated, and the video signal is multiplied by this coefficient by a multiplier and output. The above coefficient gradually approaches 1 with the passage of time.
【０００６】[0006]
【実施例】以下、図面に基づいて本発明による映像信号
振幅制限回路の実施例を詳細に説明する。図１は本発明
による映像信号振幅制限回路の一実施例の要部ブロック
図である。図において、1R、1Gおよび1Bはそれぞれ映像
信号入力端子で、赤、緑および青の各色の映像信号を入
力する。2R、2Gおよび2BはそれぞれＡ／Ｄ変換部で、映
像信号入力端子1R、1Gあるいは1Bよりの映像信号をそれ
ぞれディジタルデータに変換する。３はマトリクス回路
で、Ａ／Ｄ変換部2R、2Gおよび2Bよりの各色の映像信号
をマトリクスする。４は積分・ＡＰＬ算出部で、マトリ
クス回路３よりのデータを１フィールド分を積分し、各
フィールドのＡＰＬ（平均輝度レベル）を算出する。５
は１Ｖ期間ホールド部で、積分・ＡＰＬ算出部４よりの
データを次のフィールドのＡＰＬデータが入力されるま
での間、ホールドする。６はＡＰＬ比較部で、１Ｖ期間
ホールド部５にてホールドされたデータを取出し、今回
１Ｖ期間ホールド部５に入力されるデータと比較し、Ａ
ＰＬの差を出力する。７は乗算係数算出部で、ＡＰＬ比
較部６よりのデータに相応する乗算係数を算出する。8
R、8Gおよび8Bはそれぞれガンマ係数を記憶するγ−Ｒ
ＯＭ（読出専用ガンマ係数メモリ）で、積分・ＡＰＬ算
出部４よりのデータに対応するガンマ係数によりＡ／Ｄ
変換部2R、2Gあるいは2Bよりのデータをガンマ補正す
る。９はフィールドメモリで、γ−ＲＯＭ8R、8Gおよび
8Bよりのデータをそれぞれ１フィールド分記録する。10
は乗算器で、フィールドメモリ９より１フィールド遅れ
で読出される各色のデータに乗算係数算出部７よりのデ
ータを乗算して出力する。Embodiments of the video signal amplitude limiting circuit according to the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram of essential parts of an embodiment of a video signal amplitude limiting circuit according to the present invention. In the figure, 1R, 1G and 1B are video signal input terminals respectively for inputting video signals of red, green and blue colors. Reference numerals 2R, 2G and 2B are A / D converters for converting the video signals from the video signal input terminals 1R, 1G or 1B into digital data. A matrix circuit 3 matrixes the video signals of the respective colors from the A / D converters 2R, 2G and 2B. An integration / APL calculation unit 4 integrates the data from the matrix circuit 3 for one field to calculate the APL (average brightness level) of each field. 5
Is a 1V period hold unit, which holds the data from the integration / APL calculation unit 4 until the APL data of the next field is input. Reference numeral 6 denotes an APL comparison unit that takes out the data held by the 1V period holding unit 5 and compares it with the data input to the 1V period holding unit 5 this time.
Output the difference of PL. Reference numeral 7 denotes a multiplication coefficient calculation unit, which calculates a multiplication coefficient corresponding to the data from the APL comparison unit 6. 8
R, 8G and 8B respectively store gamma coefficients γ-R
The OM (read-only gamma coefficient memory) uses the gamma coefficient corresponding to the data from the integration / APL calculation unit 4 to perform A / D.
Gamma-corrects data from the converter 2R, 2G, or 2B. 9 is a field memory, which is a γ-ROM 8R, 8G and
The data from 8B is recorded for each field. Ten
Is a multiplier that multiplies the data of each color read from the field memory 9 with a delay of one field by the data from the multiplication coefficient calculation unit 7 and outputs the result.
【０００７】次に、本発明による映像信号振幅制限回路
の動作を説明する。映像信号入力端子1R、1Gまたは1Bよ
り入力した赤、緑および青の各色の映像信号はＡ／Ｄ変
換部2R、2Gまたは2Bにそれぞれ入力し、ディジタルデー
タに変換され、γ−ＲＯＭ8R、8Gまたは8Bに入力し、積
分・ＡＰＬ算出部４よりのデータに相応する係数により
ガンマ補正され、フィールドメモリ９に入力して１フィ
ールド分を記録する。前記Ａ／Ｄ変換部2R、2Gおよび2B
よりのデータはマトリクス回路３にも入力してマトリク
スされる。マトリクスされたデータは積分・ＡＰＬ算出
部４に印加され、内蔵の積分回路で１フィールド分を積
分し、各フィールドのＡＰＬを算出する。積分・ＡＰＬ
算出部４よりのデータは１Ｖ期間ホールド部５およびＡ
ＰＬ比較部６に入力する。１Ｖ期間ホールド部５は１Ｖ
の期間、すなわち次のフィールドのＡＰＬデータの算出
されるまでの間、入力されたデータをホールドする。そ
して、積分・ＡＰＬ算出部４より次のフィールドのＡＰ
Ｌデータが出力されたとき、ＡＰＬ比較部６にて、この
フィールドのＡＰＬデータを１Ｖ期間ホールド部５より
取出したＡＰＬデータと比較し、ＡＰＬの差を出力す
る。ＡＰＬ比較部６よりのデータは乗算係数算出部７に
入力し、２つのフィールドのＡＰＬの差に応じた係数を
算出し、この係数を乗算器10に入力し、フィールドメモ
リ９より読出された各色の映像信号にそれぞれ乗算す
る。Next, the operation of the video signal amplitude limiting circuit according to the present invention will be described. The video signals of red, green and blue colors input from the video signal input terminals 1R, 1G or 1B are respectively input to the A / D converters 2R, 2G or 2B and converted into digital data, and the γ-ROM 8R, 8G or The data is input to 8B, gamma-corrected by a coefficient corresponding to the data from the integration / APL calculation unit 4, and input to the field memory 9 to record one field. The A / D converters 2R, 2G and 2B
Data is also input to the matrix circuit 3 to be matrixed. The matrixed data is applied to the integration / APL calculation unit 4, and the built-in integration circuit integrates one field to calculate the APL of each field. Integral / APL
The data from the calculation unit 4 is the 1 V period holding unit 5 and A
Input to the PL comparison unit 6. 1V period hold unit 5 is 1V
During the period, that is, until the APL data of the next field is calculated, the input data is held. Then, the integration / APL calculation unit 4 outputs the AP of the next field.
When the L data is output, the APL comparison unit 6 compares the APL data in this field with the APL data extracted from the 1V period holding unit 5, and outputs the difference in APL. The data from the APL comparison unit 6 is input to the multiplication coefficient calculation unit 7, the coefficient is calculated according to the difference between the APLs of the two fields, the coefficient is input to the multiplier 10, and each color read from the field memory 9 is input. The respective video signals are multiplied.
【０００８】上記乗算係数算出部７は、ＡＰＬ比較部６
よりのデータの大きさに対応する乗算係数を算出し、こ
の乗算係数を時間の経過と共に徐々に１に近づく値に演
算して出力する。すなわち、例えば、ＡＰＬが大幅に上
昇し、このＡＰＬが次のフィールド以降も続いた場合、
最初のフィールドでは 0.8、次のフィールドでは0.81、
その次のフィールドでは0.82、・・・の如く徐々に１に
近づく係数を出力する。これにより、図２（イ）に示す
特性ａのように映像信号入力端子1R等よりの映像信号が
黒から白に急激に変化した場合、乗算器10より出力され
る映像信号は特性ａ′の如く黒から白に徐々に変化する
ものとなり、従ってＰＤＰの駆動回路等に内蔵されるＡ
ＰＣ回路の電流制限量は映像信号が黒から白に急変した
場合に比べて低くなり、輝度の変化量が抑えられ、か
つ、この電流制限の度合は時間と共に徐々に変わるの
で、画面の輝度は、図２（ロ）に示す如く、映像信号に
乗算係数を乗算しない場合は特性ｂであったものが、特
性ｂ′の如く輝度の変化が抑えられ、目視では画面の輝
度の変化が不自然に感じられないものとなる。The multiplication coefficient calculation unit 7 includes an APL comparison unit 6
The multiplication coefficient corresponding to the size of the data is calculated, and this multiplication coefficient is calculated and output to a value gradually approaching 1 with the passage of time. That is, for example, when the APL significantly increases and this APL continues in the next field and thereafter,
0.8 in the first field, 0.81 in the second field,
In the next field, a coefficient that gradually approaches 1 is output, such as 0.82. As a result, when the video signal from the video signal input terminal 1R or the like suddenly changes from black to white as the characteristic a shown in FIG. 2A, the video signal output from the multiplier 10 has the characteristic a '. As described above, the color gradually changes from black to white. Therefore, A built in the drive circuit of the PDP, etc.
The current limit of the PC circuit is lower than that when the video signal suddenly changes from black to white, the amount of change in brightness is suppressed, and the degree of this current limit changes gradually with time. As shown in FIG. 2B, when the video signal is not multiplied by the multiplication coefficient, the characteristic b is changed, but the change in the luminance is suppressed like the characteristic b ′, and the change in the luminance of the screen looks unnatural. It will not be felt.
【０００９】前記乗算係数算出部７に、ＡＰＬの差別に
設定されると共にそれぞれ経過時間に対応して設定され
た乗算係数を記憶するデータテーブルを設け、ＡＰＬの
変化の大きさに相応する係数を時間の経過に従って順次
読出し、乗算器10に出力するようにしてもよい。なお、
各γ−ＲＯＭの次にフィールドメモリ９を設けたのは、
ＡＰＬ比較部６より１フィールド遅れでデータが出力さ
れるので、被乗算映像信号をこの遅延に合わせるためで
ある。また、上記ではフィールド間のＡＰＬの差を比較
するもので説明したが、線順次走査の映像信号の場合は
フレーム間でＡＰＬの差を比較するようにする。The multiplication coefficient calculation unit 7 is provided with a data table for storing the multiplication coefficients set for the APL discrimination and corresponding to the elapsed time, and stores the coefficient corresponding to the magnitude of the APL change. You may make it read sequentially and output to the multiplier 10 as time passes. In addition,
The field memory 9 is provided next to each γ-ROM.
This is because the data is output from the APL comparator 6 with a delay of one field, and the multiplied video signal is adjusted to this delay. In the above description, the difference in APL between fields is compared, but in the case of a line-sequential scanning video signal, the difference in APL between frames is compared.
【００１０】[0010]
【発明の効果】以上に説明したように、本発明による映
像信号振幅制限回路によれば、入力される映像信号のフ
ィールド間のＡＰＬの差に応じて所要の係数を映像信号
に乗算して出力するので、映像信号のＡＰＬが急激に変
化した場合のＰＤＰの輝度の変化による違和感を和らげ
ることができる。As described above, according to the video signal amplitude limiting circuit of the present invention, the video signal is multiplied by the required coefficient in accordance with the difference in APL between the fields of the input video signal and output. Therefore, it is possible to reduce the discomfort caused by the change in the brightness of the PDP when the APL of the video signal changes abruptly.
【図１】本発明による映像信号振幅制限回路の一実施例
の要部ブロック図である。FIG. 1 is a block diagram of an essential part of an embodiment of a video signal amplitude limiting circuit according to the present invention.
【図２】本発明による映像信号振幅制限回路の動作を説
明するための図で、映像信号の入力レベルの変化（イ）
に対する輝度の変化（ロ）の一例の図である。FIG. 2 is a diagram for explaining the operation of the video signal amplitude limiting circuit according to the present invention, showing a change in the input level of the video signal (b).
It is a figure of an example of the change (b) of the luminance with respect to.
【図３】ＡＰＣ動作を説明するための図である。FIG. 3 is a diagram for explaining an APC operation.
1R、1G、1B 映像信号入力端子 2R、2G、2B Ａ／Ｄ変換部 ３ マトリクス回路 ４ 積分・ＡＰＬ算出部 ５ １Ｖ期間ホールド部 ６ ＡＰＬ比較部 ７ 乗算係数算出部 8R、8G、8B γ−ＲＯＭ ９ フィールドメモリ 10 乗算器 1R, 1G, 1B Video signal input terminals 2R, 2G, 2B A / D conversion unit 3 Matrix circuit 4 Integration / APL calculation unit 5 1V period hold unit 6 APL comparison unit 7 Multiplication coefficient calculation unit 8R, 8G, 8B γ-ROM 9 field memory 10 multiplier
Claims (6)
算出するＡＰＬ算出部と、ＡＰＬ算出部よりのデータを
ホールドするデータホールド部と、データホールド部に
ホールドされたデータを取出し、データホールド部に次
に入力されるデータと比較してＡＰＬの差を出力するＡ
ＰＬ比較部と、ＡＰＬ比較部よりのデータに基づいて所
要の係数を算出する乗算係数算出部と、乗算係数算出部
よりの係数を前記映像信号に乗算する乗算器とからな
り、乗算器よりの映像信号を出力するようにした映像信
号振幅制限回路。1. An APL calculating section for calculating an average luminance level of an input video signal, a data hold section for holding data from the APL calculating section, and a data hold section for taking out the data held in the data hold section. Output the difference of APL compared with the data input next to A
A PL comparison unit, a multiplication coefficient calculation unit that calculates a required coefficient based on the data from the APL comparison unit, and a multiplier that multiplies the video signal by the coefficient from the multiplication coefficient calculation unit. A video signal amplitude limiting circuit that outputs a video signal.
に変換するＡ／Ｄ変換部を設け、前記ＡＰＬ算出部に積
分回路を設けてＡ／Ｄ変換部よりのデータを積分し平均
輝度レベルを算出するようにすると共に、前記乗算器に
て、乗算係数算出部よりのデータを前記映像信号に乗算
するようにした請求項１記載の映像信号振幅制限回路。2. An average luminance level is calculated by providing an A / D conversion unit for converting an input video signal into digital data, and providing an integration circuit in the APL calculation unit to integrate the data from the A / D conversion unit. The video signal amplitude limiting circuit according to claim 1, wherein the video signal is multiplied by the data from the multiplication coefficient calculating unit in the multiplier.
別に設けられ各映像信号をそれぞれディジタルデータに
変換するＡ／Ｄ変換部と、各Ａ／Ｄ変換部よりの赤、緑
および青のディジタルデータをマトリクスするマトリク
ス回路とを設け、マトリクス回路よりのデータを前記Ａ
ＰＬ算出部に入力するようにして構成した請求項１また
は請求項２記載の映像信号振幅制限回路。3. An A / D converter provided for each input red, green and blue video signal and converting each video signal into digital data, and red, green and blue from each A / D converter. A matrix circuit for matrixing the digital data of
The video signal amplitude limiting circuit according to claim 1 or 2, wherein the video signal amplitude limiting circuit is configured to be input to a PL calculation unit.
均輝度レベルを算出し、前記データホールド部は入力さ
れるデータを１フィールドの期間ホールドするようにす
ると共に、前記Ａ／Ｄ変換部よりのデータを記録するフ
ィールドメモリを設け、前記乗算器にて、乗算係数算出
部よりの係数をフィールドメモリより読出したデータに
乗算するようにした請求項２または請求項３記載の映像
信号振幅制限回路。4. The APL calculator calculates the average luminance level of each field, the data hold unit holds the input data for a period of one field, and the A / D converter outputs the average brightness level. 4. The video signal amplitude limiting circuit according to claim 2, wherein a field memory for recording data is provided, and the multiplier multiplies the data read from the field memory by the coefficient from the multiplication coefficient calculation unit.
りのデータに基づいて算出した係数に、所要時間の経過
する都度経過時間に対応して設定された値を乗算し、徐
々に１に近づく係数を出力するようにした請求項１、請
求項２、請求項３または請求項４記載の映像信号振幅制
限回路。5. The multiplication coefficient calculation unit multiplies the coefficient calculated based on the data from the APL comparison unit by a value set corresponding to the elapsed time each time the required time elapses, and gradually increases to 1. The video signal amplitude limiting circuit according to claim 1, claim 2, claim 3 or claim 4, which outputs a coefficient that approaches.
設定されると共にそれぞれ経過時間に対応して設定され
た乗算係数を記憶するデータテーブルを設け、前記ＡＰ
Ｌ比較部よりのデータに対応し、経過時間に対応する乗
算係数を取出して出力するようにした請求項１、請求項
２、請求項３または請求項４記載の映像信号振幅制限回
路。6. The multiplication coefficient calculation unit is provided with a data table for storing the multiplication coefficient set for the APL discrimination and corresponding to each elapsed time, and the AP is provided.
5. The video signal amplitude limiting circuit according to claim 1, claim 2, claim 3 or claim 4, wherein the multiplication coefficient corresponding to the data from the L comparison section and corresponding to the elapsed time is extracted and output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7030589A JPH08223507A (en) | 1995-02-20 | 1995-02-20 | Video signal amplitude limit circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7030589A JPH08223507A (en) | 1995-02-20 | 1995-02-20 | Video signal amplitude limit circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08223507A true JPH08223507A (en) | 1996-08-30 |
Family
ID=12308060
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7030589A Pending JPH08223507A (en) | 1995-02-20 | 1995-02-20 | Video signal amplitude limit circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08223507A (en) |
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