KR20030042492A - Clock buffer circuit with clock tunning function - Google Patents

Abstract

PURPOSE: A clock buffer circuit having a clock tuning scheme is provided to tune easily a clock signal by generating slowly or rapidly an output clock signal in response to an input clock signal. CONSTITUTION: A clock path includes the first to the third inverters(INV11-INV13) connected between an input clock signal and an output clock signal in order to transmit the input clock signal. The first portion is connected with the clock path in order to output slowly a phase of the input clock signal in response to the first control signal. The first circuit portion is formed with the first and the second delay circuits(110,120). The second portion is connected with the clock path in order to output rapidly the phase of the input clock signal in response to the second control signal. The second circuit portion is formed with the first and the second stack inverters(INV14,INV15). A control circuit(130) generates the first and the second control signals.

Description

Clock buffer circuit with clock tuning function {CLOCK BUFFER CIRCUIT WITH CLOCK TUNNING FUNCTION}

TECHNICAL FIELD The present invention relates to semiconductor integrated circuit devices and, more particularly, to a clock buffer circuit having a clock tunning scheme that allows a clock signal to be adjusted quickly or slowly.

In the case of a semiconductor memory device, for example Rambus DRAM, the data output timing window (tQ) and the data output timing window (tSH) are delay lock loops. Should be ideally centered. Due to factors such as process, voltage and temperature variations (called PVT variations) and package offsets, it is difficult to center data output timing and data input timing at the wafer level. With this in mind, at design time, there should be an option circuit that can tune the clock signal through the resistor / fuse circuit instead of the metal correction.

1 is a circuit diagram illustrating a clock buffer circuit according to the prior art. Referring to FIG. 1, the clock buffer circuit 10 generates an output clock signal tclk in response to an input clock signal tclkdrv90, and the output clock signal tclk is a synchronization signal of a data output driver (not shown). Will be supplied as. The clock buffer circuit 10 includes three inverters INV1, INV2, and INV3 connected in series between the input and output clock signals tclkdrv90 and tclk. The clock buffer circuit 10 further includes first and second delay circuits. The first delay circuit 12 is connected to the input terminal of the inverter INV2, that is, the first node ND1, and the second delay circuit 14 is connected to the input terminal of the inverter INV3, that is, the second node ND2. Is connected to.

The first delay circuit 12 is composed of two NMOS transistors MN1 and MN2 and one MOS capacitor C1. The NMOS transistor MN1 is controlled by the control signal mn0, and the NMOS transistor MN2 is controlled by the control signal mn1. The MOS capacitor C1 is connected to the first node ND1 through the NMOS transistors MN1 and MN2 and is supplied with voltages of the control signals mn1 and mn1b. The second delay circuit 14 is composed of two NMOS transistors MN3 and MN4 and one MOS capacitor C2. The NMOS transistor MN3 is controlled by the control signal mn0, and the NMOS transistor MN4 is controlled by the control signal mn1. The MOS capacitor C2 is connected to the second node ND2 through the NMOS transistors MN3 and MN4 and is supplied with voltages of the control signals mn1 and mn1b. The first and second delay circuits 12, 14 generate control signals mn0, mn1, mn1b in response to the tuning signals mT0, mT1 (not shown in the figure, but provided from a fuse / register). Controlled by the selection circuit 16. The selection circuit 16 consists of connected inverters INV4, INV5, INV6, INV7 as shown.

The clock buffer circuit described above can be adjusted, for example, ± 90 ps in the direction in which the clock signal tclkdrv90 delays the phase by adding the junction capacitance of the transistor or the gate capacitance of the transistor on the path of the clock signal. For example, when the tuning signal mT0 is activated, the junction capacitance of the transistor is added to the first and second nodes ND1 and ND2, and as a result, the phase of the input clock signal tclkdrv90 is slowed. When the tuning signal mT1 is activated, not only the junction capacitance of the transistor but also the gate capacitance of the transistor is added to the first and second nodes ND1, ND2, resulting in a slower phase of the clock signal.

As described above, the clock signal is output late from the reference time by adding extra parasitic capacitance on the clock path using the tuning signals from the fuse circuit. However, the clock buffer circuit according to the prior art does not include a function of pushing and pulling a clock signal, and as a result, clock tuning is not easy. That is, the clock signal is adjusted only in either direction.

It is an object of the present invention to provide a clock buffer circuit that allows clock signals to be tuned in both directions.

1 is a circuit diagram showing a clock buffer circuit according to the prior art;

2 is a circuit diagram showing a clock buffer circuit according to a preferred embodiment of the present invention;

3A and 3B are circuit diagrams showing a preferred embodiment of the inverters INV14, INV15 shown in FIG. 2; And

4 is a circuit diagram showing a preferred embodiment of the selection circuit shown in FIG.

Explanation of symbols on the main parts of the drawings

10, 100: clock buffer circuit 12, 14, 110, 120: delay circuit

16, 130: selection circuit

According to a feature of the present invention for achieving the above object, there is provided a semiconductor device including a clock buffer circuit for generating an output clock signal in response to an input clock signal. The semiconductor device includes a clock path for transmitting the input clock signal; First means coupled to the clock path, the first means for slowing the phase of the input clock signal in response to first control signals; Second means coupled to the clock path and configured to speed up the phase of the input clock signal in response to second control signals; And a control circuit for generating said first and second control signals to operate either one of said first means and said second means in response to tuning signals and a selection signal.

In this embodiment, the clock path includes first to third inverters connected in series between the input clock signal and the output clock signal.

In this embodiment, the first means is connected to a first node between the first and second inverters, the first means providing extra capacitance to the first node in response to the first control signals. A delay circuit; And a second delay circuit coupled to a second node between the second and third inverters and providing an extra capacitance to the second node in response to the first control signals.

In this embodiment, the selection signal indicates whether the phase of the input clock signal is pushed or pulled relative to the reference clock signal.

In this embodiment, the second means comprises: a first stack inverter connected in parallel to both ends of the first inverter and operating in response to the second control signals; And a second stack inverter connected in parallel to both ends of the second inverter and operating in response to the second control signals.

In this embodiment, the tuning signals are generated using one fuse.

Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

2 is a circuit diagram illustrating a clock buffer circuit according to the present invention.

Referring to FIG. 2, the clock buffer circuit 100 of the present invention includes three inverters INV11, INV12, and INV13 connected in series between an input clock signal tclkdrv90 and an output clock signal tclk. The first delay circuit 110 is connected to the input terminal of the inverter INV12, that is, the first node ND10, and the second delay circuit 120 is connected to the input terminal of the inverter INV13, that is, the second node ND11. Is connected.

The first delay circuit 110 is composed of two NMOS transistors MN11 and MN12 and one MOS capacitor C11. The NMOS transistor MN11 is controlled by the control signal mn0, and the NMOS transistor MN12 is controlled by the control signal mn1. The MOS capacitor C11 is connected to the first node ND1 through the NMOS transistors MN11 and MN12 and is supplied with voltages of the control signals mn1 and mn1b. The second delay circuit 120 is composed of two NMOS transistors MN13 and MN14 and one MOS capacitor C12. The NMOS transistor MN13 is controlled by the control signal mn0, and the NMOS transistor MN14 is controlled by the control signal mn1. The MOS capacitor C12 is connected to the second node ND2 through the NMOS transistors MN13 and MN14 and is supplied with voltages of the control signals mn1 and mn1b.

The first and second delay circuits 110 and 120 described above are controlled by the control signals mn0, mn1, and mn1b output from the selection circuit 130, and the input clock signal is output late with respect to the reference clock. To be.

2, the clock buffer circuit 100 according to the present invention further includes inverters INV14 and INV15. Inverter INV14 is connected in parallel to both ends of inverter INV11, and inverter INV15 is connected in parallel to both ends of inverter INV12. The inverter INV14 is controlled by the control signals load0 and load0b from the selection circuit 130 and allows the delay of the first node ND10 to be reduced. That is, the inverter INV14 charges and discharges the first node ND10 in response to the input signal tclkdrv90 together with the inverter INV11, and as a result, the input signal is quickly output with respect to the reference clock. The inverter INV15 is controlled by the control signals load1 and load1b from the selection circuit 130. The inverter INV15 is controlled by the control signals load1 and load1b from the selection circuit 130, The delay of the second node ND11 is reduced. That is, the inverter INV15 charges and discharges the second node ND11 in response to the signal on the first node ND10 together with the inverter INV12, so that the signal on the first node ND10 is driven with respect to the reference clock. Outputs quickly.

Preferred embodiments of inverters INV14 and INV15 are shown in FIGS. 3A and 3B, respectively. As shown in the figure, each inverter consists of a stack inverter and is controlled by corresponding control signals. Each inverter operates when the corresponding control signals load0, load0b / (load1, load1b) are activated.

2, the selection circuit 130 controls the control signals load0, load0b, load1, load1b, mn0, mn1, mn0b, mn1b in response to the tuning signals mT0 and mT1 and the selection signal sel. Will occur). The select signal sel is a signal for causing the clock signal to be output quickly or slowly with respect to the reference clock. Tuning signals mT0 and mT1 are generated using one fuse or resistor, although not shown in the figure. A preferred embodiment of the selection circuit 130 is shown in FIG. The selection circuit 130 according to the present invention is composed of a plurality of transmission gates TG1-TG4, a plurality of inverters INV16-INV24, and a plurality of NMOS transistors MN19-MN26, as shown in FIG. 4. It is connected as shown.

When the select signal sel is at the low level, the paths of the transfer gates TG1 and TG3 are blocked and the paths of the transfer gates TG2 and TG4 are formed. In this case, the selection circuit 130 outputs the control signals mn0, mn0b, mn1, and mn1b according to the tuning signals mT0 and mT1. This causes the first and second delay circuits 110 and 120 of the clock buffer circuit 100 to operate, so that the input clock signal tclkdrv90 is output slowly relative to the reference clock. That is, when the select signal sel is at the low level, the input clock signal is pushed back. When the select signal sel is at the high level, paths of the transfer gates TG1 and TG3 are formed and paths of the transfer gates TG2 and TG4 are blocked. In this case, the selection circuit 130 outputs the control signals load0, load0b, load1, and load1b according to the tuning signals mT0 and mT1. This causes the inverters INV14 and INV15 of the clock buffer circuit 100 to operate, so that the input clock signal tclkdrv90 is quickly output with respect to the reference clock. That is, when the select signal sel is at the high level, the input clock signal is pulled forward.

In the above, the configuration and operation of the circuit according to the present invention has been shown in accordance with the above description and drawings, but this is only an example, and various changes and modifications can be made without departing from the spirit and scope of the present invention. Of course.

As described above, it is easy to tune the clock signal by allowing the input clock signal to be pushed and pulled without metal correction.

Claims (7)

A semiconductor device comprising a clock buffer circuit for generating an output clock signal in response to an input clock signal: A clock path for transmitting the input clock signal; First means coupled to the clock path, the first means for slowing the phase of the input clock signal in response to first control signals; Second means coupled to the clock path and configured to speed up the phase of the input clock signal in response to second control signals; And And a control circuit for generating said first and second control signals to operate either one of said first means and said second means in response to tuning signals and a selection signal. The method of claim 1, And the clock path includes first to third inverters connected in series between the input clock signal and the output clock signal. The method of claim 2, The first means A first delay circuit coupled to a first node between the first and second inverters and providing an extra capacitance to the first node in response to the first control signals; And And a second delay circuit connected to a second node between the second and third inverters, the second delay circuit providing extra capacitance to the second node in response to the first control signals. . The method of claim 2, And the selection signal indicates whether the phase of the input clock signal is pushed or pulled with respect to a reference clock signal. The method of claim 2, The second means A first stack inverter connected in parallel to both ends of the first inverter and operating in response to the second control signals; And And a second stack inverter connected in parallel to both ends of the second inverter and operating in response to the second control signals. The method of claim 1, And the tuning signals are generated using one fuse. The method of claim 1, And the tuning signals are generated using one register.