KR101180392B1 - Data Output circuit of Semiconductor Memory Apparatus - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data output circuit of a semiconductor memory device, and more particularly, to a rising clock signal, a falling clock signal, and a predriver on / off generated during data output of a semiconductor memory device operating at a high speed. The present invention relates to a data output circuit of a semiconductor memory device for improving a malfunction of a predriver due to a difference in a flight time between signals for driving.

The data output circuit of the semiconductor memory device according to the present invention receives a data output signal generated by the data output signal generating means, a rising clock signal generated by the rising clock signal generating means and a falling clock signal generated by the falling clock signal generating means. And a predriver controller for generating a predriver control signal for driving the predriver.

According to the present invention, there is an advantage that a stable operation of the predriver in the chip can be realized from the low frequency to the ultra high frequency.

Predriver, Rising Clock Signal, Polling Clock Signal

Description

Data output circuit of semiconductor memory device

1 is a block diagram of a data output circuit of a general semiconductor memory device;

FIG. 2 is a circuit diagram of the predriver shown in FIG. 1;

3 is a timing diagram for describing an operation of the predriver shown in FIGS. 1 and 2;

4 is a block diagram of a data output circuit of a semiconductor memory device according to the present invention;

5 is a detailed circuit diagram of the predriver control unit and the predriver shown in FIG. 4;

FIG. 6 is a timing diagram for describing an operation of the data output circuit of FIG. 4.

Description of the Related Art [0002]

100: data output signal generating means 200: rising clock signal generating means

300: polling clock signal generation means 510: predriver
520: predriver control unit 600: clock signal generation means

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BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data output circuit of a semiconductor memory device, and more particularly, to a rising clock signal, a falling clock signal, and a predriver on / off generated during data output of a semiconductor memory device operating at a high speed. The present invention relates to a data output circuit of a semiconductor memory device for improving a malfunction of a predriver due to a difference in flight time between signals for driving a.

In general, data input / output operations of synchronous dynamic RAM (SDRAM) are performed in synchronization with the rising edge of the clock. However, the data input / output operation in DDR SDRAM (Double Data Rate SDRAM) is performed in synchronization with the falling edge as well as the rising edge of the clock by using internal DLL (Delay Locked Loop) circuit, thus double the data input / output speed compared to SDRAM. Has Therefore, a high speed semiconductor memory device such as DDR SDRAM generates a rising clock and a falling clock for data output during read operation, processes data, and generates and uses a data output signal instructing data output.

Hereinafter, a data output circuit according to the related art will be described with reference to FIGS. 1 and 2.

1 is a block diagram of a data output circuit of a general semiconductor memory device.

The data output circuit shown in FIG. 1 enables data output signal generation means 100 for generating a data output signal dout instructing the operation of the predriver 410, and is synchronized with the rising edge of the clock for driving the data. A rising clock signal generating means 200 for generating a rising clock signal rclk and a falling clock signal generating means 300 for generating a falling clock signal fclk enabled in synchronization with a falling edge of a clock for driving data. And a plurality of data output means 400 for receiving the data output signal dout, the rising clock signal rclk, and the falling clock signal fclk to process and output the data.

Here, the data output means 400 receives the data output signal dout, the rising clock signal rclk, and the falling clock signal fclk when data is input, and the rising edge time and the falling edge time of the clock. And a predriver 410 for performing the data read operation and an output driver 420 for driving and outputting the data output from the predriver 410.

When the data output signal dout is enabled by the data output signal generating means 100 and input to the predriver 410, the predriver 410 starts a data read operation and the rising clock signal rclk and the rising clock signal rclk. Data is received at each time when the polling clock signal fclk is enabled. The data is then stored and transferred to the output driver 420 so that the data is finally read from the outside of the semiconductor memory device.

FIG. 2 is a circuit diagram of the predriver shown in FIG. 1.

As shown in FIG. 1, the data output signal generating means 100 generates the data output signal dout, the rising clock signal generating means 200 generates the rising clock signal rclk, and the falling clock. The polling clock signal fclk is generated by the signal generating unit 300 and transmitted to the predriver 410. When the data output signal dout is in the low level state, the PMOS transistor 413-1 is turned on to transfer an external supply power supply VDD to the common node N1, and the output of the predriver 410 is in a high level state. The PMOS transistor 413-1 is turned off when the pre-driver 410 is disabled and the data output signal dout is in a high level state, so that the common node N1 of the external power supply VDD is fixed. When the rising clock signal rclk is enabled and outputs the rising data rdata when the rising clock signal rclk is enabled, the common node N1 is turned off, and the falling data is polled data when the falling clock signal fclk is enabled. It is a structure that outputs (fdata). As described above, the general predriver includes the data output signal dout and the rising clock signal rclk from the data output signal generating means 100, the rising clock generating means 200, and the falling clock generating means 300. ) And the polling clock signal fclk, and a flight time between the data output signal dout and the rising clock signal rclk or the data output signal dout and the polling clock signal fclk. If a difference in flight time occurs, the control of the predriver becomes difficult. In low frequency operation, it is possible to adjust the timing by applying delay to each signal. However, when operating in a high frequency high speed memory, the timing of disabling the data output signal dout and the falling clock signal fclk is exactly matched. Since it is difficult, a problem occurs when the predriver 410 is driven.

FIG. 3 is a timing diagram for explaining the operation of the predriver shown in FIGS. 1 and 2 by using 8-bit data output as an example.

As shown in FIG. 3, when the data output signal dout is disabled before the polling clock signal fclk (A), the predriver 410 outputs the polled clock signal fclk. The last polling data (fdata) is not output.

The present invention has been made to solve the above problems, and includes a pre-driver controller using the rising clock signal (rclk) and polling clock signal (fclk) and the data output signal (dout) generated for data output by There is a technical problem to provide a data output circuit capable of stably controlling the data output signal (dout) by preventing malfunction due to the difference in flight time between each signal.

The data output circuit of the semiconductor memory device according to the present invention for achieving the above technical problem, the data output signal generated by the data output signal generating means, the rising clock signal and the falling clock signal generating means generated by the rising clock signal generating means And a predriver controller for generating a predriver control signal for driving the predriver by receiving the polling clock signal generated by the.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

4 is a block diagram of a data output circuit of a semiconductor memory device according to the present invention.

As illustrated, the data output circuit of the semiconductor memory device includes a predriver controller 520 and a predriver 510.
The predriver control unit 520 is configured to invert a signal output signal dout generated by the data output signal generating unit 100 and a rising signal rclkb and polling of the rising clock signal rclk generated by the clock signal generating unit 600. The predriver control signal Pre_ctrl for driving the predriver 510 is generated by receiving the inverted signal fclkb of the clock signal fclk.
The predriver 510 transmits an external supply power VDD to the common node N2 when the predriver control signal Pre_ctrl is disabled, and the external supply power when the predriver control signal Pre_ctrl is enabled. A switching unit 513 for blocking supply of the VDD to the common node N2; When the clock driving the data is the rising edge and the falling edge, the data input unit inputs the rising data rdata and the falling data fdata by the rising clock signal rclk and the falling clock signal fclk, respectively. 515; And a latch unit 517 for storing, driving, and outputting a signal or data transmitted to the common node N2.

Here, the predriver control signal Pre_ctrl inputs the data output signal dout, the rising clock inversion signal rclkb and the falling clock inversion signal fclkb output from the data output signal generating means 100. The signal is generated by the predriver control unit 520 to instruct the operation of the predriver 510. The predriver control signal Pre_ctrl is enabled before the rising clock signal rclk, and is disabled in synchronization with the falling clock signal fclk being disabled while the data output signal dout is disabled. Able to be. In addition, the rising clock signal rclk reaches a signal enabled in synchronization with a rising edge of a clock driving data, and the falling clock signal fclk is enabled in synchronization with a falling edge of a clock driving data. Leads to The rising data rdata is data input to the predriver 510 at the time of enabling the rising clock signal rclk and the polling data fdata is at the time of enabling the falling clock signal fclk. Data input to the predriver 510.

The operation of the data output circuit of the semiconductor memory device configured as described above will be described with reference to the detailed configuration diagram of FIG. 5.

FIG. 5 is a detailed circuit diagram of the predriver control unit 520 and the predriver 510 of the present invention shown in FIG. 4.

The predriver control unit 520 generates an inverter 520-1 for inverting the data output signal dout generated by the data output signal generating unit 100 and the rising clock signal generating unit 200. The inverted signal rclkb of the rising clock signal rclk and the inverted signal fclkb of the polling clock signal fclk generated by the polling clock signal generating means 300 are input, and each value is a high level. In this case, the NAND gate 520-3 outputting the low level signal, the inverter 520-5 inverting the output signal, and the signals inverted by the two inverters 520-1 and 520-5 are high level. And a NAND gate 520-7 for outputting a low level signal.

The switching unit 513 receives the predriver control signal Pre_ctrl at a gate terminal, an external supply power VDD at a source terminal, and a drain terminal thereof connected to the common node N2. It consists of 1). When the predriver control signal Pre_ctrl is enabled, the predriver control signal Pre_ctrl has a high level to block supply of the external power supply VDD to the common node N2.

The data input unit 515 transfers the rising data rdata and the falling data fdata to the common node N2 when the rising clock signal rclk and the falling clock signal fclk are enabled. A first passgate 515-1 and a second passgate 515-3 are formed. The latch unit 517 receives the signals and data inverted by the first inverter 517-1 and the first inverter 517-1 as input signals and data of the common node. And a third inverter 517-5 which inverts the signal and data inverted by the first inverter 517-1, and inverts and outputs the signal and data.

When the predriver control signal Pre_ctrl is enabled, the predriver 510 may be in a floating state when the common node N2 is in a floating state. The predriver 510 may rise by the rising clock signal rclk and the falling clock signal fclk. Data rdata and the polling data fdata are received, and when disabled, the external power supply VDD is applied to fix the output driver.

The predriver control signal Pre_ctrl is generated by using the data output signal dout, the rising clock inversion signal rclkb, and the falling clock inversion signal fclkb as input signals, and thus the predriver control signal Pre_ctrl. The timing at which is disabled may exactly match the time at which the polling clock signal fclk is disabled. Thus, stable operation of the data output predriver of the semiconductor memory device may be realized.

 6 is a timing diagram for explaining the operation of the data output circuit of the semiconductor memory device according to the present invention.

As illustrated in FIG. 6, the predriver control signal Pre_ctrl input to the PMOS transistor 513-1 is enabled at the time when the data output signal dout is enabled, thereby allowing the rising clock to rise. Enabled before signal rclk. When the data output signal dout input to the predrive controller 520 is enabled, the predriver control signal Pre_ctrl is always enabled, the data output signal dout is disabled, and the last The predriver control signal Pre_ctrl is also disabled at the timing D at which the polling clock signal fclk is to be disabled. When the last polling clock signal fclk is disabled (D), the predriver control signal Pre_ctrl is also disabled (D), so that the conventional data output signal dout is earlier than the polling clock signal fclk. The last polling data, which is not output when disabled, may be output using the predriver control signal Pre_ctrl.

The pre-driver controller 520 configured by the above-described method suppresses the malfunction of the predriver due to the difference in the flight time of the internal control signal generated during the high speed operation, thereby realizing accurate data output.

Thus, those skilled in the art will appreciate that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

The present invention is to suppress the malfunction of the predriver due to the difference in the flight time of the internal control signal generated during the high-speed operation, the effect of improving the data output driver operation characteristics by accurately controlling the predriver operation Entails.

Claims (9)

A predriver controller configured to receive a data output signal generated by the data output signal generator, a rising clock signal generated by the rising clock signal generator, and a falling clock signal generated by the falling clock signal generator to generate a predriver control signal; And And a predriver driven in response to the predriver control signal. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, The predriver control unit disables the predriver control signal before the rising clock signal and disables the predriver control signal in synchronization with the falling clock signal being disabled while the data output signal is disabled. And a data output circuit of the semiconductor memory device. Claim 3 has been abandoned due to the setting registration fee. The method of claim 1, The predriver transmits an external supply power supply (VDD) to a common node when the predriver control signal is disabled, and blocks supply of the external supply power supply (VDD) to the common node when the predriver control signal is enabled. And a switching unit to the data output circuit of the semiconductor memory device. Claim 4 has been abandoned due to the setting registration fee. The method of claim 3, And the predriver comprises a data input unit configured to transfer the rising data and the falling data to the common node when the rising clock signal and the falling clock signal are enabled. Claim 5 was abandoned upon payment of a set-up fee. The method according to claim 3 or 4, The predriver further includes a latch unit configured to store and output a signal or data transmitted to the common node. Claim 6 has been abandoned due to the setting registration fee. The method of claim 1, The predriver controller may include a first inverter for receiving the data output signal and inverting the first output signal, a first NAND gate receiving the rising clock signal and the falling clock signal, a second inverter for inverting the same, and the first inverter and the second inverter. And a second NAND gate for inputting an inverter. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 3, The switching unit includes a PMOS transistor in which the predriver control signal is input to a gate terminal, an external supply power supply (VDD) is applied to a source terminal, and a drain terminal is connected to the common node. Circuit. Claim 8 was abandoned when the registration fee was paid. 5. The method of claim 4, The data input unit may include: a first passgate configured to transfer the rising data to the common node by inputting the rising clock signal and the inverted signal of the rising clock when the rising clock signal and the falling clock signal are enabled; And a second pass gate for transmitting the polling data to the common node by inputting a polling clock signal and an inverted signal of the polling clock. Claim 9 has been abandoned due to the setting registration fee. 6. The method of claim 5, The latch unit includes a first inverter for inputting a signal of the common node and a second inverter for inputting an inverted signal caused by the first inverter to the common node as an input. .

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