KR20030038208A - Control appliance and method for one PLL using Dedicated Short Range Communication Protocol - Google Patents

Abstract

PURPOSE: An apparatus for controlling a single PLL using dedicated short range communication protocol and a method therefor are provided to transmit and receive data with the single PLL. CONSTITUTION: A CPU(201) writes data and operation basic information of a PLL(Phase Locked Loop) module at a DPRAM(205). An FPGA(Field Programmable Logic Array)(203) reads the PLL data for preliminarily operating transmitting and receiving switching order, and controls PLL locking data transmission and a transmitting/receiving switch within each guard time of a frame. An RF module(207) has a single PLL module, and transmits and receives short range wireless data by a control signal of the FPGA(203).

Description

Control unit and method for one PLL using Dedicated Short Range Communication Protocol

The present invention provides a short range wireless communication in a short range wireless communication base station of an intelligent transportation system, in particular, when implementing a wireless communication base station or a terminal, a short range wireless communication that enables short range wireless communication regardless of transmission / reception and heterogeneous PLL modules. A single PLL controller and method using a protocol are described.

ITS (Intelligent Transport System) is a new transportation system that improves the mobility, stability, efficiency and the traffic environment by integrating the existing transportation system with advanced technologies such as information communication, electronics, control, and computers. It is aimed at reducing congestion, reducing traffic accidents, expanding the use of public transportation, and reducing logistics costs.

The new Dedicated Short Range Communication (DSRC) introduced to provide such intelligent transportation system service is a communication system composed of a near-field wireless communication base station (roadside device) and a vehicle terminal (vehicle on-vehicle device) located on the roadside.

The short-range wireless communication is a small output device that supports the TDMA / TDD scheme of the 5.8GHz band with a communication distance of 100M or less and a transmission speed of 1Mbps, and includes not only an automatic toll collection system (ETC) service but also a traffic information and control system. It accommodates ITS services.

The high frequency device of the conventional short range wireless communication base station is as shown in FIG.

Referring to FIG. 1, a tuner unit 102 for transmitting / receiving short-range wireless data with a vehicle terminal through an antenna 101, and converting a received high frequency signal into an intermediate frequency by a local oscillation signal and demodulating received data. A receiving unit 111, a transmitting unit 123 for modulating the transmission data into a local oscillating signal and outputting to the tuner unit 102 at 5.8 GHz frequency, and a localizing unit for transmitting and receiving local oscillating signals according to the transmission and reception modes. It consists of an oscillation part 131.

In addition, the tuner unit 103 generates a high frequency switch 105 which is switched to a transmission or reception path by the control unit 129 according to a transmission or reception mode, and low noise of the reception frequency (5.8 GHz) of the high frequency switch 105. A low noise amplifier (LNA) 107 for amplifying and a power amplifier 109 for power amplifying a transmission signal to the high frequency switch 105 are provided.

In addition, the receiver 111 includes a first bandpass filter 113 for bandpass filtering the output of the low noise amplifier 107 and a frequency converter for mixing the bandpass filtered frequency with a local oscillation signal and outputting the intermediate frequency at an intermediate frequency. 115, a second band pass filter 117 for filtering the frequency-converted signal into a signal of an intermediate frequency band, an intermediate frequency amplifier 119 for amplifying the intermediate frequency signal, and the intermediate frequency amplifier 119 And a demodulator 121 for demodulating the signal amplified by.

In addition, the transmitter 123 includes an ASK modulator 125 for ASK-modulating the transmission data into a local oscillation signal, and a third bandpass filter 127 for filtering the ASK-modulated signal into a short range radio frequency band (about 5.8 GHz). It consists of.

The local oscillator 131 includes a transmission frequency generation module 133 and a reception frequency generation module 143 operating according to transmission and reception modes, and a temperature for generating a PLL reference frequency in the transmission and reception frequency modules 133 and 143. Compensation crystal oscillators 135 and 145, PLL modules 137 and 147, fourth and fifth band pass filters 139 and 149, and driving amplifiers 141 and 151.

The high frequency device of the conventional short-range wireless communication base station as described above will be described with reference to FIG. 1.

First, in the reception mode, the control unit 129 switches the high frequency switch 105 of the tuner unit 103 to the reception path a. In this case, the frequency received through the antenna 101 is low noise amplified by the low noise amplifier 107 via the high frequency switch 105.

The output frequency of the low noise amplifier 107 is filtered by the first band pass filter 113 of the receiver 111 to a frequency of 5.8 GHz, mixed with the local oscillation signal by the frequency converter 115, and converted into an intermediate frequency. The second band pass filter 117 filters the intermediate frequency band. The intermediate frequency amplifier 119 performs intermediate frequency amplification, and the demodulator 121 demodulates the received data Rx data from the intermediate frequency and outputs the demodulated data.

Referring to the operation of the reception frequency generating module 133 of the local oscillator 131 at this time, the temperature compensated crystal oscillator (TCXO) 135 generates a PLL reference frequency, and the PLL module 137 operates by the PLL reference frequency. And generates a received local oscillation signal, and the received local oscillation signal is filtered by a fourth band pass filter 139 into a predetermined band (5.87 GHz) and then driven through the drive amplifier 141 to the frequency converter 115. By being outputted, short-range wireless data is received.

On the other hand, in the transmission mode, the control unit 129 switches the high frequency switch 105 to the transmission path b. At this time, the transmission data (Tx Data) is modulated into a local oscillation signal by the ASK (Amplitude Sequence Keying) modulator 125 of the transmitter 123, and the modulated transmission frequency is a predetermined band (by the third band pass filter 127). 5.8 GHz) is filtered, and the filtered signal is amplified to a predetermined level by the power amplifier 109 of the tuner unit 109 and then transmitted to the antenna 105 via the high frequency switch 105.

When the transmission frequency generating module 143 of the local oscillator 131 operates, the temperature compensated crystal oscillator (TCXO) 145 generates a PLL reference frequency, and the PLL module 147 operates by the PLL reference frequency. Generates a local received oscillation signal, and the received local oscillated signal is filtered to a predetermined band (5.8 GHz) by the fourth band pass filter 149 to the ASK modulator 123 through a driving amplifier 151. By outputting, short-range wireless data is transmitted.

Referring to the operation of the control unit 129 for the control of the high frequency device, conventionally, each of the phase locked loop (PLL) modules 137 and 147 for transmission and reception, and each of the transmission and reception at system initialization after the power is turned on The PLL data is transmitted to the PLL modules 137 and 147 for frequency locking. When the transmission / reception frequency locking is completed during system initialization, only the transmission / reception path switch is changed during transmission / reception switching without performing frequency locking.

However, in the related art, since the two PLL modules 137 and 147 are used for transmission and reception, respectively, the size of the RF modules 137 and 147 increases and the price competitiveness with other products is weak.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and the short-range wireless communication protocol enables a single PLL module to be applied to a high frequency module to effectively control transmission / reception locking switching and transmission / reception switch switching within a guard time. It is an object of the present invention to provide a single PLL module controller and method.

Using the short-range wireless communication protocol, the lock data operation result of the PLL module is stored in memory at system initialization, read from the program logic device, and then transferred to the high-frequency module to control the switching operation according to the transmission / reception mode. Its purpose is to provide a single PLL module control and method.

In addition, the program logic device analyzes the frame message control slot to recognize whether the next channel is transmitted / received, the order and time of each guard time, and then performs PLL data and transmit / receive switch control. It is an object of the present invention to provide a single PLL control apparatus and method using a communication protocol.

In addition, even if the PLL module is replaced in the central processing unit, the software can be changed without replacing the hardware, and the actual logic control of the high frequency module is performed in the program logic device, thereby reducing the load sharing of the central processing unit and enabling effective high frequency module design. A single PLL control apparatus and method using a short range wireless communication protocol.

1 is a block diagram of a high frequency device of a conventional short-range wireless communication.

2 is a block diagram showing a single PLL module control device using a short range wireless communication protocol according to an embodiment of the present invention.

3 is a memory mapping diagram according to an embodiment of the present invention.

4 is a detailed block diagram of a high frequency device of short-range wireless communication according to an embodiment of the present invention.

5 is a PLL control timing diagram in a roadside base station in short-range wireless communication according to an embodiment of the present invention.

6 is a frame control slot configuration of short-range wireless communication.

7 is a configuration diagram of a connection slot for short-range wireless communication.

<Explanation of symbols for the main parts of the drawings>

Central processing unit 203 Program logic device

Memory 207 High-frequency module

313 Tuner section 215 High frequency switch

217 Low noise amplifier

221 ... receiver 223 ... first band pass filter

225 frequency converter 227 second band pass filter

229 Medium frequency amplifier 231 Demodulator

233 Transmitter 235 ASK Modulator

237 Third Band Pass Filter 239 Local Oscillator

241 Temperature Compensated Crystal Oscillator 243 PLL Module

245 4th Bandpass Filter 247 Drive Amplifier

249 ... output switch

In order to achieve the above object, a single PLL module control apparatus using a short range wireless communication protocol according to the present invention,

A central processing unit for writing data of the PLL module into a memory;

A program logic device that reads the PLL data recorded in the memory, precomputes a transmit / receive switching order, and then controls PLL locking data transmission and transmission / reception switches within respective guard times in the frame;

And a high frequency module having a single PLL module and transmitting / receiving short-range wireless data according to a transmission and reception mode by a control signal of the program logic device.

Preferably, the memory includes a PLL module control register group region, a PLL module data region, a command_register region, each of which has a channel transmit / receive direction indication register and each PLL module characteristic display register value recorded therein to accommodate various PLL modules. And a transmission data area and a reception data area.

Preferably, the PLL module data is set in an R-counter, an R-counter corresponding to an upper value determined internally by the sum of various variables when the frequency portion is set to a desired frequency in consideration of the operation of each PLL module. Then, the N-counter corresponding to the remaining lower value, and the function latch data corresponding to the data value that determines the time the PLL stays in the high gain mode to quickly fix the PLL to the desired frequency.

Preferably, the program logic device detects whether or not a frame control message slot having an SCI field containing control information every frame through analysis, whether or not each guard time sequence and time information is detected, and then guards within each slot time. It is characterized by transmitting the transmission PLL data or the reception PLL data and the transmission / reception switch control signal to the high frequency module in advance within the guard time in accordance with the next slot transmission / reception at time.

Preferably, the high frequency module comprises: a tuner unit comprising a high frequency switch switched to a transmission / reception path according to a switch control signal of a program logic device, a low noise amplifier on a reception path, and a power amplifier on a transmission path;

A receiver converting the received high frequency signal into an intermediate frequency by a local oscillation signal and demodulating the received high frequency signal;

A transmitter which modulates the transmission data by the local oscillation signal in the transmission mode, and outputs the short-range radio frequency band to the tuner unit;

Oscillator to generate PLL reference frequency on single path, single PLL module to generate local oscillation signal by PLL data, output bandpass filter to filter local oscillation signal output from PLL module, drive amplifier, transmit / receive And a local oscillator comprising an output switch switched to output a local oscillation signal to a transmitter or a receiver by a switch control signal.

In a method of controlling a single PLL module using a short range wireless communication protocol according to another embodiment of the present invention, a central processing unit sets PLL data corresponding to PLL module characteristics before initialization of a program logic device to transmit and receive a single PLL module of a high frequency module. Recording a result value calculated in accordance with the corresponding high frequency in a memory;

The program logic device reads the recorded PLL data value and then calculates the transmission / reception switching order in one frame in advance, taking into account the stable time required by the high frequency module in each guard time in the frame, and transmitting / receiving the PLL locking data. Performing control;

And transmitting / receiving data by the high-frequency module through short-range wireless communication due to the operation of a single PLL module according to the PLL locking data and the transmit / receive switch control signal, and due to switching of the transmit / receive switch. .

Hereinafter, with reference to the accompanying drawings as follows.

2 is a block diagram illustrating a single PLL module control apparatus using a short range wireless communication protocol according to an embodiment of the present invention, FIG. 3 is a memory mapping diagram according to an embodiment of the present invention, and FIG. 4 is a short range according to an embodiment of the present invention. 5 is a detailed configuration diagram of a high frequency device of wireless communication, FIG. 5 is a PLL control timing diagram of a roadside base station in a short range wireless communication according to an embodiment of the present invention, FIG. 6 is a frame control slot configuration diagram of a short range wireless communication, 7 is a block diagram illustrating a connection slot of short-range wireless communication.

Referring to FIG. 2, a central processing unit (CPU) 201 for recording data and basic operation information of a PLL module in a memory (DPRAM) 205 and PLL data recorded in the memory 205 are read and transmitted. Field Programmable Logic Array (FPGA) 203 for controlling PLL locking data transmission and transmission / reception switches within each guard time in a frame after pre-calculating the reception switching order, and a single PLL module 243. And a high frequency (RF) module 207 for transmitting / receiving short-range wireless data by a control signal of the program logic device 203.

As shown in FIG. 4, the high frequency module 207 includes a tuner unit 213, a receiver 221 and a transmitter 233, and a local oscillator 239 having a single PLL module 243. .

The local oscillator 239 may convert a local oscillation signal generated according to the temperature compensation crystal oscillator 241, the PLL module 243, the bandpass filter 245, the driving amplifier 247, and the transmission / reception mode. 225 and an output switch 249 for selectively switching output to the ASK modulator 235.

The apparatus and method for controlling a single PLL module using the short range wireless communication protocol as described above will be described with reference to the accompanying drawings.

2 to 4, since the high frequency module 207 performs short-range wireless communication using a single PLL module 243, a PLL data signal (PLL control) and a single PLL module 243 may be used. The high frequency switch 215 and the output switch 249 should be controlled by a transmit / receive transfer signal (Rx / Tx switch).

Here, three items should be taken into consideration for the settling time of the high frequency module 203. The first is a locking time of the PLL module of the high frequency module, and the second is a transmission / reception high frequency switch operation and a separation time. The third is PLL data transmission time.

In the first case, prior to securing the stability time considering the characteristics of the high frequency module within the guard time allowed by the DSRC protocol, priority is given. In the second case, in order to prevent high frequency oscillation at the Transient Interval when transmitting / receiving frequency, 5-10us separation time and the switch should be opened before transmitting / receiving the actual data. You just need to match one characteristic.

To this end, the central processing unit (CPU) 201 outputs a memory control signal (DPRAM Control) to the memory 205, so that the PLL data (N) corresponding to the individual characteristics of the PLL module before initialization of the program logic device 203 (N). The PLL internal register data values are written into the memory (DPRAM) 205 by computing the values of Counter, R-Counter, and Function-Latch Data in software for the corresponding high frequency. This allows the PLL module to be locked within the guard time defined by the DSRC protocol, considering the characteristics of a single PLL module that is applied because there are many differences depending on the design of the high frequency module.

This is recorded in the PLL module data area in the memory mapping diagram of FIG. That is, even if the PLL module is replaced, the PLL data (R-counter, N-counter, Function-latch) value is calculated in advance when the unique operating characteristics or desired frequency values for each PLL module are changed. The value is written to the memory 205.

3 shows a PLL module control register group in a first region, a PLL module data in a second region, and a command register in a third region. command_register), the fourth region includes transmission data, and the fifth region includes reception data. In the PLL module control register group of the first region, each PLL module characteristic display register (PLL IC internal register size, PLL_spcc_register) characteristic value is recorded so as to accommodate a channel transmit / receive direction indication register (PLL_en_register) and various PLL modules. .

This PLL module data area is a part for setting the frequency and has an internal register. The internal register includes three values of upper value (R-Counter), lower value (N-Counter), and function latch (Function-Latch) data. There is. The role of upper value (R-Counter) internally determines the frequency part as the sum of various variables when setting to the desired frequency considering the operation of different PLL modules. The role of the counter is set to the upper value (R-counter) and then the remaining lower value, and the function of the function latch data is high gain to fast lock the PLL module to the desired frequency. In gain mode, you need to determine how long the PLL module will stay, which is the data value.

At that time, the PLL high value (PLL R counter) data, the function latch data of the PLL module, the low counter data (TX_PLL N counter Data) of the transmitting PLL module, and the high counter data of the receiving PLL module are stored in each memory area. RX_PLL N counter Data) is recorded. The internal registers of the three PLL modules are read by the program logic device (FPGA (or ASIC) 203) and transmitted to the PLL module provided in the high frequency module 207.

The channel transmit / receive direction indication register PLL_en_Reg may know the program logic device 203 itself by analyzing the frame control message slot (FCMS) itself in the DSRC protocol. In order to reduce such a calculation process, the central processing unit 201 calculates (PLL_en_Reg does not need to be used).

In order to effectively control the PLL module 243 and the transmit / receive switches 215 and 249 of the high frequency module 207 as described above, the central processing unit 201 controls the memory (DPRAM) 205 with a memory control signal (DPRAM CONTROL). Record PLL information. That is, the central processing unit 201 writes operation basic information on the control of the PLL module in the memory 205 even when the PLL module of the high frequency module 207 is replaced.

The program logic device 203 generates an interrupt signal to the central processing unit 201 to request information on a new frame, and the central processing unit 201 receiving the signal receives data for the next frame. Indicates that is written in the memory 205 by the data update signal Data_update.

At this time, the program logic device 203 reads the PLL data recorded in the memory 205, calculates the transmission / reception switching order in advance, and then switches the PLL locking data transmission and transmission / reception switch within each guard time in the frame. The controlling high frequency control signal RF_control is output to the high frequency module 207. That is, since the high frequency module 207 shares transmission / reception as one PLL module and transmits / receives short-range wireless communication data, PLL data and transmission / reception switch control are performed.

In addition, the program logic device 203 may perform various transmission and reception procedure changes within one frame in the short range wireless communication protocol, and consider the characteristics of the high frequency module 207 and sufficient locking time when transmitting and receiving short range wireless communication data. Transmit / receive mode switching operation must be completed within time. However, in the high frequency module using two PLL modules, locking does not occur when the system is initialized. However, in the case of one PLL module according to the present invention, transmission / reception locking switching and transmission / reception high frequency switch switching are performed within the minimum guard time in the DSRC standard (SPEC). Should be made stable.

The program logic device 203 receives a frame control message slot (FCMS), analyzes the SCI field in the slot, and knows the nature of the slot in the frame and whether or not to transmit or receive the PLL data. .

The frame control message slot has a structure as shown in FIG. 6, and is used to provide general information on channel usage from a roadside apparatus to a vehicle mounting apparatus, and is located at the front of the frame. This slot contains the communication profile and slot assignment information and is used exclusively for downlink (roadside equipment → vehicle loading equipment). In FIG. 6, SCI # i represents an i-th SCI field among slot control information (SCI) fields consecutive in a frame. t0 and t2 are guard times.

When the frame control message slot is received by the onboard device, the data content between SCI # 1 to SCI # 8 is analyzed in the internal structure of the frame control message slot, and thus a combination of transmission / reception slots can be expected in the frame. In other words, frame control message slots having SCI fields containing control information are analyzed for each frame to predict in advance how the remaining slot combinations in the frame are performed, how many seconds are transmitted, received, and MDS / ACT. Know the guard time and time. Through this information, the transmission PLL and the reception PLL data are transmitted to the PLL module in advance according to whether the next slot is transmitted or received at the guard time within each slot time.

Here, the message data slot (MDS) may be located behind a frame control slot or another message data slot and used for uplink (mounting device → roadside device) or downlink (roadside device → mounting device). This slot is used for message data exchange between roadside and payload units. One frame may include up to eight message data slots.

An access request slot (ACTS) is used by the payload device to request the roadside device to allocate a message data slot as shown in FIG. 7 and is used exclusively for uplink (mounting device → roadside device). A maximum of eight access request slots (48 access request channels) can be allocated to one frame.

As such, each PLL module must anticipate the locking time, specific slot transmission or reception in advance, set the characteristics of the PLL module early, and comply with the provisions of the Near Field Communication (DSRC) protocol. do. In view of the common satisfying conditions of these three conditions, the configuration of the slot combination in one frame can be predicted in advance when the frame control message slot (FCMS) is received. That is, after a few seconds, receive after a few seconds, you can see the order and time of each guard time (guard_time).

Then, at the guard time, the next slot is transmitted or received in advance. Therefore, the frequency setting data value (PLL IC operation) is considered in consideration of the stability time required by the PLL IC locking time programmatically within the guard time. Program logic device ASIC (FPGA) is transmitted to the high frequency module.

The operation of the high frequency module 209 will be described with reference to FIGS. 2 and 4 as follows.

The high frequency switch 215 of the tuner unit 213 and the output switch 249 of the local oscillator 239 are controlled by a switch control signal (Rx / Tx switch) of the program logic device 203 for near field communication with the vehicle terminal. It interlocks during the transfer operation to the corresponding path (a or b) according to the transmission or reception mode.

In addition, the program logic device 203 outputs PLL data (PLL Data, PLL Rx_LE, PLL Tx_LE) to a single PLL module 243 included in the local oscillator 239 according to a transmission or reception mode.

In the reception mode, the transmission signal of the vehicle terminal is received through the antenna 211, and the received high frequency signal is transmitted to the low noise amplifier 217 through the switching path a of the high frequency switch 210 of the tuner 215. The low noise is amplified and input to the receiver 221.

The first bandpass filter 223 of the receiver 221 bandpass filters the received high frequency signal into the 5.8 GHz band, and the frequency converter 225 mixes the filtered high frequency signal with the local oscillation frequency of the local oscillator 239. After converting the intermediate frequency, the second bandpass filter 227 filters only the intermediate frequency component from the signal converted by the frequency converter 225, is amplified by the intermediate frequency amplifier 229 and then through the demodulator 231. It is demodulated to received data (Rx Data; Manchaster coding Data).

In the transmission mode, the transmitter 233 modulates the digital data to be transmitted into a local oscillation signal generated by the local oscillator 239 by the ASK modulator 235, and then transmits the digital data to the third band pass filter 237. If only the 5.8 GHz band of the modulated frequency is bandpass filtered and then outputs the transmission data, the power amplifier 219 of the tuner unit 213 power amplifies the bandpass filtered frequency, so that the high frequency switch 215 It is sent to the antenna 211 through the path (b).

On the other hand, the local oscillator 239 generates a local oscillation signal for synchronizing with the transmission and reception signals of the transmission and reception units 221 and 233, respectively generating a transmission and reception local oscillation signal according to the transmission and reception mode on a single path. .

The local oscillator 239 includes a temperature compensated crystal oscillator (TCXO) 241, a phase lock loop (PLL) module 243, a fourth band pass filter (BPF) 245, a driving amplifier 247, and an output switch 249. It is composed of

The temperature compensated crystal oscillator 241 is a crystal application, and generates a reference frequency for operating the PLL, and the PLL module 243 compares the phase of the PLL reference frequency and the oscillation frequency and uses the difference to obtain a frequency. Find and output the desired transmit and receive frequencies respectively. The PLL module 242 generates a local oscillation frequency for time division duplex (TDD) communication in bidirectional communication.

At this time, the program logic device 203 temporarily guards the time required for changing the operating frequency (transmission and reception) (PLL locking time) within the stabilization time (30us or 40us) using the PLL data previously recorded in the memory 205. Implement to switch within time. That is, in the TDD scheme, frequency generation to different transmission and reception frequencies can be quickly changed by the fast locking time.

That is, the program logic device 203 may determine the PLL data values (R-counter, N-counter, Funcion-latch) that the central processing unit 201 previously recorded in the memory at the time of system initialization, depending on whether the next transmission or reception is performed at the guard time. , Tx_PLL N counter, Rx_PLL N counter), the PLL module 243 writes the transmission PLL data or the received PLL data to the PLL module 243 by serial communication at the correct transmission / reception moment. In this case, when the PLL data is transmitted during the guard time, the PLL module needs 30us or 40us stabilization time, and transmits it in advance considering the characteristics of the PLL module (locking data, locking time, PLL data transmission speed and time). .

In addition, the program logic device 203 receives the frame control message slot and predicts the configuration of the slot combination in one frame, so that the order and time of each guard time can be known. It outputs a control signal according to the characteristics of the switch.

Therefore, the PLL module 243 generates a receive or transmit local oscillation signal by the PLL data, and the generated local oscillation signal is filtered by the fourth band pass filter 245 into the transmit or receive local oscillation frequency band, After being amplified by the drive amplifier 247, the output signal is output to the selection path a or b of the output switch 249, and then output to the frequency converter 225 or the ASK modulator 235.

In addition, the PLL oscillation frequency control can be achieved by looping the oscillation frequency control based on the proper transmission of the PLL module operation information.

5 is a PLL control timing diagram of a roadside base station in short-range wireless communication according to an exemplary embodiment of the present invention.

Referring to FIG. 5, in the transmission mode, PLL data as shown in FIG. 5D is transmitted, and when PLL data is transmitted, FCMC data (FCMC = FCMS−) after a time interval (a) having a PLL locking time and a stabilization time. When the guard time is transmitted, and switching (Tx_on) to the high frequency switch and the output switch path (b) as shown in FIG. 5 (b), the transmission data as shown in FIG. 5 (a) is transmitted through the transmission path.

Again, the high frequency switch and the output switch 215, 249 are turned off after data transmission and the switch 215, 249 is turned on for the reception mode with the transmission / reception switching separation time from the time when it is turned off, and the PLL data before the reception data is received. The data is transmitted before the PLL locking time and the stabilization time in advance, thereby receiving the reception data MDC.

At this time, the time interval (a) in FIG. 5 is a sum of the PLL locking time and the stabilization time, which is a time in which a PLL value is set in advance to accurately receive or transmit high frequency data and reflects up to the time required for stabilization of the PLL module. The time interval (b) is a switch switching separation time. When switching the transmission and reception, if the time is not sufficiently separated, the frequency is changed, that is, when the transmission frequency is changed to the reception frequency and the reception frequency is changed to the transmission frequency. Vibration may occur, causing incorrect frequencies. This is the switch separation time so that such secondary propagation does not occur when changing frequencies in transmission or reception and vice versa.

In this manner, the transmission data ACKC is transmitted again, and the reception data ACTC is sequentially received. In this case, the PLL data transmission is transmitted in advance before receiving the transmission / reception data, and the switches 215 and 249 are switched with a transmission / reception switching interval for data reception.

Here, since the slot is composed of one or more channels and one or more guard times, it is formed as "FCMS = FCMC + guard time", and the message data slot (MDS) is composed of MDC + guard time + ACKC + guard time.

A message data channel (MDC) is a data area corresponding to a message in a message data slot, and an ACKC is a channel used for checking a message data slot. That is, the message data channel (MDC) is an acknowledgment channel that transmits the message data channel (MDC) back to the place where the message data channel is transmitted for confirmation. On the contrary, when the message data slot is transmitted, if the acknowledgment is needed, the reception of the access request slot (ACKC) is waited.

Therefore, the connection request slot (ACTS) is composed of six connection request slots (ACTC) and several guard times.

That is, in short-range wireless communication, the onboard device first requests a roadside device to allocate a message data slot (MDS) using an access request channel (ACTC) in order to access a communication link, and then requests a connection in a slotted ALOHA manner. By accessing the channel and succeeding. There are six connection request channels (windows) in one connection request slot. The window structure of the connection request slot (ACTS) is shown in FIG. 7, and a channel guard interval (t5 = guard time) is set between each window, and a channel guard interval is set after the last window. Here, accessing by the slot aloha method means that one channel is randomly selected from among 6 connection request channels and connected at random, and the terminal indicates the end of the last ACTC.

This means that the last channel (ACTC) in Figure 5 is the last slot (ACTC (6)) shown in FIG.

Meanwhile, in the present invention, the program logic device 207 serves as a coprocessor for the load sharing of the central processing unit 201. That is, the central processing unit 201 controls the high frequency module 207 in the program logic device 203 instead of performing the PLL data and the transmit / receive switch control of the high frequency module 207. Therefore, the central processing unit 201 performs only the basic information on the PLL module and writes it to the memory 205 even when the PLL module is replaced to support the high frequency module that transmits and receives a single PLL module.

Therefore, the program logic device 203 reads the lock data operation result value of the memory 205, and then calculates the transmission / reception switching order in one frame in advance, so as to obtain the stable time required by the high frequency module in each guard time time in the frame. Consider PLL locking data transmission and transmit / receive switch control at the right moment. The transmit / receive switch control is not the PLL module part of the high frequency module, but is controlled in consideration of the characteristics of the high frequency transmit / receive switch.

As described above, according to the apparatus and method for controlling a single PLL module using a short range wireless communication protocol according to the present invention, it is possible to transmit / receive with a single PLL module when implementing a roadside base station or a terminal of an intelligent transportation system. The size and cost of high frequency module can be reduced.

In addition, even if any PLL module is applied to a high frequency module, by updating the characteristic information of the PLL module, there is an effect of enabling short-range wireless communication through a single PLL module and switch control without changing hardware.

Claims (7)

A central processing unit for writing data of the PLL module into a memory (DPRAM); A program logic device that reads the PLL data recorded in the memory, precomputes a transmit / receive switching order, and then controls PLL locking data transmission and transmission / reception switches within respective guard times in the frame; And a high frequency module having a single PLL module and transmitting / receiving short range wireless data according to a transmission and reception mode by a control signal of the program logic device. The method of claim 1, The memory includes a PLL module control register group area, a PLL module data area, a command register (command_register) area, and a transmit data area, in which a channel transmit / receive direction indication register and respective PLL module characteristic display register values are recorded to accommodate various PLL modules. And a receiving data area, comprising: a single PLL controller using a short range wireless communication protocol. The method according to claim 1 or 2, When the PLL module data is set to a desired frequency in consideration of the operation of each PLL module, the PLL module data is internally set at an R-counter and an R-counter corresponding to an upper value determined by the sum of various variables. N-counter corresponding to the lower value, and using the short-range wireless communication protocol characterized in that it includes the function latch data corresponding to the data value to determine the time the PLL stays in the high gain mode to quickly fix the PLL to the desired frequency Single PLL Control. The method of claim 2, The program logic device analyzes a frame control message slot having an SCI field carrying control information every frame to detect transmission / reception, order of each guard time and time information, and transmit the next slot at the guard time within each slot time. A single PLL control device using a short range wireless communication protocol characterized by transmitting a transmission PLL data or a reception PLL data and a transmission / reception switch control signal to a high frequency module in advance within a guard time depending on whether or not reception is performed. The method of claim 1, The high frequency module includes: a tuner unit including a high frequency switch switched to a transmission / reception path according to a switch control signal of a program logic device, a low noise amplifier on a reception path, and a power amplifier on a transmission path; A receiver converting the received high frequency signal into an intermediate frequency by a local oscillation signal and demodulating the received high frequency signal; A transmitter which modulates the transmission data by the local oscillation signal in the transmission mode and outputs the short-range radio frequency band to the tuner unit; Oscillator to generate PLL reference frequency on single path, single PLL module to generate local oscillation signal by PLL data, output bandpass filter to filter local oscillation signal output from PLL module, drive amplifier, transmit / receive A single PLL control device using a short range wireless communication protocol comprising a local oscillator comprising an output switch switched to output a local oscillation signal to a transmitter or a receiver by a switch control signal. A first processor for writing a variable data operation according to a single PLL module and a result thereof in a memory; And a second processor configured to read operation information about the recorded PLL module and perform data transmission control according to the timing and operation order of the PLL module and the transmit / receive switch of the high frequency module. Single PLL control used. Writing, in a memory, a result of calculating, by a central processing unit, PLL data corresponding to a PLL module characteristic to a corresponding high frequency before initialization of a program logic device for transmission and reception switching of a single PLL module of the high frequency module; The program logic device reads the recorded PLL data value and then precomputes the transmission / reception switching order in one frame, taking into account the stable time required by the high frequency module in each guard time in the frame, and transmitting / receiving the PLL locking data. Performing control; And transmitting / receiving data by the high-frequency module through short-range wireless communication due to the operation of a single PLL module according to the PLL locking data and the transmit / receive switch control signal, and due to switching of the transmit / receive switch. Single PLL Control Using Near Field Communication Protocol.