CN1223098C

CN1223098C - Device and method for controlling phase-locked loop module via short-range communication protocol

Info

Publication number: CN1223098C
Application number: CNB02124474XA
Authority: CN
Inventors: 李载珩
Original assignee: LG Electronics Inc
Current assignee: Novera Optics Korea Co Ltd
Priority date: 2001-11-09
Filing date: 2002-06-28
Publication date: 2005-10-12
Anticipated expiration: 2022-06-28
Also published as: CN1417757A; KR100446238B1; KR20030038208A

Abstract

The invention discloses a device and method for controlling phase-locked loop (PLL) module via dedicated short-range communication (DSRC) protocol. The method for controlling PLL module via DSRC protocol in the DSRC base station and the terminal of ITS includes the steps: A CPU, according to the corresponding radio frequency, counts PLL data value suitable for PLL module attribute before initializing a Programmable Logic device, and the value is recorded in the memorizer; the Programmable Logic device reads the recorded PLL data value for preliminarily operating transmitting and receiving switching order, transmits PLL lock data, and controls a transmitting/receiving switch based on the desired settle time for the module within each guard time of a frame; and based on the PLL lock data and the transmitting/receiving control signal, an operation of PLL module and a switch of the transmitting/receiving switch transmit and receive a transmitting/receiving data by an RF module in DSRC.

Description

Utilize the apparatus and method of dedicated short-range communication control phase-locked loop module

Technical field

The present invention relates to a kind of apparatus and method of utilizing Dedicated Short Range Communications, (DSRC) agreement control phase-locked loop (PLL) module, it can utilize PLL module transmission/reception data and carry out DSRC in the enforcement of DSRC base station or intelligent transportation system (ITS) terminal, and irrelevant with the PLL type of module.

Background technology

ITS is a kind of new transportation system, and it is by with advanced person's information technology and flexibility, fail safe, efficient and the traffic environment of communicating by letter, electronics, control and computer application improve transportation in the transportation system of routine.ITS can reduce traffic jam and traffic accident, convenient public transportation and reduction logistical costs.

For providing the ITS DSRC system that service proposes or implements to comprise: DSRC base station, roadside (roadside equipment) and car-mounted terminal (being installed on the equipment on the vehicle).

The DSRC system is a small-sized output equipment, and it supports 5.8GHz bandwidth TDMA/TDD, and communication distance is in 100M, and transmission speed is 1Mbps, and it is applied to electronic charging service, traffic-information service and the common ITS service of control system.

Fig. 1 has shown the radio-frequency unit that is applied to the DSRC base station.

With reference to Fig. 1, radio-frequency unit comprises tuned cell 103, be used for by antenna 101 to/from car-mounted terminal transmission/reception DSRC data; Receiving element 111 is used for according to oscillation signals according the radiofrequency signal that receives being converted to intermediate-freuqncy signal and data that demodulation received; Transmitting element 123, being used for the transmission data-modulated is oscillation signals according, and output 5.8GHz bandwidth frequency; And local oscillation unit 131, be used for oscillation signals according being exported to transmission and receiving

element

111 and 123 according to transmission/receiving mode.

Tuned cell 103 comprises: radio frequency switch 105, and control unit converts radio frequency switch 105 to transmission/reception path according to transmission/receiving mode; Low noise amplifier 107 is used for the receive frequency (5.8GHz) that low noise amplifies radio frequency switch 105; Power amplifier 109 is used for amplifying the transmission signal, and sends consequential signals to radio frequency switch 105.

Receiving element 111 comprises: first band pass filter 113 is used for the output signal of bandpass filtering from low noise amplifier 107; Frequency converter 115 is used for filtered frequency and oscillation signals according mixing, and the output intermediate-freuqncy signal; Second band pass filter 117, being used for the signal filtering through frequency inverted is the mf band signal; Intermediate frequency amplifier 119 is used to amplify intermediate-freuqncy signal; With demodulator 121, be used to separate menstruation regulating intermediate frequency amplifier 119 amplifying signals.

Transmitting element 123 comprises: amplitude shift key modulation device 125 is used for the transmission data-modulated is advanced oscillation signals according; And the 3rd band pass filter 127, being used for the signal filtering after the modulation is DSRC band signal (approximately 5.8GHz).

Local oscillation unit 131 has tranmitting frequency generation module 133 and the receive frequency generation module 143 according to the operation of transmission/receiving mode.Transmission/

receive frequency module

133 and 143 comprises respectively: temperature compensating

crystal oscillator

135 and 145 is used to produce the PLL reference frequency;

PLL module

137 and 147; The the 4th and the 5th

band pass filter

139 and 149; With

driving amplifier

141 and 151.

The following radio-frequency unit that the DSRC base station is described with reference to Fig. 1.

In the receiving mode of DSRC base station,, amplify by radio frequency switch 105 and by low-noise preamplifier 107 low noises by the frequency that antenna 101 receives when control unit 129 is converted to the radio frequency switch 105 of tuned cell 103 when receiving path.

The frequency of low noise amplifier 107 outputs is filtered into the 5.8GHz audio range frequency by first band pass filter 113 of receiving element 111, becomes intermediate frequency by frequency converter 115 and oscillation signals according mixing, and is filtered into Mid Frequency by second band pass filter 117.Therefore, final frequency is the intermediate frequency that is amplified by intermediate frequency amplifier 119, and is demodulated into Manchester coding reception data Rx Data by demodulator 121.

At this, the receive frequency generation module 133 of local oscillation unit 131 is described now.Temperature compensating crystal oscillator (TCXO) 135 produces the PLL reference frequency, according to PLL reference frequency operation PLL module 137, receives oscillation signals according to generate.Oscillation signals according is filtered into predetermined band (5.87GHz) by the logical filter 139 of the four-tape, and outputs to frequency converter 115 by driving amplifier 141, to receive the DSRC data.

On the other hand, in the sending mode of DSRC base station, control unit 129 is converted to transmission path with radio frequency switch 105.At this, send amplitude shift key modulation device 125 modulation that data Tx Data is sent out unit 123, and be filtered into predetermined band (5.87GHz) by the 3rd band pass filter 127, power amplifier 109 by tuned cell 103 is amplified to predetermined level, and sends to car-mounted terminal by radio frequency switch 105 and antenna 105.

In addition, the following describes the transmission frequency generation module 143 of local oscillation unit 131.Temperature compensating crystal oscillator (TCXO) 145 produces the PLL reference frequency, according to PLL reference frequency operation PLL module 147, receives oscillation signals according to produce.Oscillation signals according is filtered into predetermined band (5.87GHz) by four-tape bandpass filter 149, and outputs to the amplitude shift key modulation device 125 of transmitting element 123 by driving amplifier 151, thereby modulates the DSRC data.

In order to control radio-frequency unit, control unit 129 comprises

PLL module

137 and 147, is used for transmission/received signal, and sends the PLL data to

PLL module

137 and 147 respectively, the transmission when being used to power the back system initialization/receive frequency locking.When transmission/reception locking behind the system initialization finished, transmission/reception path switch was changed between transmission/receiving mode and be need not subsequently frequency lock.

Yet existing frequency equipment uses two

PLL modules

137 and 147, is used for transmission/reception, has therefore increased the size and the price of RF module.

Summary of the invention

Therefore; main purpose of the present invention provides a kind of apparatus and method of the DSRC of utilization agreement control PLL module; by with a PLL module application in radio-frequency module, can change according to transmission/receiving mode control transmissions/receive frequency locking efficiently and transmission/reception switch in guard time (guard time).

Another object of the present invention provides a kind of apparatus and method of the DSRC of utilization agreement control PLL module, it is by storing the locking data operation values of PLL module in memory when system initialization, from programmable logic device, read this value, and send it to radio-frequency module, thereby can be according to transmission/receiving mode control transformation

Another object of the present invention provides a kind of apparatus and method of the DSRC of utilization agreement control PLL module; it is by the control of analysis frame message in programmable logic device time slot; thereby in the order of the transmission/reception of discerning subsequent channel and guard time with after the time, conversion PLL data and control transmission/reception switch.

A further object of the present invention provides a kind of apparatus and method of the DSRC of utilization agreement control PLL module, when central processing unit computing PLL data value, it can change software and need not to change hardware, it makes programmable logic device can control radio-frequency module, thereby can reduce the load of central processing unit, and it can design radio-frequency module efficiently.

To achieve the above object, provide a kind of device of the DSRC of utilization agreement control PLL module, having comprised: central processing unit is used for the data in memory record PLL module; Programmable logic device is used at each frame guard time transmission PLL locking data, and controls transmission/reception switch, union transmission/reception conversion sequence behind the PLL module data of reading and recording in memory; And by the radio-frequency module that a PLL module constitutes, be used for according to from the control signal of programmable logic device in transmission/receiving mode transmission/reception DSRC data.

Memory comprises: PLL module controls registers group district, wherein writing down the value of channel transmission/receive direction display register and the value of PLL module attribute display register, to receive multiple PLL module; PLL module data district is wherein writing down the value of frequency configuration; The command register district; Send the data field; And reception data field.

The PLL module data comprises: setting up according to its operational attribute in the process of each PLL module with required frequency, when frequency by in when being decided to be a plurality of variable sum, corresponding to the R-counter of higher limit; After the R-counter is set up corresponding to the N-counter of remaining lower limit; And corresponding to be used under the high gain mode for PLL module quick lock in is determined the function latch data of the data value of the PLL module time of staying in required frequency.

Programmable logic device is analyzed the frame control message time slot with SCI field (it includes control information) in each frame; detect the order and the temporal information of transmission/reception and each guard time; and according to the transmission/reception of subsequent timeslot; in cycle, send transmission/reception PLL data and transmission/reception changeover control signal at the guard time of each time slot to radio-frequency module.

Radio-frequency module comprises: tuner unit, and it comprises according to being converted to the radio frequency switch of transmissions/reception path from the changeover control signal of programmable logic device, is in the low noise amplifier in the reception path and is in power amplifier in the transmission path; Receiving element is used for changing received RF signal into intermediate-freuqncy signal according to oscillation signals according, and the modulated medium frequency signal; Transmitting element is used for sending data according to oscillation signals according in the sending mode modulation, and the signal after tuner unit output modulation becomes the DSRC frequency range; And local oscillation unit, it has the oscillator that is used for producing the PLL reference frequency on a path, a PLL module that produces oscillation signals according according to the PLL data, be used for carry out the band pass filter of filtering from the oscillation signals according of PLL module, the driving amplifier that is used for the amplification filtering signal, and the output switch, change it and oscillation signals according is outputed to transmitting element or receiving element according to transmission/reception changeover control signal.

In order to reach other above-mentioned purpose, the invention provides a kind of method of utilizing dedicated short-range communication control phase-locked loop module, comprise the steps: before the programmable logic device initialization, to be suitable for the PLL data value of PLL module attribute according to corresponding radio frequency computing by central processing unit, end value is recorded in the memory, with the transmission/reception of PLL module of conversion radio-frequency module; In each frame guard time, read the PLL data value that is write down by programmable logic device, transmission/reception conversion order to a frame carries out computing in advance, sends the PLL locking data, and transmission/reception switch is controlled in required stabilization time at radio-frequency module; And according to PLL locking data and transmission/reception control signal, by the operation of PLL module and the conversion of transmission/reception switch, by the radio-frequency module transmission/reception transmission/reception data among the DSRC.

Description of drawings

By following detailed description, in conjunction with the accompanying drawings, can more be expressly understood purpose, the feature and advantage of the invention described above.In the accompanying drawing:

Fig. 1 is the block diagram that shows the radio-frequency unit of relevant DSRC base station;

Fig. 2 is the block diagram that shows according to the device that utilizes DSRC agreement control PLL module of the embodiment of the invention;

Fig. 3 is a memory map of the present invention;

Fig. 4 is the detailed structure view of demonstration according to the radio-frequency unit of the DSRC of the embodiment of the invention;

Fig. 5 is the sequential chart of demonstration according to the PLL control operation of the base station, roadside of DSRC of the present invention;

Fig. 6 is the structure chart that shows the frame control message time slot of DSRC; With

Fig. 7 is the structure chart that shows the access slot of DSRC.

Preferred embodiment describes in detail

Following with reference to description of drawings the preferred embodiments of the present invention.In the following description, identical label is represented components identical in different figure.The things that limits in specification, for example detailed structure of circuit and element are only with helping the deep the present invention of understanding.Therefore obviously, there is not the things of these qualifications can implement the present invention yet.In addition, do not describe known function or structure in detail, because they can make the present invention because unnecessary details and ambiguous.

Fig. 2 is the structure chart according to the device that utilizes DSRC agreement control PLL module of the embodiment of the invention, Fig. 3 is a memory map of the present invention, Fig. 4 is the detailed structure view according to the radio-frequency unit of the DSRC of the embodiment of the invention, Fig. 5 is the PLL control operation sequential chart according to the base station, roadside of DSRC of the present invention, Fig. 6 is the structure chart of the frame control message time slot of DSRC, and Fig. 7 is the structure chart of the access slot of DSRC.

As shown in Figure 2, utilize the device of DSRC agreement control PLL module to comprise: central processing unit 201 is used for data and basic operation information in memory (DPRAM) 205 record PLL modules; Programmable logic device (FPGA: field programmable logic array) 203, be used at each frame guard time transmission PLL locking data, and in the PLL data that write down by reading in the memory 205 and behind the computing transmission/reception conversion order, control transmission/reception switch; And radio-frequency module 207, constitute by PLL module 243, be used for according to control signal transmission/reception DSRC data from programmable logic device 203.

As shown in Figure 4, radio-frequency module 207 comprises: tuned cell 213; Receiving element 221; Transmitting element 233; With local oscillation unit 239 with a PLL module 243.

Local oscillation unit 239 comprises: temperature compensating crystal oscillator 241; PLL module 243; Band pass filter 245; Driving amplifier 247; With output switch 249, be used for according to transmission/receiving mode to frequency converter 225 and amplitude shift key modulation device 235 output oscillation signals according.

Explanation utilizes the apparatus and method of DSRC agreement control PLL module with reference to the accompanying drawings.

Still arrive Fig. 4 with reference to Fig. 2, because radio-frequency module 207 utilizes a PLL module 243 to carry out DSRC, so must control PLL module 243 according to PLL data-signal PLL, and, must under each pattern, control radio frequency switch 215 and output switch 249 according to transmission/reception switching signal Rx/Tx switch.

At this, for considering three factors the stabilization time of radio-frequency module 203; The locking time of PLL module, transmission/received RF handover operation and disengaging time and PLL data transmission period.

In first factor, most important, must in the guard time that the DSRC agreement guaranteed, consider the attribute of radio-frequency module 207 and obtain stabilization time.In second factor, need the disengaging time of 5 to 10 μ s prevent to send/conversion of receive frequency in instantaneous strength, and in data transmission/reception, must disconnect switch in advance.In the 3rd factor, need to consider the particular attribute of PLL module.

For this reason, central processing unit 201 is to memory 205 output storage control signal DPRAMControl, before programmable logic device 203 initialization, computing on software is suitable for PLL data value N-counter, R-counter and the function latch data of PLL module attribute according to corresponding radio frequency.Because the PLL module is subordinated to radio-frequency module, so in the guard time that the DSRC agreement is determined, carry out lock operation according to the attribute of PLL module.

It is recorded in the PLL module data district of memory map of Fig. 3.That is to say, even changed the PLL module, according to the peculiar operational attribute of PLL module and required frequency values, computing PLL module data value N-counter, R-counter and function latch data on software in advance, and PLL internal register value record in memory 205.

As shown in Figure 3, first district has PLL module controls registers group, and there is the PLL module data in second district, and there is command register in the 3rd district, and there are the transmission data in the 4th district, and there are the reception data in the 5th district.In order to receive various PLL modules, the property value separately (register size of PLL IC, PLL-spcc-register or the like) that channel is sent/receive display register PLL_en_register and PLL module attribute display register is recorded in the PLL module controls registers group in first district.

PLL module data district comprises the internal register that is used to be provided with frequency.The internal register of example comprises higher limit R-counter, lower limit N-counter and function latch data Function-Latch Data.When the operation according to different PLL modules was provided with required frequency, frequency was determined by a plurality of variable sums are inner.Higher limit R-counter is corresponding to the higher limit of frequency.Lower limit N-counter is to set up remaining lower limit behind the higher limit R-counter.Function latch data Function-Latch Data is the data value that is used for determining the PLL module time of staying in high gain mode, is used to use required fast frequency locking PLL module.

The last counter data PX_PLL N-counter data of the function latch data of PLL higher limit data PLL R-counter, PLL module, the following counter data TX_PLL N-counter data that sends the PLL module and reception PLL module is recorded in each memory area.Programmable logic device (FPGA or ASIC) 203 reads three internal registers of PLL module, sends to the PLL module of radio-frequency module 207 then.

In channel transmission/receive direction display register PLL_en_Reg, when DSRC protocal analysis frame control message time slot FCMS, programmable logic device 203 can be confirmed to send or receive.Central processing unit 201 is used to simplify procedures.

As mentioned above, for PLL module 243 and transmission/reception switch 215 and 249 of controlling radio-frequency module 207 effectively, central processing unit 201 is according to memory control signal DPRAMControl executive control operation, and in memory 205 record PLL information.That is to say that even changed the PLL module 243 of radio-frequency module 207, central processing unit 201 also can be recorded in the basic operation information of control PLL module in the memory 205.

The frame information that programmable logic device 203 will be looked for novelty to central processing unit 201 by generating interrupt signal.The central processing unit 201 that receives interrupt signal is by Data Update signal Data_update circular record frame data subsequently in memory 205.

At this moment; by the PLL data of reading and recording in memory 205; programmable logic device 203 computing transmission/reception conversion orders, and be used in each guard time, sending the radio-frequency (RF) control signal RFControl of PLL locking data and control transmission/reception switch to radio-frequency module 207 output.Just, radio-frequency module 207 uses a PLL module to carry out the transmission/reception of DSRC data, to send PLL data and control transmission/reception switch.

In a frame of DSRC agreement, programmable logic device 203 produces sizable transmission/reception to be changed.In the transmission/reception of DSRC data, consider the attribute and the sufficient locking time of radio-frequency module 207, programmable logic device 203 must finish the conversion of transmission/receiving mode in guard time.Under the situation of the common radio-frequency module that uses two PLL modules, owing to carry out lock operation at the initial phase of system, so it is not binding.Yet, use the radio-frequency module of a PLL module in the guard time of minimum, stably to carry out transmission/reception locking conversion and the conversion of transmission/received RF switch according to DSRC Spec.

In order to control the transmission/time of reception of PLL data, programmable logic device 203 received frame control messages time slot FCMS analyze time slot control information field SIC and confirm the transmission/reception of time slot attribute and frame in advance.

Frame control message time slot FCMS has structure shown in Figure 6, and is in the head of frame, is used to use the information from roadside equipment to provide conventional channel to mobile unit.Time slot comprises communication overview (profile) and time slot allocation information, and is exclusively used in down link (roadside equipment is to mobile unit).In Fig. 6, SCI#i represents i SCI field of the continuous SCI file of frame, and t0 and t2 represent guard time.

In frame control message time slot FCMS, header PR has the length of 16 bits and at first sends MSB, and frame alignment word FSW is used to extract frame synchronization, and communication channel control field SIG has the length of 16 bits and shows physical layer attributes.Roadside permanent plant identifier FID is represented by 8 bits, produces the value between 0 to 255 when the roadside equipment initialization.Frame structure identifier FSI represents the timeslot number behind the frame control message time slot FCMS, and the mobile unit that release timer identifier RLT definition inserts a link at least once inserts this link time before again.Service codes SC represents the application service and the initial method of corresponding roadside equipment.Time slot control identifier SCI comprises an eight bit byte time slot allocation control information son field and 4 eight bit byte link address son fields.

Mobile unit received frame control messages time slot FCMS is to operate.By analyzing the data content from SCI#1 to SCI#8 in the internal structure of frame control message time slot FCMS, can predict transmission/receiving slot frame combination.That is to say,, in each frame, analyze frame control message time slot FCMS, confirm each guard time and cycle thus with the SCI field that comprises control information in order to predict remaining time slots combination, transmission/time of reception and the message data time slot/activation of this frame.According to the information of prediction, consider the transmission/reception of time slot subsequently, in the guard time of each time slot, in advance transmission/reception PLL data are sent to the PLL module.

At this, message data time slot MDS is in the frame control time slot of up link (mobile unit is to roadside equipment) or down link (roadside equipment is to mobile unit) or the back of other message data time slot, and time slot is used for the data that exchange messages between roadside equipment and mobile unit.One frame comprises 8 message data time slots at most.

As shown in Figure 7, when mobile unit requires roadside equipment assignment messages data slot, activate time slot A CTS and be exclusively used in up link (mobile unit is to roadside equipment).Can distribute 8 to activate time slot (48 are activated channel) in one frame at most.

Therefore, in each PLL module,, preestablishing the attribute of PLL module, and observe the standard of DSRC agreement for fixed frequency and particular time-slot transmission/reception predict that be essential locking time.Suppose that three conditions are common adequate condition, can predict a time slot combination in the frame by received frame control information time slot FCMS.That is to say, can predict the order and the time of transmission/time of reception and each guard time.

Owing in guard time, confirmed the transmission/reception of subsequent timeslot; according to radio-frequency module in the guard time desired stabilization time (PLL IC locking time), programmable logic device ASIC or FPGA are to radio-frequency module transmission frequency setting data value (PLL IC operating data).

Following operation with reference to Fig. 2 and 4 explanation radio-frequency modules 209.

The radio frequency switch 215 of tuner unit 213 links to each other with the output switch 249 of local oscillation unit 239, and is the respective channels (a or b) under the transmission/receiving mode according to the changeover control signal Rx/Tx switch transition from the programmable logic device 203 of DSRC to car-mounted terminal.

Programmable logic device 203 is exported PLL data (PLL data, PLL Rx_LE and PLL Tx_LE) according to transmission/receiving mode to the PLL of local oscillation unit 239 module 243.

In receiving mode, by the transmission signal of antenna 211 reception car-mounted terminals, received RF signal is carried out the low noise amplification and is outputed to receiving element 221 by low noise amplifier 217 by the reception path (a) of the radio frequency switch 210 of tuner unit 215.

First band pass filter 223 of receiving element 221 is filtered into the 5.9GHz wave band to received RF signal, frequency converter 225 is with the radiofrequency signal of filtering and the local oscillation frequency mixing of local oscillation unit 239, and output intermediate-freuqncy signal, second band pass filter 227 is filtering intermediate frequency composition from the signal of frequency converter 225 conversion, intermediate frequency amplifier 229 amplifies this composition, and demodulator 231 is demodulated into it and receives data (Rx data: the Manchester coded data).

In sending mode, when transmitting element 233 utilizes amplitude shift key modulation device 235 to modulate digital signal into the oscillation signals according that produced by local oscillation unit 239,5.8GHz wave band by the modulated frequency of the 3rd band pass filter 237 bandpass filterings, and output sends data, the frequency of 219 pairs of bandpass filterings of power amplifier of tuned cell 213 is carried out power amplification, and the transmission road by radio frequency switch 215 sends the frequency of having amplified through (b) to antenna 211.

On the other hand, local oscillation unit 239 is according to transmission/receiving mode, for the transmission/received signal locking with transmission/receiving element 221 and 233 generates oscillation signals according on a path.

Local oscillation unit 239 comprises temperature compensating crystal oscillator (TCXO) 241, PLL module 243, the four-tape bandpass filters 245, driving amplifier 247 and output switch 249.

Temperature compensating crystal amplifier 241 is crystal application products, is used to operation PLL and produce reference frequency.PLL module 243 compares the phase place of the phase place of frequency of oscillation and PLL reference frequency, utilizes difference to detect frequency, exports required transmission/receive frequency.In two-way communication, PLL module 242 is that time division duplex (TDD) communication produces local oscillation frequency.

At this, programmable logic device 203 utilization is previously recorded in the PLL data in the memory 205, for changing (transmitting and receiving) instantaneous enforcement PLL locking time in guard time in the operating frequency of (30 or 40 μ s) internal conversion stabilization time.That is to say, under tdd mode since high speed locking time can be different transmission/receive frequencies with frequency shift apace.

Therefore; programmable logic device 203 passes through according to PLL data value (R-counter; the N-counter;, Function-Latch; Tx_PLL N Counter and Rx_PLL N Counter) accurate transmission/time of reception in serial communication; record sends the PLL data or receives the PLL data in PLL module 243, these PLL data values be by central processing unit 201 during system initialization, in guard time according to subsequently transmission or receiving mode record.At this moment, programmable logic controller (PLC) 203 sends the PLL data according to the corresponding PLL module attribute of (locking data, locking time and PLL data transmission speed and time) (just PLL module needs 30 still are the stabilization time of 40 μ s) in guard time.

In addition, the time slot combination that programmable logic device 203 comes predictive frame by received frame control messages time slot FCMS, to confirm the order and the time of guard time, thus, according to the property control transmission/reception switch and the output control signal of switch.

Therefore, PLL module 243 produces transmission/reception oscillation signals according according to the PLL data.Oscillation signals according is filtered into transmission/reception local oscillation frequency wave band by four-tape bandpass filter 245, and is amplified by driving amplifier 247, outputs to the path (a or b) of output switch 249, outputs to frequency converter 225 or amplitude shift key modulation device 235 again.

When PLL module operation information normal transmission, can control the PLL frequency of oscillation by loop.

Fig. 5 is the PLL control timing figure of the base station, roadside of DSRC among the present invention.

With reference to Fig. 5, in sending mode, when sending PLL data shown in Figure 5, after having the time interval of PLL locking time and stabilization time, send the FCMC data, when the radio frequency switch is converted to path shown in Figure 5 with the output switch, send transmission data shown in Figure 5 by transmission path.

After data send, turn-off radio frequency switch and output switch 215 and 249.For receiving mode, switch 215 and 249 transfers connection to from closing breakpoint behind transmission/reception conversion disengaging time.This receives before data in reception, particularly before PLL time and stabilization time, sends the PLL data, to receive this reception data M DC.

At this, the time interval among Fig. 5 (a) be PLL locking time and stabilization time sum, it preestablishes the PLL value and accurately sends/received RF data and time of having reflected stable PLL module.The time interval (b) is a switch conversion disengaging time.Sending change-over time and receiving under the situation that does not have fully to separate change-over time, on the contrary when transmission frequency change into receive frequency or, the vibration owing to radio frequency can produce harmful frequency.That is to say that the time interval (b) is to be used for preventing sending/the switch disengaging time of the additional electric wave of receive frequency conversion.

Acknowledgement channel ACKC sends in an identical manner, and then receives activation channel ACTC.Before receiving transmission/reception data, send the PLL data, switch 215 and 249 utilizes transmission/reception disengaging time to change, to receive data.

Time slot comprises at least one channel and at least one guard time (FCMS=FCMC+ guard time), and message data time slot MDS is made up of ' MDC+ guard time+ACKC+ guard time '.

Message data channel MDC is the data field corresponding to the message in the message data time slot, and acknowledgement channel ACKC is used for the acknowledge message data slot.That is to say that by the message data channel is returned to transmit leg, message data channel MDC confirms that data are normal receptions or unusual the reception.Opposite, when sending the message data time slot, need acknowledgement channel ACKC to confirm to receive.

Therefore, activate time slot A CTS and comprise that six are activated channel and a few guard time.

In DSRC, for the accessing communication link, the mobile unit utilization activates channel ACTC and requires roadside equipment assignment messages data slot, and activates channel with time slot ALOHA way access.One is activated time slot and comprises that six are activated channel (window).Fig. 7 has shown the window structure that activates time slot A CTS.Set the channel guard phase (t5=guard time) between window, the channel guard phase is set at after the last window.At this, time slot A LOHA method refers to selects six of activating in the channels to conduct interviews at random, and notify last activate channel ACTC the time finish in the axle notion.Last time slot A CTC (6) in the last channel ACTC presentation graphs 7 among Fig. 5.

On the other hand, programmable logic device 207 alleviates the load of central processing unit 201 as coprocessor.That is to say, the PLL data of central processing unit 201 not responsible transmission radio-frequency modules 207 and control transmission/reception switch, but programmable logic device 203 is responsible for control radio-frequency module 207.Thereby support radio-frequency module by the transmission/reception of a PLL module converts, central processing unit 201 writes down the basic operation information of PLL module in memory 205, even in the process of changing the PLL module.

Therefore; programmable logic device 203 reads the locking data operating value from memory 203; the conversion sequence of computing transmission/reception in advance sends the PLL locking data and controls transmission/reception switch according to radio-frequency module in the guard time of each frame 207 desired stabilization times in precise time.Transmission/reception switch is by the attribute of radio frequency transmission/reception switch, rather than controls by the PLL module of radio-frequency module.

As mentioned above, use base station, roadside that the apparatus and method of DSRC agreement control PLL module can be by being located at ITS or the PLL module transmission/reception data in the terminal, reduce the size and the price of radio-frequency module.

In addition, though various PLL module application are arranged, can need not to change hardware and the attribute information of PLL module is upgraded, to implement DSRC by single PLL module and conversion and control in radio-frequency module.

Though the present invention has been described with reference to a specific preferred embodiment, has those skilled in the art will appreciate that the various changes that under the prerequisite of the spirit and scope of the present invention that do not break away from claims and limited, can carry out on form and the details.

Claims

One kind to utilize Dedicated Short Range Communications, be the device of DSRC agreement control phase-locked loop pll module, comprising:

Central processing unit is used for data and basic operation information in the memory record PLL of the described device that links to each other with this central processing unit module;

Programmable logic device is used in each frame guard time transmission PLL locking data, and reading and recording in described memory the PLL module data and computing transmissions/reception conversion sequence after control the switching of transmission/reception; With

Radio-frequency module has a PLL module, is used for according to the control signal transmission/reception DSRC data under transmission/receiving mode from programmable logic device, and this radio-frequency module comprises:

Tuned cell comprises according to being converted to the radio frequency switch of transmissions/reception path from the switch-over control signal of programmable logic device, is in the low noise amplifier on the reception path and is in power amplifier on the transmission path;

Receiving element is used for changing received RF signal into intermediate-freuqncy signal according to oscillation signals according, and this intermediate-freuqncy signal of demodulation;

Transmitting element is used for sending data at sending mode according to oscillation signals according modulation, and modulation signal is outputed to described tuned cell becomes the DSRC frequency range; With

The local oscillation unit comprises: temperature compensating crystal oscillator is used for producing the PLL reference frequency on signal path; A PLL module is used for producing oscillation signals according according to the PLL data; Band pass filter is used for the oscillation signals according from the PLL module is carried out filtering; Driving amplifier is used to amplify the signal of filtering; With the output switch, change according to described control signal, thereby oscillation signals according is outputed to transmitting element or receiving element.
2. device according to claim 1 is characterized in that, described memory comprises: PLL module controls registers group district, wherein writing down the value of channel transmission/reception display register and PLL module attribute display register, to receive various PLL modules; PLL module data district is wherein writing down the value that is used for frequency configuration; The command register district; Send the data field; And reception data field.
3. device according to claim 1, it is characterized in that, described PLL module data comprises: according to the operational attribute of different PLL modules with the process of the described different PLL modules of required frequency configuration in when frequency is defined as a plurality of variable sum by inside, corresponding to the R-counter of higher limit; Set the N-counter of the remaining lower limit in back corresponding to the R-counter; And corresponding under high gain mode, being the function latch data of the data value that described PLL module quick lock in is used for determine the PLL module time of staying in required frequency.
4. device according to claim 2; it is characterized in that; programmable logic device is analyzed the frame control message time slot with the SCI field that has comprised control information in each frame; the order and the temporal information of prediction transmission/reception and each guard time; and, in the guard time of each time slot, send transmission/reception PLL data and transmission/reception switch-over control signal to described PLL module according to the transmission/reception of subsequent timeslot.
One kind to utilize Dedicated Short Range Communications, be the method that the DSRC agreement is controlled a phase-locked loop pll module, comprise the steps:

The PLL data value that before the programmable logic device initialization, is suitable for the PLL module attribute by central processing unit according to corresponding radio frequency computing, and in the memory that end value is recorded in central processing unit is connected, with the transmission/reception of PLL module of conversion radio-frequency module;

In each frame guard time, read the PLL data value that is write down by programmable logic device, the transmission of one frame of computing in advance/reception conversion sequence sends the PLL locking data, and controls the switching of transmission/reception in desired stabilization time at radio-frequency module; With

According to PLL locking data and transmission/reception control signal, utilize the conversion of the switching of the operation of PLL module and transmission/reception, by the radio-frequency module transmission/reception transmission/reception data among the DSRC from described programmable logic device.