KR20030032681A - Signature id circuit using a voltage detector in a semiconductor device - Google Patents

Abstract

PURPOSE: A semiconductor device with a signature ID circuit utilizing a voltage detector is provided to detect previously stored ID information using a signal ID circuit in a semiconductor device having a single power terminal. CONSTITUTION: A pull-up diode(D10) is connected between a pad(100) and a line voltage(VDD). A pull-down diode(D20) is connected between the pad(100) and a ground voltage(VSS). The semiconductor device further comprises a voltage detector(120) and a signature ID circuit(140). The voltage detector(120) supplies an operation voltage(VDET) of the signature ID circuit(140) for storing package information. The operation voltage(VDET) accords to an external line voltage during normal operation and has the ground voltage(VSS) in a test mode for detecting stored package information.

Description

SIGNATURE ID CIRCUIT USING A VOLTAGE DETECTOR IN A SEMICONDUCTOR DEVICE

The invention relates to semiconductor integrated circuits. More specifically, the present invention relates to an asynchronous semiconductor memory device including a signature ID circuit that can manage information related to a manufacturing process of semiconductor manufacturing.

The manufacturing method for manufacturing a semiconductor device usually consists of a very large number of processes. A typical method of manufacturing a semiconductor device will be briefly described below. First, a photolithography step, an etching step, a cleaning step, and the like are repeatedly performed on the surface of the wafer during the wafer processing process so that specific semiconductor chips are formed on the wafer. Next, a test for determining the good / bad of the individual chips formed on the wafer is performed using a probe device to obtain mapping data, which is sent to a wafer assembly process. First, during the wafer assembly process, the wafer is divided into individual dies in a dicing step. Next, a good die is picked up according to the mapping data and mounted on the lead frame in the bonding step. Then, in the wire bonding step, the lead-out terminal for the semiconductor chip and the connection electrode are connected through wire bonding. Then, in a packaging process, mold molding is performed on the semiconductor chip using a thermosetting resin and specific information is displayed on the surface of the package to complete the semiconductor device.

As described above, in order to complete a semiconductor device, a large number of complicated processes must be executed, and it is necessary to execute accurate information management regarding information on semiconductor products in individual processes. In the semiconductor manufacturing process of the prior art, since the main focus of the manufacturing method in the prior art is tailored to manufacturing a large number of semiconductor devices having the same specifications in order to take advantage of mass production, the information management for semiconductor devices distributed through the process is Relatively easy. That is, in the semiconductor manufacturing method of the prior art, semiconductor devices processed through the same manufacturing system are distributed as one lot unit through the process, and each lot is usually processed under the same conditions, so that information management is relatively easy.

However, in recent years, as semiconductor devices have become very widely used in general commodity and component fields, there is a market demand for multi-volume, small quantity production semiconductor devices such as application specific integrated circuit (ASIC) and system on silicon (SOS). Is rising. In quantitative terms, one wafer may sometimes ensure an amount sufficient to produce several types of semiconductor devices for a particular application. At the same time, as in the case of a large-capacity memory chip, there is a situation in which a product can be shipped as long as a part of the chip is good, and therefore, it is necessary to perform information management individually on each chip in a given wafer.

For this purpose, in the semiconductor manufacturing method of the prior art, the distribution of the semiconductor device through various processes, marking the ID information such as numbers and alphabet letters on the surface of the semiconductor chip on the semiconductor package or wafer sealed with resin. Is managed. However, the amount of information that can be recorded using alphabetic characters is limited. In addition, it is necessary to perform edge recognition processing when reading alphanumeric characters, which is difficult. This method adds the problem that the character is susceptible to contamination or damage.

An example of an ID circuit is U.S. Patent No. 6,259,270, entitled "Semiconductor Programmable Test Arrangement Such As An Antifuse ID Circuit Having Common Programming Switches."

1 shows a portion of a semiconductor memory device having a signature ID circuit according to the prior art. Referring to FIG. 1, diodes D1 and D2 are connected as protection circuits between pad 10 and first power supply voltage VDD and between pad 10 and ground voltage VSS, respectively. The signature ID circuit 20 is connected between the pad 10 and the second power supply voltage VDDQ. The signature ID circuit 20, as is well known, consists of diodes connected in series between the supply voltage and the pad and fuses connected across each of the diodes (see FIG. 4). As shown in FIG. 1, a power supply of a semiconductor memory device is divided into a first power supply voltage VDD and a second power supply voltage VDDQ.

When the chip information is checked using the signature ID circuit of the semiconductor device including the memory, the chip information may be detected by setting up specific conditions during the test. The normal device function should not be affected at all during the detection of information. Therefore, VDD is usually set to 0 V, and the measurement is performed by measuring the level determined by the number of diodes adjusted by fuse cutting by applying current to the pad 10. You will see the package information.

In the case of a semiconductor device having a single power source (or using a single power source), instead of the package information stored in the signature ID circuit, the threshold voltage level of the electrostatic (ESD) protection diode inserted for reliability is measured. That is, when VDD and VDDQ are connected to the same power line in FIG. 1, information of the signature ID circuit 20 may not be obtained by the ESD protection diode D1 connected to the pad 10. Therefore, in the case of a semiconductor memory device such as an asynchronous high speed SRAM using a single power supply or a non-separated power scheme, it is impossible to use the signature ID circuit for the reasons described above.

An object of the present invention is to provide a semiconductor device having a signature ID circuit capable of detecting previously stored ID information under a single power supply system.

1 shows a portion of a semiconductor memory device having a signature ID circuit according to the prior art;

2 illustrates a portion of a semiconductor memory device having a signature ID circuit in accordance with the present invention;

3 is a preferred embodiment of the signature ID circuit shown in FIG. 2;

4 is a preferred embodiment of the voltage detector shown in FIG. 2;

5 is a diagram illustrating an output waveform of the voltage detector of FIG. 4 according to a change of an external power supply voltage; And

6 and 7 illustrate detection currents according to fuse cutting conditions.

Explanation of symbols on the main parts of the drawings

100: pad 120: voltage detector

140: signature ID circuit

According to a feature of the present invention for achieving the above object, the semiconductor device comprises at least one pad; A signature ID circuit connected to the pad and configured to store ID information of the semiconductor device; And a voltage supply circuit for supplying a predetermined bias voltage to the signature ID circuit as an operating voltage in a normal operation mode, and supplying a ground voltage as the operating voltage in a test operation mode.

In this embodiment, the semiconductor device has a single power supply terminal.

In this embodiment, the voltage supply circuit comprises: a voltage divider for distributing a power voltage supplied through the single power terminal; A comparator for determining whether the output voltage of the voltage divider is lower than a predetermined reference voltage and outputting a detection signal as a result of the determination; And an output unit configured to output the bias voltage or the ground voltage as the operating voltage to the signature ID circuit in response to the detection signal.

In this embodiment, when the output voltage of the voltage divider is lower than the predetermined reference voltage, the voltage supply circuit outputs the bias voltage as the operating voltage.

In this embodiment, when the output voltage of the voltage divider is higher than the predetermined reference voltage, the voltage supply circuit outputs the ground voltage as the operating voltage.

In this embodiment, the device further includes an electrostatic discharge protection device connected between the pad and the power supply voltage supplied through the single power supply terminal.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described in detail with reference to the drawings.

The signature ID circuit according to the present invention can fundamentally solve various problems that may occur in a semiconductor device having a single power supply scheme (or no separate power supply) and using a CoSi process. That is, in implementing the signature ID circuit, package information may be measured by controlling an operating voltage supplied to the signature ID circuit (or by differentiating it from a device power supply). A block diagram showing a semiconductor device having a signature ID circuit of the present invention to achieve this is shown in FIG.

2, a pull-up diode D10 is connected between the pad 100 and a power supply voltage VDD, and a pull-down diode D20 is connected between the pad 100 and the ground voltage VSS. The semiconductor device according to the present invention further includes a voltage detector 120 and a signature ID circuit 140. The voltage detector 120 supplies an operating voltage VDET of the signature ID circuit 140 for storing package information. The operating voltage VDET moves along the external power voltage EXTVDD during normal operation. The test mode for detecting stored package information has a ground voltage (VSS).

A preferred embodiment of the voltage detector 120 shown in FIG. 2 is shown in FIG. 3. Referring to FIG. 3, the voltage detector 120 of the present invention utilizes the characteristics of a differential amplifier having one output terminal, and is connected to a plurality of PMOS transistors 200-203 and a plurality of NMOS as shown in the figure. It consists of transistors 204-207, resistors 208, 209, and a number of inverters 210, 211, 212. Resistors 208 and 209 distribute the power supply voltage VDD as a voltage divider. The plurality of PMOS transistors 200-203 and the plurality of NMOS transistors 204-207 form a differential amplifier, and the inverters 210, 211, 212 invert the output of the differential amplifier so that the signature ID circuit ( It outputs as the operation voltage of 140).

In the circuit operation, referring to Fig. 5, when the output voltage Vin1 of the voltage divider is lower than the reference voltage Vin2, the output Vout of the differential amplifier has almost ground voltage. Therefore, the voltage detector 120 outputs an operating voltage VDET moving along with the external power supply voltage EXTVDD. If the output voltage Vin1 of the voltage divider reaches (or is higher than) the reference voltage Vin2, the output Vout of the differential amplifier moves along with the external supply voltage. Therefore, the operating voltage VDET output from the voltage detector 120 becomes the ground voltage VSS.

Here, the time point at which the output voltage VDET of the voltage detector 120 becomes the ground voltage is a time point at which the reference voltage Vin2 and the division voltage Vin2 coincide, and adjust the reference voltage level or the resistors R1 of the voltage divider. , R2) can be optimized by adjusting the resistance ratio. In this case, it should be noted that the output voltage VDET of the voltage detector 120 should be the ground voltage at the supply voltage VDD which does not affect the normal function.

A preferred embodiment of the signature ID circuit 140 shown in FIG. 2 is shown in FIG. Referring to FIG. 4, the signature ID circuit 140 of the present invention is composed of a plurality of diode-connected NMOS transistors 220-225, a resistor 226, and a plurality of fuses 227-230. , As shown in the figure. It is obvious to those who have gained common knowledge in this field that package information is stored with and without fuses. The signature ID circuit 140 of the present invention is supplied with the output voltage VDET of the voltage detector 120, unlike that of the prior art, which output voltage VDET is the ground voltage in the test mode to detect the package information. Becomes At this time, the power supply voltage VDD will be maintained at the same voltage as or higher than the normal operation mode. Thus, the current applied to the pad 100 in the test mode does not flow through the pull-up diode but only through the path formed in the signature ID circuit 140, through the VDET terminal and the inverter 212 of the voltage detector 120. Will flow. 6 and 7 summarize currents that change depending on whether fuses are cut or not.

As can be seen from the foregoing description, in a semiconductor device having an unseparated power scheme (or a single power scheme) and having a pull-up diode as a protection circuit, by controlling the operating voltage supplied to the signature ID circuit according to the operation mode The signature ID circuit may be applied to a semiconductor device having a power system that is not separated.

In the above, the configuration and operation of the circuit according to the present invention has been shown in accordance with the above description and drawings, but this is only an example, and various changes and modifications can be made without departing from the spirit and scope of the present invention. Of course.

As described above, it is possible to use the signature ID circuit in a semiconductor device having a single power supply terminal among semiconductor devices employing a pull-up diode for electrostatic discharge protection used to improve electrostatic discharge. Therefore, the analysis using the chip information can greatly contribute to improving the reliability and productivity of the semiconductor device.

Claims (6)

At least one pad; A signature ID circuit connected to the pad and configured to store ID information of the semiconductor device; And And a voltage supply circuit for supplying a predetermined bias voltage to the signature ID circuit as an operating voltage in a normal operation mode, and supplying a ground voltage as the operating voltage in a test operation mode. The method of claim 1, And the semiconductor device has a single power supply terminal. The method of claim 2, The voltage supply circuit A voltage divider for distributing a power voltage supplied through the single power terminal; A comparator for determining whether the output voltage of the voltage divider is lower than a predetermined reference voltage and outputting a detection signal as a result of the determination; And And an output unit configured to output the bias voltage or the ground voltage as the operating voltage to the signature ID circuit in response to the detection signal. The method of claim 3, wherein And the voltage supply circuit outputs the bias voltage as the operating voltage when the output voltage of the voltage divider is lower than the predetermined reference voltage. The method of claim 3, wherein And when the output voltage of the voltage divider is higher than the predetermined reference voltage, the voltage supply circuit outputs the ground voltage as the operating voltage. The method of claim 1, And a static discharge protection device connected between the pad and a power supply voltage supplied through the single power supply terminal.