KR20030028293A - Boundary Scan Test System and Method for the Same - Google Patents

Abstract

PURPOSE: A boundary scan test system and a delay compensation method thereof are provided, which output data to a boundary scan test chip embedded in a board to check connection state of the chip, and sample data passing through the chip according to delay generated in the board or a cable. CONSTITUTION: A boundary scan test system comprises a main controller checking connection state of a boundary scan test chip by outputting a pattern signal synchronized to a clock signal with the chip and by analyzing the pattern signal passing through the chip. The main controller further includes a correction clock signal part which measures delay generated in the boundary scan test chip embedded in the board and in a signal line transmitting data to the chip and generates a corrected clock signal according to the delay.

Description

Boundary Scan Test System and Method for Correcting Delay

The present invention relates to a boundary scan test system and a delay correction method thereof, and more particularly, to a boundary scan test system and a delay correction method capable of correcting a delay occurring during a boundary scan test process of a chip mounted on a board.

Recently, a boundary scan test (BST) for checking a connection state of a chip mounted on a board has been widely used. The BST inputs data having a predetermined pattern such as '101010' to each pin of the chip having the BST structure to check the connection state of the chip mounted on the board, shifts the input data by one data, and then This test compares the data passing through the chip with a data pattern that should normally be output, such as the initial data pattern.

If the data passing through the chip is the same as the initial data pattern, there is no problem in the connection state of the chip, but if it is not the same, this means that the chip has a problem in the connection state. It can be seen that it was shorted in the process.

A BST chip having a structure capable of performing the BST is illustrated in FIG. 1, wherein the plurality of data input pins I1 to In and the data output pins O1 to On are the data of the predetermined pattern. Is connected to a flip-flop cell (F / F) configured to output and shift the data one by one, and then add five more pins (TMS, TDI, TDO, TCK, TRST) Are pins to which a signal for controlling the operation of the BST chip is input during each BST. Here, the TMS is a test mode select, the TDI is a test data input, the TDO is a test data output, the TCK is a clock, and the TRST is a test reset. It is a pin to which control signal related to reset) is input. In addition, the controller 1 controls the state of the BST chip according to the signals input through the five pins, and the logic unit 2 implements the function of the chip to test the connection state. That is, after implementing a general chip in the logic unit 2, the plurality of data input pins I1 to In, data output pins O1 to On, and five test access ports (hereinafter referred to as TAPs). TMS, TDI, TDO, TCK, TRST) and the controller 1 by implementing the periphery thereof, the general chip has a BST chip structure, and thus the connection state of the BST chip is changed to a computing device such as a PC. You can check Since the TRST is an additionally connected port, the BST may be performed using only four ports (TMS, TMI, TDO, and TCK) excluding the TRST port.

An example of performing BST using the above BST chip is as shown in FIG. 2. That is, the main controller 1 outputs the pattern signal TDO synchronized to the clock signal TCK to the BST chip 3 mounted on the board 2, and the pattern signal TDI passed through the chip 3. Analyze the connection status by comparing with the pattern signal that should be originally output.

However, when the main controller 1 and the BST chip 3 to be inspected are not mounted on one board 2 as described above, the delay on the cable between the main controller 1 and the board 2 ( Da1), a delay Da2 due to an element and a pattern such as a buffer existing between the board 2 and the chip 3, and a delay Db1 generated when a signal passes through the chip 3; The delay Db2 generated when the signal passing through the chip passes through elements and patterns, such as a buffer present on the board 2, and the signal passing through the board 2 are connected to the main controller 1. Due to the delay Db3 occurring on the cable until it is input to the TCK, the TCK signal period of the main controller 1 is affected. That is, even if the period of TCK ignores the setup time for the signal in the main controller 1, it should not be smaller than the total delay Dt (Dt = Da1 + Da2 + Db1 + Db2 + Db3). Therefore, the period of the TCK is limited by the Dt.

3A, 3B and 3C show waveforms for sampling the TDO in the existing main controller 1.

In FIG. 3A, when the data output to the chip 3 is detected at T1 of the TCK, the main controller 1 outputs the TDO signal output from the chip at T2, which is the next falling edge (hereinafter, referred to as FE). Sampling ie read it. In T3, Data 2 by T2 is read. Data 1 is delayed by Dt from T1, and the period of TCK is Ptck as shown. Wherein the Ptck is less than the Dt. However, if Dt increases to approximate Ptck as shown in FIG. 3B, the sampled data loses reliability. In addition, when Dt is larger than Ptck as shown in FIG. 3C, sampling is performed at T3, which is the FE after T2.

Therefore, there arises a problem that a situation in which BST cannot be performed properly occurs depending on the Dt value. In addition, in order to solve the above problems, the Dt value may be measured and taken into account during data sampling, but there is a problem in that it is cumbersome to calculate Dt manually as the chip to be inspected and the implemented inspection equipment change every time. .

In addition, when Ptck and Dt are similar as shown in FIG. 3B, since data 1 must be read but not read in T2, there is a meaningless case even if Dt is known.

The present invention has been made to solve the above-mentioned problems of the prior art, the object of which is to output the data to the chip to check the connection state of the boundary scan test chip mounted on the board and the data passed through the chip The present invention provides a boundary scan test system and a delay correction method for sampling data passing through the chip according to delays generated in the board and cable in the main controller to be analyzed.

1 is a block diagram showing a configuration of a general boundary scan test chip;

2 is a block diagram showing the configuration of a conventional boundary scan test system;

3A, 3B, and 3C are waveform diagrams showing waveforms occurring in a conventional boundary scan test system,

4 is a block diagram showing a part of a configuration of a boundary scan test system according to the present invention;

FIG. 5 is a waveform diagram illustrating waveforms when a delay is corrected during TDO sampling according to the operation of FIG. 4;

FIG. 6 is a waveform diagram illustrating a waveform generated in FIG. 4 such that a delay is corrected according to FIG. 5;

7 is a table illustrating values of waveforms output from the pattern analyzer according to the present invention according to FIG. 6.

<Explanation of symbols on main parts of the drawings>

10: delay unit 20: pattern analysis unit

30: delay signal selector D1 to Dn: delay element

F1 ~ Fn: D-Flip Flop

According to a feature of the boundary scan test system according to the present invention for solving the above problems, a chip supporting a boundary scan test function (hereinafter referred to as a boundary scan test chip) mounted on a board is applied to a clock signal. In a boundary scan test system comprising a main controller for outputting a synchronized pattern signal and analyzing the pattern signal passed through the chip to inspect the connection state of the boundary scan test chip, the main controller is mounted on the board And a correction clock signal unit for measuring a delay occurring on a signal line transmitting data to the boundary scan test chip and the boundary scan test chip and generating a clock signal corrected according to the measured delay. Boundary scan test system.

In addition, according to a feature of the delay correction method of the boundary scan test system according to the present invention, a first step of outputting a pattern signal synchronized to the clock signal to the chip to check the connection state of the boundary scan test chip mounted on the board And a second step of generating a plurality of delay clock signals by delaying the clock signal of the first step by a plurality of time intervals, and a corrected clock signal used to sense data output from the chip among the plurality of delay clock signals. The third step is to select.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As shown in Figure 4, the correction clock signal unit of the boundary scan test system according to the present invention is implemented in the main controller delay unit 10 for delaying the TCK of the main controller a plurality of time intervals, and the delay unit A pattern analyzer 20 analyzing the BST chip pass signal output from the main controller in synchronization with the plurality of delayed clock signals delayed by 10 and the delay unit according to an analysis result of the pattern analyzer 20. The delay signal selector 30 selects one of a plurality of delayed clock signals delayed at 10 as a correction clock signal.

Here, the delay unit 10 is composed of a plurality of delay elements (D1 ~ Dn) connected in series so that the TCK can be delayed at a plurality of time intervals, the degree of delay of the delay element is adjusted as necessary.

The pattern signal TDO, which is synchronized with the delay clock signal output from the output terminals of the plurality of delay elements D1 to Dn, and passes through the BST chip according to the delay clock signal, is output to the BST chip. The D-flip flops F1 to Fn of the pattern analyzing unit 20 to compare the high waveform signal may not be the same when the BST chip pass pattern signal is the same as the pattern signal output to the BST chip. In this case, a low waveform signal is output. Here, a set of low or high waveforms respectively output from the D-flip flop is Q [1 to N].

The delay signal selector 20 may select any one of the plurality of delay elements D1 to Dn according to a low or high waveform of the plurality of D-flip flops F1 to Fn output from the pattern analyzer 20. Recognizing whether the D-flip flop F1 to Fn outputs a high waveform signal according to a clock signal delayed at intervals, and accordingly, a plurality of outputs from the output terminals of the plurality of delay elements D1 to Dn. One of the delay clock signals is selected as the correction clock signal. In the present invention, a plurality of low / high waveforms output from the plurality of D-flip flops F1 to Fn are analyzed, and which D-flip flop outputs a high waveform, and the delay signal selector 20 The delay signal selector 20 selects the corrected clock signal according to the selection signal SELL by inputting the selection signal SELL.

5 shows a sampling of the TDO according to a corrected clock signal generated in accordance with the present invention. As shown, T2comp of the correction clock signal TCKcomp is delayed by Dcomp with respect to T2 of TCK. The conventional main controller samples according to the TCK shown in FIG. 5, but the boundary scan test system according to the present invention samples data 1 to T2comp and data 2 to T3comp. Therefore, the sampling can be performed smoothly despite the delay of the pattern signal passing through the BST chip.

In order to measure the delay according to the present invention, first, a component such as each BST chip mounted on a board is made in a pass mode, and then a signal input to the TDI of the BST chip is output as it is through the TDO of the BST chip. Be sure to The main controller may combine the TMS and the TDI input to the BST chip to switch the mode of the BST chip to the pass mode.

6 illustrates waveforms input and output to generate a corrected clock signal in a boundary scan test system according to the present invention.

In FIG. 6, TCK is a clock signal used to output a pattern signal from the main controller to the BST chip, TDO is a pattern signal passed through the BST chip input to the main controller, and Clear is a plurality of D-flips. It is a signal for clearing the D-flip flops F1 to Fn so that the pattern signal analysis can be performed on the flops F1 to Fn.

Here, each delay element and its number n are adjusted so that the sum of delays delayed in the plurality of delay elements D1 to Dn shown in FIG. 4 is greater than Dt. The outputs of the delay elements are connected in chains to their respective D flip-flops. The main controller clears all the outputs of the D-flip flop using the Clear signal, and then causes the TDO shown in FIG. 6 to be input to the D-flip flop. In this situation, if the delay of the delay element is 1/4 of Dt and the number n is 8, the delay clock signals TCK1 to 8 output to the first to eighth delay elements are as shown. In particular, FIG. 6 shows waveforms when the TDO is sampled at a rising edge (hereinafter referred to as RE).

7 shows waveforms of Q [1-8] output at the point of time P1.

Here, it can be seen that the TDO is sampled at the second REs of the TCK7 and TCK8 as Q7 and Q8 output the high waveform. That is, since Q7 and Q8 output high waveforms, it is considered appropriate to use TCK7 and TCK8 as correction clock signals. Accordingly, the boundary scan test system according to the present invention acquires Q1 to Q8 to determine the Q at which 'H' starts.

Information regarding the determined Q is input to the delay signal selection unit 30 as a selection signal SLEC. Accordingly, the delay signal selector selects one delay signal among the delay signals output from the plurality of delay elements D1 to Dn according to the Q value included in the selection signal SLEC, and the main controller selects the delay signal. Is used as a correction clock signal to sample the pattern signal that has passed through the BST chip.

In addition, the RE of the TCK6 at the time P2 in FIG. 6 coincides with the beginning of the data of the TDO. In this case, the TDO data may be sampled but may not be due to the lack of setup time of the D-flip-flop. That is, Q6 is unpredictable. In FIG. 7, Q7 was 'L', but may also be 'H'.

Therefore, in the boundary scan test system according to the present invention, the selection signal applied to the delay signal selection unit 30 is based on the next number of the Q number that starts 'H', that is, the one above the number. Accordingly, the ambiguity caused by the TCK6 will be solved, and the delay signal selector 30 will select TCK8 as the correction clock signal.

Let's look at the actual case.

Normally, if TCK is 10 MHz, the TCK period is 100 ms. If the delay element is written with an IC buffer of 10µs and the maximum Dt is 150µs, the circuit can be configured with n being about 16. As a delay element, an actual delay element may be used, but since each delay does not need to be accurate, a suitable IC buffer having a delay of about 1/4 or less of a TCK period can be used as a delay element.

If a higher clock signal is generated for the TCK generated by the main controller, and counted at the point of time when the TDO is changed during the TDO sampling, a method of determining a TDO sampling time during the actual BST operation is performed. Should be generated. For example, when the TCK is about 25 MHz, if the high-speed clock signal about four times is generated, a circuit operating at 100 MHz should be configured. Therefore, there is a problem that the implementation is complicated and expensive.

In the present invention, a device having a delay of about 10 [mu] s may be used. In general, an F series IC is suitable, which simplifies circuit implementation and reduces cost.

The boundary scan test system and the delay correction method of the present invention configured as described above do not have prior knowledge of the delay caused by the board and cables generated during the boundary scan test that can check the connection state of the chip mounted on the board. A chip mounted on a board and a controller inspecting the chip are generated by generating a delay clock signal that is delayed at multiple time intervals so that the TDO can be sampled effectively, and selecting one of them as a correction clock signal that is used during TDO sampling. Delays can be measured even when they are not mounted on the circuit board, while the delayed signal is compensated for by sampling and reading the pattern signal passing through the chip mounted on the board. There is an effect that can be prevented.

Claims (7)

The boundary scan is performed by outputting a pattern signal synchronized with a clock signal and analyzing a pattern signal passing through the chip with a chip supporting a boundary scan test function mounted on a board (hereinafter referred to as a boundary scan test chip). In the boundary scan test system comprising a main controller for checking the connection state of the test chip, The main controller measures a delay occurring on a boundary scan test chip mounted on the board and a signal line transmitting data to the boundary scan test chip, and a correction clock signal unit configured to generate a clock signal corrected according to the measured delay. Boundary scan test system, characterized in that further comprises. The method of claim 1, A delay unit configured to delay the clock signal; A pattern analyzing unit analyzing the pattern signal passing through the chip mounted on the board according to the delay clock signal generated by the delay unit; And a delay signal selector configured to select one of the clock signals delayed by the delay unit as the corrected clock signal according to an analysis result of the pattern analyzer. The method of claim 2, The delay unit includes a plurality of delay elements connected in series so that the clock signal can be delayed at a plurality of time intervals. Boundary scan test system, characterized in that the plurality of delay clock signal output from the delay element is input to the pattern analyzer. The method of claim 2, The pattern analyzer determines whether the pattern signal passed through the chip and the pattern signal input to the chip are equal to each other in synchronization with the delay clock signal output from the delay unit. Boundary scan test system, characterized in that it is configured to output a signal. A first step of outputting a pattern signal synchronized with a clock signal to the chip for checking a connection state of a boundary scan test chip mounted on a board; A second step of generating a plurality of delay clock signals by delaying the clock signal of the first step by a plurality of time intervals; And a third step of selecting a corrected clock signal used for sensing data output from the chip among the plurality of delay clock signals. The method of claim 5, The third step may include: synchronizing the plurality of delay clock signals to determine whether the pattern signal passing through the chip is identical to the pattern signal input to the chip; And selecting a delay clock signal as the corrected clock signal when it is determined to be the same in the determination process. The method of claim 5, The third step may include determining whether or not the pattern signal passing through the chip is identical to the pattern signal input to the chip according to the plurality of delay clock signals; And selecting the delayed clock signal following the delayed clock signal as the corrected clock signal when it is determined to be the same in the determination process.