KR20030026751A - Circuit and method for high speed phase locking in a transmission system - Google Patents

Abstract

PURPOSE: A high speed phase synchronizing circuit of a transmission system and a method are provided to reduce a synchronous time of a phase synchronous loop in a SDH(Synchronous Digital Hierarchy) network. CONSTITUTION: A de-mapping stage(210) performs a de-mapping of input data according to a system clock and compares a phase difference between the system clock and a recovery clock. A frequency multiplexing stage(220) performs multiplexing of phase difference information detected from the de-mapping stage and self-oscillating frequency. A phase adjusting stage(230) oscillates a phase synchronous clock according to a level of signal formed by passing the band selected from the output of the frequency multiplexing stage and then provides the oscillated signal to the de-mapping stage(210).

Description

High speed phase synchronization circuit of transmission system and its method {Circuit and method for high speed phase locking in a transmission system}

The present invention relates to a phase synchronization circuit, and more particularly, to a high speed phase synchronization circuit of a transmission system for reducing a synchronization time of a phase locked loop (PLL) in a synchronous digital hierarchy (SDH). It is about.

In general, the phase-locked loop refers to a circuit element that generates an arbitrary frequency by a signal from the outside, and is a feedback closed circuit composed of a phase comparator, a low pass filter, an error amplifier, and a voltage controlled oscillator.

In the phase-locked loop, the frequency and phase of an input signal and the oscillation frequency and phase of a voltage controlled oscillator are compared by a phase comparator to generate a DC voltage proportional to the error. This error voltage is amplified through the low pass filter and applied to the voltage controlled oscillator to change the frequency of the voltage controlled oscillator in a direction to reduce the oscillation frequency and phase difference between the input signal and the voltage controlled oscillator.

Such phase locked loops have various uses. For example, it is used to synchronize the VC-class data of the SDH with the system clock.

1 is a block diagram of a phase synchronization circuit of a transmission system according to the prior art.

In SDH networks in accordance with Recommendation G Series of the International Telecommunication Union-Telecommunication section (ITU-T), the Synchronous Transfer Module 1 (STM1) signal is sent to the Administrative Unit 3 (AU3) in connection with demultiplexing of signals transmitted between transmitting stations. After demapping, it is converted to Virtual Container 3 (VC3).

1, phase synchronization circuits of a transmission system are provided in a working path and a protection path, respectively. This is to form a redundant path and to stably perform signal processing in case of unit failure or the like.

In the operation path and the protection path forming the redundant signal processing path, each phase synchronization loop has the same configuration. The operation of the phase locked loop in the operation path will be described.

The V3 data extracted through demapping of the STM1 signal in the transmission system and a recovery clock synchronized with the data are applied to the VC3 ASIC block 110. The VC3 ASIC block 110 includes a demapping unit 111 for extracting payload data from VC3 data and a phase comparator 112 for comparing phases of a recoverer clock and a system clock.

The demapping unit 111 of the VC3 ASIC block 110 demaps the VC3 data using a system clock used in the system and converts the VC3 data into payload data and a transmission clock. At this time, jitter is generated because the system clock is not exactly synchronized with the recovery clock extracted from the SDH network.

In order to remove jitter during the demapping of the demapping unit 111, the phases of the system clock and the recovery clock are synchronized.

Phase difference information is required for phase synchronization. Thus, the phase comparison unit 112 compares the phase difference between the recovery clock and the system clock to generate phase difference data PhaseDP. This PLL clock is supplied from the phase adjusting stage 120.

Phase difference data PhaseDP generated by the phase comparator 112 is applied to the phase adjusting stage 120. The phase difference data PhaseDP is low-passed and properly amplified by the low pass filter 121 of the satellite control stage 120 and then applied to the voltage controlled oscillator (VCXO) 122. The voltage controlled oscillator 122 controls the oscillation frequency according to the input voltage level, and is controlled according to the output voltage of the low pass filter 121 to output a system clock.

Jitter is removed and the system clock is applied to the demapping unit 111 and the phase comparator 112 of the VC3 ASIC block 110, respectively. Through this feedback closed circuit, a jitter-free system clock is formed to demap VC3 data.

Although the operation path has been described, the operation system in the protection path is the same.

On the other hand, when a path failure occurs, the operation path should be converted to a protection path. Path switching is controlled by an ablation control signal AON. For example, when the transfer control signal (AON) is 'ON', the protection path is switched to the operation path and the recovery clock (Recovery Clock) and the input according to each function of the VC3 ASIC block 150 and phase adjustment stage 160 and By synchronizing the phase of the system clock and demapping the VC3 data, the payload data and the transmit clock are extracted, respectively.

As described above, in the related art, the recovery clock input to the operation path is not transmitted to the protection path. Therefore, when the protection path is changed to the operation path during the path switching, the PLL clock is held after the VC3 data and the recovery clock are input. Therefore, the synchronous time is delayed in the phase-locked loop, making it difficult to operate normally after a fast switching. There is a problem.

The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to provide a high speed phase synchronization circuit of a transmission system for reducing the synchronization time of the phase synchronization loop in the SDH network.

A high speed phase synchronization circuit of the transmission system of the present invention for achieving the above object comprises: a demapping stage for demapping input data according to a system clock and comparing a phase difference between the system clock and a recovery clock; A frequency multiplexing stage for multiplexing the phase difference information and the self oscillation frequency detected by the demapping stage; And a phase adjusting stage for oscillating the phase-locked clock and supplying it to the demapping stage according to the level of a signal formed by passing a band set at the output of the frequency multiplexing stage.

Another object of the present invention is to detect phase difference information between the input data and the system clock, multiplex it with a self-oscillated signal, and then band-filter it to initiate phase synchronization from an intermediate level signal on a path that is switched to the operation path during path switching. It is to provide a fast phase synchronization method of a transmission system.

A high speed phase synchronization method of a transmission system of the present invention for achieving the above object comprises the steps of: detecting a phase difference between the input data and a system clock while demapping input data according to a system clock; Multiplexing the oscillated signal with the detected phase difference information and a set frequency; Band-filtering the multiplexed signal, and oscillating the phase-locked clock according to the level of the band-filtered signal.

1 is a block diagram of a phase synchronization circuit of a transmission system according to the prior art.

2 is a block diagram of a high speed phase synchronization circuit of a transmission system according to an embodiment of the present invention;

3 is a flowchart of a fast synchronization time phase synchronization method of a transmission system according to an embodiment of the present invention;

Explanation of symbols on the main parts of the drawings

210, 250: demapping stage 220, 260: multiplexing stage

230, 270: phase adjusting stage 211, 251: de-mapping unit

212 and 252: phase comparator 221 and 261: oscillator

222, 262: multiplexer 231, 271: low pass filter

232, 272: voltage controlled oscillator

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

2 is a block diagram of a high speed phase synchronization circuit of a transmission system according to an embodiment of the present invention, and FIG. 3 is a flowchart of a high speed phase synchronization method of a transmission system according to an embodiment of the present invention.

According to FIG. 2, the present embodiment is applied to a circuit configuration which is dually operated as a working path and a protection path when demapping VC3 data of a SDH network. VC3 data (VC3 DATA) formed by demapping STM1 signal in SDH network is de-mapped again according to the system clock (SYSTEM CLOCK) used in the system, and payload data (PAYLOAD DATA) and transmission clock (TRANSMIT CLOCK) are extracted. do. The present embodiment is applied when the demapping path of the VC3 data is duplicated and operated.

Since each of the redundant phase synchronization circuits has the same configuration, the following description will focus on phase synchronization in the operation path.

Demapping for extraction of payload data and transmission clocks is performed in the demapping stage 210. The demapping stage 210 may be implemented as an ASIC, and includes a demapping unit 211 and a phase comparator 212.

The demapping unit 211 of the demapping stage 210 receives VC3 data (VC3 DATA) and a system clock (SYSTEM CLOCK) and demaps the VC3 data (VC3 DATA) according to the system clock (SYSTEM CLOCK) to payload. Extract PAYLOAD DATA and TRANSMIT CLOCK. When the demapping unit 211 demaps, the degree of phase shift should be determined to remove jitter, which may occur when synchronization between the VC3 data and the system clock SYSTEMLOCK is inconsistent. In order to achieve such a function, the phase comparison unit 212 compares a phase between a recovery clock inputted in synchronization with VC3 data and a system clock and detects a phaseDP. Is performed by

The phase difference (PhaseDP) detected by the phase comparator 212 is transmitted to the multiplexer 220.

The multiplexing stage 220 includes an oscillator 221 and a multiplexer 222. The oscillator 221 oscillates itself at a set frequency. Preferably, the oscillator 221 oscillates at the same frequency as a recovery clock. In addition, the multiplexer 222 selects and outputs a phase difference (PhaseDP) transmitted from the oscillator 221 and the phase comparator 212.

In the multiplexer 222, a phase difference PhaseDP is input to the low pass filter 231 in the operation path by using the switching control signal AON, and the output of the voltage controlled oscillator 272 is supplied to the low pass filter in the protection path. (271).

The phase adjusting stage 230 includes a low pass filter 231 and a voltage controlled oscillator 232. The low pass filter 231 performs band filtering on the signals output from the multiplexer 222 to pass only the low pass signal. The output of the low pass filter 231 detects the voltage level and controls the generation of the system clock of the voltage controlled oscillator 232. The functions of the low pass filter 231 and the voltage controlled oscillator 232 of the phase adjusting stage 230 are well known.

The system clock generated by the voltage controlled oscillator 232 is applied to the phase comparator 212 of the demapping stage 210 to form a feedback closed circuit.

In the operation path described above, the operation of the phase synchronization circuit is also applied to the protection path. However, since there is no input of the VC3 data and the recovery clock in the protection path, the phase difference output from the phase comparator 252 is fixed to high or low. In the protection path, the multiplexer 262 applies the oscillation frequency to the low pass filter 271 according to the switching control signal AON. At this time, the self-oscillation frequency should be a frequency set close to the recovery clock (Recovery Clock).

Therefore, the system clock on the protection path is input to the multiplexer 262 through the input path of the voltage controlled oscillator 272. Then, the signal input to the low pass filter part 271 immediately after the transfer control signal AON is 'ON' to switch to the operation path has a frequency similar to the recovery clock, not high or low. The phase locked loop can start phase synchronization at a moderate frequency. Therefore, it is possible to reduce the synchronization time during phase synchronization due to the path switching.

Next, an embodiment of the phase synchronization method according to the present invention will be described. The description of the demapping method not limited by the phase synchronization method is omitted here.

According to FIG. 3, a phase difference (PhaseDP) between a recovery clock and a system clock, which are input as an operation path, is detected. The detection of the phase difference PhaseDP may be performed by the phase comparison unit 212 (S310).

The voltage controlled oscillator 232 self oscillates a frequency set close to the recovery clock (S320).

The phase difference (PhaseDP) detected in step S310 and the signal oscillated in step S320 are multiplexed and output. Since the transfer control signal (AON) is 'ON' in the operation path, the multiplexer 222 outputs the phase difference (PhaseDP) information. (S330).

Band filtering is performed on the signal multiplexed and output in step S330, and a PLL clock is generated according to the voltage level of the band-filtered signal and mixed with the phase DP information detected in step S310. This mixing operation may be performed by the phase comparison unit 212 (S340).

The process then repeats from step S310 to step S340. As a result, phase synchronization between the VC3 data and the system clock in the operation path proceeds.

On the other hand, the path switching may be made at any point during the performance of step S310 to step S340. Since the time point at which the path switching is started does not have a characteristic influence on subsequent operations, the following description will be provided as a step subsequent to step S340 for convenience.

That is, if a path change command is issued after the step S340 is performed, the transfer control signal AON is switched to 'ON' on the protection path in which the transfer control signal AON is not 'ON', thereby protecting the corresponding path. The path is switched to the operation path (S350).

When the transfer control signal AON that is 'ON' in step S350 is applied to the multiplexer 260 of the corresponding path, the multiplexer 260 decodes the system clock inputted as phase DP information at the corresponding time. Output After that, the corresponding path becomes the operation path, and returns to step S310 to receive the VC3 data and the recovery clock (Recovery Clock) to perform demapping and multiplexing (S360).

Here, while the steps S310 to S340 are in progress, the multiplexer 262 is controlled while the switching control signal AON is not 'ON' so that the frequency of the oscillator 261 oscillates. Then, the PLL clock is input to the multiplexer 262 in place of phaseDP information on the protection path where the VC3 data is not input. Therefore, in the path that is switched to the operation path at the moment of the path switching, the multiplexing unit 262 is immediately activated to output a signal corresponding to the frequency of the recovery clock to the low pass filter unit 271 for rapid synchronization. To be done.

As such, the present embodiment maintains the phase difference information input to the phase synchronization loop on the protection path to be similar to the frequency corresponding to the recovery clock, thereby enabling rapid phase synchronization at the moment of switching to the operation path due to the path switching. In the present embodiment, when the switching path to the protective path in the operating path is made, the low pass filter input value starts at the high or low side in the transition to the operating path, so that the synchronous time required for catching the PLL phase is long. Has the advantage of being contrasted.

The embodiments described above are within the scope of various changes, modifications, and equivalents of the present invention. Therefore, the present invention is not limited to the description of the examples.

According to the high-speed phase synchronization circuit and the method of the transmission system of the present invention, when the path of the protective path is switched in the operating path, the low pass filter input is maintained at an intermediate level, thereby enabling rapid phase synchronization.

Claims (7)

A demapping stage for demapping input data according to a system clock and comparing a phase between the input data and a system clock to detect a phase difference; A frequency multiplexing stage for multiplexing the phase difference information and the self oscillation frequency detected by the demapping stage; And a phase adjusting stage for oscillating the system clock and supplying the system clock to the demapping stage according to a level of a signal formed by passing only a predetermined band among the outputs of the frequency multiplexing stage. . The method of claim 1, wherein the de-mapping stage, A demapping unit configured to demap VC3 data of the SDH network according to a system clock to generate payload data and a transmission clock; And a phase comparator for detecting the phase difference between the VC3 data and the system clock and mixing the system clock with the system clock applied from the phase adjusting stage to the frequency multiplexing stage. The method of claim 1, wherein the frequency multiplexing stage, An oscillator for self oscillating at a set frequency; And a multiplexer for multiplexing the phase difference information output from the demapping stage and the signal oscillated by the oscillator and applying the same to the phase adjuster. 4. The multiplexer of claim 3, wherein the multiplexing unit is provided in the operation path and the protection path, respectively. When the protection path is converted to the operation path by the path switching according to the set switching control signal, the switched operation path is activated by the transfer control signal to apply the multiplexed signal to the phase adjusting stage. High speed phase synchronization circuit of the system. Detecting a phase difference between the input data and the system clock while demapping input data according to a system clock; Multiplexing the oscillated signal with the detected phase difference information and a set frequency; Band-filtering the multiplexed signal, and oscillating the system clock according to the level of the band-filtered signal. The method of claim 5, wherein the phase difference information, A high speed phase synchronization method of a transmission system, characterized in that it is calculated by comparing the phase between the VC3 data of the SDH network and the system clock. The method of claim 5, wherein the multiplexing of the phase difference information and the oscillated signal when the phase synchronization loop is provided in the operation path and the protection path, respectively, A path switching is performed according to a set switching control signal, and is performed on a path transferred from the protection path to an operation path.