KR20030026236A - An improved digital transmission system for an enhanced ATSC 8-VSB system - Google Patents

Abstract

PURPOSE: An improved digital transmission system for an enhanced ATSC(Advanced Television System Committee) 8-VSB(Vestigial Side Band) system is provided to transmit new robust bit streams together with the standard ATSC bit streams. CONSTITUTION: A digital signal transmission system transmits encoded data packets including normal packets for transmission as a normal bit stream and robust packets comprising information for transmission as a robust bit stream. The system comprises a first forward error correction unit(110) for encoding packets belonging to each the robust and normal data bit streams; a robust processor unit(115) for receiving robust packets comprising priority data and processing the packets for generating the robust bit stream; a trellis encoder unit(330) for producing a stream of trellis encoded data bits corresponding to bits of the normal and robust streams; an optional second forward error correction encoding unit(125) for ensuring backward compatibility with a receiver device by reading in only packets of the robust bit stream and enabling generation of parity bytes only for the robust stream packets; and a transmitter device for transmitting the robust bit streams in a backwards compatible manner, separately or in conjunction with the normal bit stream over a fixed bandwidth communication channel to a receiver device. A receiver device includes an existing receiver device capable of receiving and processing packets of the robust bit stream as null packets.

Description

An improved digital transmission system for an enhanced ATSC X-UX system

TECHNICAL FIELD The present invention relates to digital signal transmission systems, and in particular, to the Advanced Television Systems Committee (ATSC) digital television (DTV) standard (A / 53). The present invention describes a method of transmitting a robust bit stream with a standard bit stream using the ATSC standard with backward compatibility.

The ATSC standard for high-definition television (HDTV) transmission over terrestrial broadcast channels modulates a series of twelve independent, time-multiplexed data streams as 8-level residual sideband (VSB) symbol streams at a rate of 10.76 MHz. Use one signal. The signal is converted to the 6 MHx frequency band corresponding to a standard VHF or UHF terrestrial television channel that broadcasts the signal at a data rate of 19.39 million bits per second (Mbps). Details of the ATSC digital television standard and the latest revision A / 53 are available at http://www.atsc.org/.

1 is a block diagram illustrating a typical prior art high definition television (HDTV) transmitter 100. MPEG-compatible data packets are first randomized in the data randomizer 105 and each packet is encoded for forward error correction (FEC) by the Reed Solomon (RS) encoder unit 110. The data packets in successive segments of each data field are then interleaved by the data interleaver 120, which is then interleaved and encoded by the trellis encoder unit 130 again. The trellis encoder unit 130 generates a data symbol stream having three bits each. One of the three bits is pre-encoded and the other two bits are generated by the four state trellis encoder. The three bits are then mapped to eight level symbols.

As is known, the prior art trellis encoder unit 130 includes twelve parallel trellis encoders and pre-coder units to provide twelve interleaved encoded data sequences. . The multiplexer 140 combines the synchronization bit sequences 150, which are "segment sync" and "field sync" from a synchronization unit (not shown), to the symbols of each trellis encoder unit. The in-phase small signal is then inserted by pilot insertion unit 160 and optionally pre-equalized by filter device 165. The symbol stream is then modulated by a residual sideband (VSB) suppressed carrier by VSB modulator 170. The symbol stream is then finally up-converted to radio frequency by a radio frequency (RF) converter 180.

2 is a block diagram illustrating a typical prior art high definition television (HDTV) receiver 200. The received RF signal is down-converted to the intermediate frequency IF by the tuner 210. The signal is then filtered and converted into digital form by the IF filter and detector 220. The detected signal is in the form of a data symbol stream, each of which corresponds to one level of eight level positions. The signal is then filtered at NTSC rejection filter 230 and equalized and position tracked by equalizer and phase tracker 250. The recovered encoded data symbols are trellis decoded by trellis decoder unit 260. The decoded data symbols are deinterleaved again by the data deinterleaver 270. The data symbols are then decoded by Reed Solomon decoder 280. Accordingly, MPEG compatible data packets transmitted by the transmitter 100 are recovered.

The current ATSC 8-VSB A / 53 digital television standard can transmit enough signals to overcome many channel damages such as ghosting, noise bursts, signal fades and interference in terrestrial settings, but with varying priority and data rates. There needs to be flexibility in the ATSC standard so that streams can be accommodated.

Accordingly, an object of the present invention is to provide a technique for transmitting new robust bit streams along with a standard ATSC bit stream in an ATSC digital transmission system, where the new bit stream has a lower latency threshold than an ATSC stream. It can be used to transmit high priority information bits.

Another object of the present invention is to provide a flexible ATSC digital transmission system and method that is backward compatible with current digital receiver devices.

It is yet another object of the present invention to provide a flexible ATSC digital transmission system and method that provides a parity byte generator mechanism for backward compatibility with current receiver devices.

According to a preferred embodiment of the present invention, there is provided a digital transmission system and method for improving the ATSC A / 53 HDTV signal transmission standard,

A first forward error correction (FEC) encoding unit for forming packets belonging to the robust and normal data bit stream;

A robust processor unit for receiving robust packets containing priority data and processing these packets to generate a robust bit stream;

An encoder unit for generating a trellis encoded data bit stream corresponding to the bits of a regular and robust stream, wherein the encoder is configured to encode the encoded data bits of the robust packets in accordance with one or more symbol mapping schemes. The trellis encoder unit employing means for mapping to symbols;

An optional second forward error correction (FEC) encoding unit for ensuring backward compatibility with a receiver device by reading only packets of the robust bit stream to enable generation of parity bytes only for the robust stream packets and;

A transmitter device for transmitting the robust bit streams to a receiver device for backward compatibility, separately or together with the regular bit stream, over a fixed bandwidth communication channel, the current receiver device comprising the robust bit Packets in the stream can be received and processed.

Add parity bytes to robust bitstream packets using an optional non-systematic Reed-Solomon encoder, to be backward compatible with current receivers from various manufacturers. . The standard 8-VSB bit stream will be encoded using the ATSC FEC scheme (A / 53). Packets sent using the new bit stream will be ignored by the transport layer decoder of the current receiver.

1 is a block diagram of a high definition television (HDTV) transmitter according to the prior art;

2 is a block diagram of a high definition television (HDTV) receiver according to the prior art;

3 shows a first embodiment 201 of an improved ATSC standard in accordance with the present invention.

4 shows a second embodiment 300 of an improved ATSC standard according to the present invention.

5 is a block diagram illustrating a trellis encoding method 330 implemented in the transmission systems of FIGS. 3 and 4.

6 is a simplified block diagram showing a coding circuit 335 outside of a modified trellis encoder 330 in accordance with the present invention.

7 is a detailed view of a robust packet interleaver block 300 shown as including an interleaver 401 and a packet formatter unit 402.

8 (a) and 8 (b) show two bytes of a packet when MODE = 2 or 3 and NRS = 0 (Fig. 8 (a)) and NRS = 1 (Fig. 8 (b)), respectively. A diagram illustrating the functionality of a basic formatter that replicates in bytes.

9 (a) and 9 (b) show two bits of the input packet when MODE = 1 and NRS = 0 (Fig. 9 (a)) and NRS = 1 (Fig. 9 (b)), respectively. A diagram illustrating the functionality of a basic formatter to rearrange it.

10 illustrates a parity 'place-holder' insertion mechanism in the case of an example scenario.

* Description of the symbols for the main parts of the drawings *

105; Data randomizer 110; RS encoder

115; Robust Interleaver, Packet Formatter, and Packet MUX

170; VSB modulator 180; RF upconverter

A new method of the ATSC digital transmission system standard, including means and methods for transmitting a new "robust" bit stream along with a standard ATSC (8-bit) bit stream, wherein the new bit stream is lower than the standard 8-VSB ATSC stream. With a Visibility Threshold (TOV), it can be used to transmit high priority information bits, and this new scheme is disclosed herein, which is incorporated herein by reference in its entirety and described herein by reference. Applicant's co-pending US patent application 10/078933 entitled "system".

In particular, the novel features provided in the proposed ATSC digital transmission system and method described in co-pending U.S. Patent Application 60/280782, incorporated herein, are subject to error even in severe static and dynamic multipath interference environments at reduced CNR and reduced TOV. A mechanism that allows for the trade-off of data rates of standard bit streams for robustness of new bit streams by enabling the decoding of robust packets with new receiver devices without the need for backwards compatible transmissions with current digital receiver devices. It includes a mechanism for enabling it. The described system improves on current ATSC digital transmission system standards by enabling flexible transmission rates, particularly for robust and standard streams to accommodate a large range of carrier noise and channel conditions.

3 shows a first embodiment 201 of an improved ATSC standard in accordance with the present invention. As shown in Fig. 3, the improved ATSC digital signal transmission standard according to the first embodiment firstly changes the data randomizer element 105 which changes the input data byte value according to the generation of the pseudo-random number of the known pattern. ). According to the ATSC standard, for example, the data randomizer XORs all incoming data bytes into a 16-bit maximum length pseudo random binary sequence (PRBS) that is initialized at the beginning of the data field. The output randomized data is input to the Reed Solomon (RS) encoder element 110, which acts on a data block size of 187 bytes, whereby 20 RS parity bytes for error correction are added to the total transmitted per data segment. The RS block size is 207 bytes. These bytes will later be processed and sent using robust arrays. After RS encoding, the 207 byte data segment is input to a new block 1150 to process / reformat robust input bytes, which includes a robust interleaver element, a packet formatter element, and a packet multiplexer element. . Details of the operation of individual elements of the packet formatter block can be found in the "Packet identification mechanism at the transmitter", incorporated herein by reference in its entirety and disclosed herein, and the co-pending US patent application 10/078933, incorporated herein by reference. and receiver for an enhanced ATSC 8-VSB system, described in detail in Applicant's co-pending US patent application 10/118876. Most commonly, robust interleaver, packet formatter, and packet multiplexer elements for reformatting incoming bytes will process input bytes (for robust bytes) or not (for regular bytes). In response to the mode signal 113 indicating. After interleaving robust packets in the robust interleaver, the data bytes belonging to the input robust bit-stream are buffered and divided into groups of a predetermined number of bytes, for example 207 bytes, in the packet formatter device. In general, for robust packets, only four bits of each byte of the packet formatter output, i.e., MSBs 6, 4, 2, 0, correspond to the input stream. The other four bits of each byte, i.e., the MSBs 7, 5, 3, and 1, can be set to any value for the following reasons. After byte reformatting in the packet formatter 115, the bytes belonging to robust packets are multiplexed with the bytes belonging to the standard stream. Multiplexed stream 116 multiplexed with robust bytes and standard robust is input to convolutional interleaver mechanism 120, where each data field is used to scramble the sequential order of the data streams according to the ATSC A / 53 standard. Interleaving the data packets in successive segments of. As described below, the bytes associated with each robust packet or standard packet are tracked in concurrent processing control blocks (not shown). As shown in FIG. 3, interleaved, RS encoded and formatted data bytes 117 are trellis encoded by the novel trellis encoder device 330. The trellis encoder unit 330, in particular in response to the mode signal 113, has a backward compatible pariter byte generator element 125, referred to herein as a backward compatible (optional RS encoder) block 125, as described in detail below. Interact with each other to generate a trellis coded data symbol output stream having three bits, each mapped to an eight level symbol. The trellis coded output symbols are sent to the multiplexing unit 140 and combined with the synchronization bit sequences 138 which are " segment sync " and " field sync " from the synchronization unit (not shown) in the multiplexing unit. The pilot signal is then inserted by the pilot insertion unit 160. The symbol stream is residual sideband (VSB) suppressed carrier modulated by VSB modulator 170, and the symbol stream is finally up-converted to radio frequency by radio frequency (RF) converter 180.

4 shows a second embodiment 300 of an improved ATSC standard in accordance with the present invention. As shown in FIG. 4, the improved ATSC digital television transmission standard according to the second embodiment includes blocks of the same function as the first embodiment shown in FIG. 3, but the system 300 of FIG. The front end processes the bytes belonging to robust packets received from the input robust bit stream 207 and the processed to the MPEG multiplexing unit 210 which also receives the bytes belonging to the regular (standard) bit stream 208. New blocks that include robust processor element 205 that sends the message. The multiplexing unit 210 multiplexes the robust packet and the standard robust for input to the standard data randomizer element 105 which changes input data byte values according to pseudo-randomly generated patterns, for example. The output randomized data is then input to Reed Solomon (RS) encoder element 110, which acts on a data block size of 187 bytes, transmitting 20 RS parity bytes for error correction, thereby transmitting per data segment. Total RS block size of 207 bytes. After RS encoding, 207 bytes of data segment 214 are entered into a byte permute block 215, which is an optional block that processes only packets of the robust bit stream and passes unaltered regular packets. This byte permut block 215 serves to replace the parity bytes added by the preceding RS encoder block 110 to zero, and after the data interleaver, 184 data bytes (header bytes) generated by the robust processor Permute the 207 bytes to make them precede the parity bytes. As shown in Fig. 4, the new block, the byte permut block 215, operates in accordance with the mode signal 113, which specifically indicates whether or not to process input bytes into this block. As in the first scheme described with respect to FIG. 3, the data segments of robust bytes and standard bytes 216 output from the byte permut block 215 are input to the convolutional interleaver mechanism 120 and in this mechanism In order to scramble the sequential order of the data streams according to the ATSC A / 53 standard, interleaving data packets in successive segments of each data field. As shown in Fig. 4, the interleaved, RS encoded and formatted data bytes 217 are trellis encoded by the novel trellis encoder device 330. As described below, the trellis encoder Unit 330 interacts with backward compatible (optional RS encoder) block 125 to generate a trellis coded data symbol output stream having 3 bits each mapped to an 8 level symbol. The trellis coded output symbols are sent to the multiplexing unit 140 and combined with the synchronization bit sequences 138 which are " segment sync " and " field sync " from the synchronization unit (not shown) in the multiplexing unit. The pilot signal is then inserted by the pilot insertion unit 160, the symbol stream is modulated by a residual sideband (VSB) suppressed carrier by the VSB modulator 170, and the symbol stream by the radio frequency (RF) converter 180. Up-converted to radio frequency.

As shown in FIG. 4, robust processor element 205 includes an input for receiving MPEG data packets 207 delivered as a robust stream. This robust processor block 205 includes a Reed-Solomon encoder, followed by an interleaver device, followed by a formatter block that forms 188 byte long packets (MPEG compatible packets). The last block (MPEG packet formation) inserts redundant bits to form a 184 byte packet, followed by four MPEG header bytes to form a complete 188 MPEG packet. Robust packets 206 from the processor block 205 are sent through the MPEG multiplexer 210 to the ATSC stream 209 including the regular packet and the robust packet so that the regular packets of the MPEG packet stream 208 can be sent. Multiplexed with them. Normal stream packets are preferably multiplexed with robust packets according to a predefined algorithm described below. For purposes of discussion and as described in detail in Applicant's co-pending US Patent Application No. 10/118876, which is hereby incorporated by reference herein, control of tracking the type of packets transmitted, i.e., regular or robust type. Mechanisms are provided. Accordingly, as shown in FIGS. 3 and 4, with respect to each byte, a regular / robust includes bit 211 used to identify the bytes by tracking the transition of the bytes in the enhanced ATSC digital signal transmission scheme. ("N / R") signal is generated.

In general, in the embodiment of ATSC described in connection with FIG. 4, in the transmission of robust packets in the manner of multiplexing robust packets 206 with regular packets 208 in the MPEG multiplexer element 210. You need to know about it. Packets should be inserted so that they can improve the dynamic and static multipath performance of the receiver device. A representative algorithm for controlling the multiplexing of robust stream packets into regular stream packets in robust processor block 205 of FIG. 5 is described with reference to Table 1. Robust packets can be utilized to design a better robust receiver by the packet insertion algorithm.

At the beginning of the MPEG field, one group of robust packets is arranged adjacent thereto, and the remaining packets are inserted using a predetermined algorithm as described above with reference to Table 1. Packets of the first group allow the equalizer to acquire static and dynamic channels more quickly. This robust packet insertion algorithm is implemented before interleaving all fields. Regarding the robust packet insertion algorithm as an example of Table 1, first, the following quantities and terms are defined. The first amount, referred to as "NRP", represents the number of robust segments occupied by robust packets per field (ie, the number of robust packets in a frame). The amount called "M" is the number of contiguous packet locations occupied by the robust bit-stream immediately following field synchronization. The letter "U" represents two sets of unions. "Flow" denotes a decimal cut that causes the values to be integer values. As shown in Table 1, the algorithm performs the following evaluation to determine the arrangement of robust packets in the bit stream.

Thus, in the implementation where M = 18, in accordance with the above algorithm, the algorithm for the arrangement of robust packets is as follows.

In each of the first and second embodiments of FIGS. 3 and 4, a backward compatible pariter byte generator element 125 (also referred to as an optional non-systemic RS encoder) is used to read the bytes from the trellis decoder. I install it. In particular, this block 125 includes a byte de-interleaver block and an optional " non-cystematic " RS encoder block that reads packets from the byte de-interleaver block and encodes them to generate parity bytes. This generates pariter bytes only for robust stream packets used for backward compatibility. The algorithm used to perform this function is provided in relation to Table 2.

For some packets (e.g., 1 to 7 mod 52), it may be necessary to have advance information about randomized header bytes because not all header bytes of these packets may be used in RS encoding. will be. That is, these packets are when some header bytes come after the parity bytes in the convolution interleaver output. Therefore, instead of waiting for these header bytes to calculate 20 parity bytes, dictionary information about the header bytes that is used instead in calculating the parity bytes is used (they are deterministic).

In 1984, as described in the "Error Control Technique for Digital Communication" book by Arnold Michelson & Allen Levesque of John Wiley, New York, the (N, K) RS decoder was used for (NK) / 2 error or (NK) cancellation. The erase can be corrected, where "N" is the code word length and "K" is the message word length. In general, when there is an E _a erase and an E _b error in _a code word of length N, the decoder searches for as many code words as (E _a + 2 * E _b ) equal to or less than (NK), as shown in Equation (1) below. It can be completely restored.

(E _a + 2 x E _b ) ≤ (NK) (1)

Where E _a and E _b are the number of erases and the number of errors in the code word, respectively.

This property of RS codes can be used to generate 20 parity bytes. Twenty parity byte positions are calculated for use as the position of erases in the RS decoder. The process of calculating parity byte positions is similar to that used in the packet formatter. Bytes belonging to the packet (zero parity byte positions) are passed to the RS decoder as an input code word. The decoder calculates bytes for the erase position in the erase filling process. These bytes correspond to 20 parity bytes. Accordingly, the parity byte generator block generates parity byte position information. Parity bytes and header bytes are always encoded as standard 8-VSB symbols.

Parity bytes for each packet and their location information are sent to a modified trellis encoder device for mapping robust bytes according to a new symbol mapping scheme. It should be noted that for some packets (e.g., packets 1 to 7) it is necessary to have advance information about randomized header bytes since not all header bytes of these packets will be available in RS encoding. something to do.

The high-level operation of the modified trellis encoder is controlled by the rules described in Section 4.2.5 of the ATSC A / 53 Transmission Standard. This high-level operation relates to trellis interleaving, symbol mapping, the manner in which each trellis encoder is read, and the like. The trellis encoding of canonical 8-VSB packets is not changed. However, the trellis encoder block according to the ATSC A / 53 standard has 1) the ability to bypass the pre-coder if the bytes belong to the robust bit stream, and 2) each MSB if the bytes belong to the robust stream. Derive bits and send new bytes to the "Byte De-Interleaver" block, and 3) read pariter bytes from the "Byte De-Interleaver" block and use them for encoding (if they belong to the robust stream). And 4) a modified mapping scheme to perform the function of mapping the symbols belonging to the robust bit-stream. It will be appreciated that parity bytes are preferably mapped to eight levels.

With regard to the function of bypassing the pre-coder and the function of forming the byte, this process is a dependent mode as described with respect to the modified trellis encoder diagram of FIGS. 5 and 6.

In particular, FIG. 5 is a block diagram illustrating a trellis encoding scheme 330 implemented in the transmission systems of FIGS. 3 and 4. For enhanced 8-VSB (E-VSB), or 2-VSB streams, each trellis encoder receives one byte and contains only 4 bits (LSB) information bits within this byte. When a byte belonging to the robust stream is received at the trellis encoder, the information bits (LSB, bits 6, 4, 2, 0) are arranged in X ₁ (after being encoded in the robust mode). The bits to be arranged in X ₂ are then determined to obtain a particular symbol mapping scheme. Once X ₂ and X ₁ are determined, all the bits of the byte are determined for the purpose of doing the subsequent “non-systemic” RS encoding. This byte is then passed through the data lines 35 to the backward compatible parity-byte generator 125 (ie, a "non-systemic" Reed-Solomon encoder). However, the parity bytes and PID bytes of a "non-systemic" Reed-Solomon encoder will be encoded using the 8-VSB encoding scheme. The upstream trellis encoding block 335 of the trellis encoder 330 in each digital signal modulation mode is described with reference to FIG.

The upstream trellis encoding block 335 shown in FIG. 6 is the inputs of the pre-coder 360 of the standard trellis encoder block 359, X ₂ , to achieve the desired symbol mapping or encoding method, and Calculate X ₁ . For example, these encoding methods are for standard 8-VSB, (enhanced) E-VSB and 2-VSB, so that the "8/2" control bits 353 to indicate the correct encoding (symbol mapping scheme). This is provided. The output bits of this block are divided into groups into their respective bytes, which are eventually fed to a "non-systemic" RS encoder block for parity byte generation. The regular / robust control bits 211 required to configure the multiplexers 336a,... 336d of FIG. 6 are provided by the tracking / control mechanism blocks of FIGS. 3 and 4, respectively.

Accordingly, in normal (standard) 8-VSB symbol mapping mode, the input bits X ' ₂ , X' ₁ received from the preceding interleaved block and input to the upstream coder 335 of the trellis encoder 330. ) Is sent to the regular trellis encoder, which includes the pre-coder unit 360 and the encoder unit 370, without modification. This is accomplished by having the N / R bit 211 select the N input of the multiplexers. The 8/2 bit 353 is another control bit indicating the trellis mapping method to use when the N / R bit is R (robust).

In 2-VSB mode and 4-VSB symbol mapping mode, the MSB does not have any information. In order to satisfy the mapping requirement, the Z ₂ bits are first calculated and then modulo-2 summed with the pre-coder memory contents 363 (Figure 5) to derive MSB X ₂ . A new byte is formed from the calculated MSB and input information bit X ₁ . The memory element is updated to X ₂ . Thus, in this case, the trellis encoder outputs Z ₂ , Z _{1 become} equal to the information bit. In other words, the input X ₂ is calculated to be equal to the information bits when the output Z ₂ of the pre-coder is pre-coded. This operation is implemented in the upstream coding circuit 335 shown in FIG. In addition, X ₁ becomes equal to the information bit. These operations, in combination with the current symbol mapping scheme performed by the trellis encoded symbol mapper 380, result in symbols from the alphabet {-7, -5, 5, 7}. This is essentially a 2-VSB signal in that the information bits are sent as the sign of this symbol. The actual symbol is a valid trellis coded four-level symbol that can be decoded by current trellis decoders. For example, to achieve 2-VSB encoding, the N / R bit 211 is set to select the R input and the 8/2 switch 353 is set to '' of the multiplexers 336a, ..., 336d. It is set to select 2 'inputs.

In enhanced 8-VSB mode (E-VSB) mode, X ₂ and X ₁ correspond to the outputs of the enhanced coder (ie, upstream coder 335). These bits should be used when forming bytes instead of actual inputs. Therefore, in this mode, Z ₂ becomes equal to the information bits by inserting the trellis coded information bits into X ₁ . To do this, X ₂ is calculated to be an information bit when pre-coded. The information bits go through an additional trellis encoder to output X ₁ . Overall, for the E 8-VSB, the outer coder 335 and regular trellis encoder 359 would be the same as the 1/3 rate trellis encoder in the higher state (eg 16 state). . The resulting symbol is an 8-level trellis coded symbol. To achieve enhanced 8-VSB encoding, the N / R bit 211 is set to select the R input and the 8/2 switch 353 is the "8" input of the multiplexers 336a, ..., 336d. Is set to select.

In each of these modes, there is a delay of 12 bytes by the symbol-byte converter.

Regarding the function of reading parity bytes from the byte de-interleaver, this is only implemented when NRS = 1 (ie, non-systemic RS encoding is implemented). The trellis encoder 330 obtains parity bytes and position information of the parity bytes for each packet from the parity byte generator 125. The trellis encoder 330 then determines whether the particular byte to encode belongs to a set of parity bytes. If the byte belongs to the robust stream parity byte set, it reads one byte from the byte de-interleaver and uses it for trellis encoding instead. Symbols generated from parity bytes are always mapped to eight levels using the original encoding and mapping method.

In particular, a parity 'place-holder' is inserted by the packet formatter element of the transmission systems of FIGS. 3 and 4.

7 details a robust packet processor block 300 shown as including an interleaver 401, a packet formatter unit 402, and a regular / robust multiplexer (N / R MUX) 405. . Robust packet interleaver 401 preferably interleaves only robust packets. The packet formatter 402 processes robust packets depending on whether a "non-systemic" RS encoder has been used so that current receivers are backward compatible. If it is determined that NRS = 1, a "non-systemic" RS encoder is used and the packet formatter 402 reads 184 bytes from the interleaver and divides these bytes into two 184-byte data blocks. In general, only four bits of each robust byte, i.e., LSBs (6, 4, 2, 0), correspond to the input stream. The other four bits of each byte, i.e., the MSBs 7, 5, 3, 1, are set to arbitrary values. After packet segmentation is performed, three randomized null packet ID (or three null PID) bytes are inserted at the beginning of each of the two 184-byte long data blocks. The 207 byte packet is then generated by inserting 20 "place-holder" parity bytes into each data block. Upon generating 208 bytes, after the standard 8-VSB data interleaver, permute the 84 bytes containing the information stream and 20 "place-holder" parity bytes such that these 20 bytes appear at the end of 184 bytes containing the information bits. At this stage, the values of 20 bytes can be set to zero. With this option used for the purpose of enabling current receivers to be backward compatible, the effective data rate is reduced since 23 bytes (20 parity bytes and 3 header bytes) have to be added per packet. The result is a 12% reduction in payload. If it is determined that NRS = 0, the "non-cystematic" RS encoder is not used. In this case, the packet formatter 402 reads 207 bytes from the interleaver and splits these bytes into two 207-byte packets. In general, only four bits of each byte, i.e., LSBs (6, 4, 2, 0), correspond to the input stream. The other four bits of each byte, i.e., the MSB (7, 5, 3, 1), can be set to any value. In both cases, robust / regular packet MUX 405 is a packet (207 byte) level multiplexer. This multiplexes robust packets and regular packets on a packet basis.

The function of the packet formatter depends on the MODE and NRS parameters. If NRS = 0, the packet formatter basically performs the function of byte duplication or byte rearrangement. If NRS = 1, insert a 'place-holder' for the extra header and parity bytes. Table 3 summarizes the packet formatter functionality for each combination of MODE and NRS parameters.

NRS MODE Number of input packets Number of output packets Functional 0 2, 3 One 2 Byte duplicate 0 One 2 2 Reorder bits One 2, 3 4 9 Duplicate bytes, insert "place holders" One One 8 9 Insert rearranged bits, "place holders"

Where the "MODE" parameter contains a specification of robust packets and the robust packets are used to identify the format, and as mentioned, the "NRS" parameter encodes one robust packet into two symbol segments by an FEC block. Whether a non-systemic RS coder is not used (when NRS = 0), or a group of four robust packets is encoded by the FEC block into nine packet segments. Indicates whether the tick RS coder was used (when NRS = 1). Regarding the MODE parameter, it is desirable to use two bits in identifying four possible modes. For example, MODE 00 represents a standard stream with no robust packets to transmit, MODE 01 represents an H-VSB stream, MODE 10 represents a 4-VSB stream, and MODE 11 represents a pseudo 2-VSB stream. If MODE = 00, the remaining parameters can be ignored. Specifically, the packet formatter block 402 includes three functional units: 1) basic formatter, 2) parity position calculator, and 3) 'place-holder' inserter. As shown in Figs. 8A and 8B, when MODE = 2 or 3, and NRS = 0 (Fig. 8 (a)) and NRS = 1 (Fig. 8 (b)), respectively, When = 2 or 3, the base formatter duplicates the bytes of the packet 411 into two bytes 412a, 412b. When MODE = 1 as shown in Figs. 9 (a) and 9 (b), respectively, for each case where NRS = 0 (Fig. 9 (a)) and NRS = 1 (Fig. 9 (b)), The default formatter rearranges the bits of the input packet. The bit rearrangement, for example, as shown in Figures 9 (a) and 9 (b), causes bits 415 belonging to the "robust stream" to always go to the MSB bit positions and the "insert stream". Bits 417 belonging to 'are performed in H-VSB mode to always go to the LSB bit positions of reformatted packets 418a and 418b. As mentioned, the packet formatter unit 402 of FIG. 7 includes a parity 'place-holder' inserter function. The parity 'place-holder' inserter block is used only when NRS = 1 (ie, when an additional parity byte generator is used). This specifically converts 8 packets into 9 packets by inserting 20 'place-holders' for three header bytes and pariter bytes into each of the eight formed packets. Header bytes are always scrambled after being arranged in positions 0, 1, 2 of each byte. Byte positions corresponding to parity byte positions may be filled with zeros upon first formation. All other remaining byte positions can be filled with message bytes in order.

10 illustrates a parity 'place-holder' insertion mechanism in the case of an example scenario (NRS = 1). The basic formatter converts one data packet 450 of 207 bytes into 404 bytes (ie, two packets). Parity byte place-holder positions 460a, 460b, 460c for each packet are determined according to the following equation (2).

m = (52 * n + (k mod 52)) mod 207 (2)

Where m is the number of output bytes and n is the number of input bytes, for example n = to 206, and k = 0 to 311 corresponds to the number of packets. The 'm' values of parity byte positions can be computed for n = 187 to 206 million so that the position of 20 parity packets for each packet always corresponds to the last 20 bytes of this packet (these n values are packets Corresponding to the last 20 bytes of. For example, substituting k = 0 and n = 187-206, the parity byte positions for packet 0 are 202, 47, 99, 151, 203, 48, 100, 152, 204, 49, 101, 153, 205, 50 , 102, 154, 206, 51, 103, 155. This indicates that the parity byte PB0 should be at position 202 so that after the interleaver the position is from packet 0 to 187. Similarly, parity byte PB1 should be at position 47, and so on. For some packets, parity bytes may be in packet header positions (m = 0, 1 or / and 2), ie since the first three positions of the packet are reserved for three null header bytes. It can be seen that m "will be 0, 1 or 2. To avoid this situation, the range of 'n' may be increased by the number of parity bytes (up to 3) coming in the header positions. Thus, in the calculation of 20 values of "m" for other packet numbers, some of these "m" values become 0, 1 and / or 2 when "k mod 52" = 1-7. For example, when "k mod 52" = 0, none of the "m" values will be in the location of the header byte. In this case, all 20 "m" values are specified as parity place-holder positions. When "k mod 52" = 1, one of the "m" values becomes 0 (the header byte). In this case, the "n" range is increased by 1 so that "n" becomes 186-206. Thus, 21 "m" values are calculated and these "m" values coming in header byte positions are discarded. The remaining 20 "m" values are designated as parity place-holder positions. When "k mod 52" = 2, two of the calculated "m" values may be 0 and 1 (the header bytes). In this case, the "n" range is increased by 2 such that "n" becomes 185-206. Thus, 22 "m" values (20 + 2 additions) are calculated and the "m" values coming in the header byte positions are discarded. The remaining 20 "m" values are designated as parity place-holder positions. Table 4 provides packet numbers for all other exception cases. This also gives the number of additional 'm' values to calculate.

Packet Count mod 52 Additional "m" values to be calculated range of 'n' 0 0 187-206 One One 186-206 2 2 185-206 3 3 184-206 4 3 184-206 5 3 184-206 6 2 185-206 7 One 186-206 8-51 0 187-206

In particular, as shown in FIG. 10, when each packet 450 contains 207 bytes, the basic formatter will split it into two new packets 451, 452 each containing 207. The parity place-holder insertion mechanism performed by the packet formatter specifically processes each of the new packets 451, 452 to include 20 parity bytes at interleaved positions 460a, 460a,... Accordingly, from new packets 451 and 452, the packet formatter will generate new packets 451 'and 452' to accommodate all parity and header bits. Accordingly, a new packet 451 'of 207 bytes includes 184 bytes of 451, 20 parity place-holders and 3 null header bytes 454. As shown in Fig. 10, this is the first of three new packets 451 ', 452', 453 'where two new packets 451, 452' are completely filled and the third packet 453 'is only partially filled. ) Means that one raw data packet 450 is mapped. Before inserting a data byte into new packets 451 ', 452', and 453 ', the position is checked to see if it belongs to the parity byte. If the position does not correspond to any of the positions of the parity byte, then the data byte is placed at that position. If the position belongs to a parity byte, that byte position is skipped and the next byte position is checked. The process is repeated until all bytes are arranged in new packets. As a result of this conversion, each of the nine output packets includes 92 bytes from the input packets (eg, input packet 450). In one embodiment, the minimum element of 9 segments is selected for NRP when NRS = 1. When data is read from the randomizer, four packets of a nine packet block will contain information bytes while the remaining five packets will not contain any information. The packet formatter spreads four packets of information into nine packets through the process described above. This ensures that the payload data rate is not lowered more than necessary.

In the newly proposed technique of the present invention, several bits must be transmitted to the receiver so that the receiver device can decode the correct transmission mode. This mode typically includes the number of robust packets, the type of modulation, and the redundancy level inserted for trellis encoding. This information may be sent in the reserved bit portion of the field sync segment 138.

In particular, in order to reliably detect the transmitted information, additional encoding bits are needed. According to a preferred embodiment, a spread spectrum type code is provided for encoding each information bit into the present illustrated N bits.

For example, bit 1 can be encoded as b, where b = {1 1 0 0 1 1 0 0}. In this case N = 8. Bit 0 may then be encoded as {1 1 1 1 1 1 1 1} xor b and becomes {0 0 1 1 0 0 1 1}. Each bit is encoded in this way and inserted in field sync. Accordingly, in HDTV receivers, standard correlation algorithms can be used to detect the transmitted bits. This encoding technique provides a means by which the detection of information bits can be achieved using simple decoding hardware under extremely severe interfering conditions.

The presented DTV system requires the transmission of many bits. For example, 2 bits indicating modulation type, 1 bit indicating trellis coding redundancy, 4 bits indicating the number of robust packets per field, and 1 bit indicating Reed Solomon information. A total of 8 bits need to be transmitted in this example. If each bit is encoded with 8 bits, a total of 64 bits are needed for the field sync segment (ie 8 ² ). Since this will occupy most of the bits reserved in data segment synchronization, a way to reduce the number of bits occupied by these bits is to split the encoded bits into two groups of 32 bits each. Group 1 will be sent during even field transmission (e.g., when the center PN63 of the A53 ATSC standard is not inverted) and another 32 bits can be sent during odd field transmission (when the central PN63 is inverted). Therefore, the current field sync sequence structure is utilized to reduce the number of bits needed to transmit per field.

An alternative technique may require the addition of one encoded bit conveying the type information conveyed by the group of bits. Thus, the group of bits need not be bound to the type of field sync.

While it has been shown and described what are considered preferred embodiments of the invention, it will be appreciated that various modifications and changes can be made in form or detail without departing from the spirit of the invention. Therefore, it is intended that the invention not be limited to the form as described and illustrated, but encompass all modifications that come within the scope of the appended claims.

According to the present invention, in an ATSC digital transmission system, a technique is provided for transmitting new robust bit streams along with a standard ATSC bit stream, where the new bit stream has a lower visibility threshold compared to an ATSC stream and thus has priority. Can be used to transmit high information bits.

In addition, there is provided a flexible ATSC digital transmission system and method that is backward compatible with current digital receiver devices, and a flexible ATSC digital transmission system that provides a parity byte generator mechanism for enabling reverse encryption with current receiver devices. A method is provided.

Claims (25)

A digital signal transmission system (201, 300) for transmitting encoded data packets comprising regular packets for transmission as a regular bit stream and robust packets containing information for transmission as a robust bit stream, A first forward error correction (FEC) unit (110) for encoding packets belonging to each of said robust and regular bit streams; A robust processor unit (115, 205) for receiving robust packets (207) containing priority data and for processing the packets to generate the robust bit stream; A trellis encoder unit 330 for generating a stream of trellis encoded data bits corresponding to the bits of the regular and robust streams, the encoder according to one or more symbol mapping schemes; Said trellis encoder unit (330) employing means (380) for mapping encoded data bits of robust packets to symbols (R); An optional second forward error correction (FEC) encoding unit for guaranteeing backward compatibility with the receiver apparatus by reading only packets of the robust bit stream to enable generation of parity bytes only for the robust stream packets; 125); A transmitter device (160, 170, 180) for transmitting the robust bit streams to the receiver device (200) in a backward compatible manner separately from or in conjunction with the regular bit stream on a fixed bandwidth communication channel, The receiver device comprises a current receiver device (200) capable of receiving and processing packets of the robust bit stream as null packets. The method of claim 1, And the receiver device comprises a new receiver device capable of receiving and processing packets of the robust bit stream with a lower TOV compared to a standard bit stream. The method of claim 1, The robust processor unit 115, 205, 400 for processing the robust packets, An apparatus (401) for receiving the robust packets and interleaving the robust packets of an input data stream; Whether or not backward compatibility with the current receiver device is selected, including a packet formatter device 402 for processing robust packets 450 according to the symbol mapping scheme employed for the robust packets, The formatter device 402 reads the robust bytes 411 from the robust interleaver and corresponds to each robust packet 450 to facilitate robust encoding in the trellis encoder unit. Means for generating two or more data blocks (412a, 412b). The method of claim 3, wherein The packet formatter 402, Means for arranging information bits of each robust byte in the least significant bit (LSB) positions of the two or more data blocks 412a, 412b for robust encoding in the trellis encoder unit. Including, The remaining bits in the most significant bit (MSB) positions are subsequently determined based on the symbol mapping scheme employed. The method of claim 4, wherein The packet formatter is configured to eventually receive the parity bytes provided by the second FEC encoding unit 125 when selected to ensure backward compatibility at various locations in each of the two or more data blocks. Means for inserting the placeholder bytes (460a, 460b) of the digital signal transmission system. The method of claim 5, The packet formatter 402 further includes means for inserting three header bytes 454 into each data block to identify the packet at a receiver device, Placeholder bytes comprise a predetermined location in each of the two or more data blocks (451, 452) for eventually receiving the three header bytes. The method of claim 5, The placeholder bytes are inserted at one or more positions including byte positions interspersed over each data block 451, 452, And the one or more locations of placeholder bytes in each of the data blocks are positioned to result in placement of parity bytes at byte locations adjacent to the end of the packet when interleaved. The method of claim 6, A parity byte generator device 125 for de-interleaving the bytes obtained after trellis encoding for robust packets 330 when selected to ensure backward compatibility, The generator further obtains parity byte position information 460a, 460b, 460c for each robust packet, generates the parity bytes from the second FEC unit, and generates the parity byte at the placeholder positions in the robust packet. A digital signal transmission system for placing parity bytes. The method of claim 1, And a multiplexer device (405, 210) for multiplexing regular stream packets with robust packets according to a predefined algorithm. The method of claim 1, The one or more symbol mapping schemes 370, 380 include one selected from the group comprising a pseudo 2-VSB symbol mapping scheme, a 4-VSB symbol mapping scheme, and an H-VSB mapping scheme. system. The method of claim 1, Wherein the parity bytes are mapped to one of 8-VSB levels according to the Advanced Television Systems Committee (ATSC) standard 8-VSB bit stream standard. A method (201, 300) for transmitting a digital signal comprising encoded data packets comprising regular packets for transmission as a regular bit stream and robust packets containing information for transmission as a robust bit stream , a) encoding packets belonging to each of said robust and regular bit streams in a first forward error correction (FEC) unit 110; b) receiving robust packets containing priority data and processing the packets to generate the robust bit stream (115, 205); c) generate a stream of trellis encoded data bits corresponding to the bits of the regular and robust streams (330), and trellis encoded the robust packets according to one or more symbol mapping schemes. Mapping (380) data bits to symbols; d) backward compatibility with the receiver device is achieved by reading only packets of the robust bit stream in a second forward error correction (FEC) encoding unit 125 to enable generation of parity bytes only for the robust stream packets. Optionally assuring; e) transmitting (160, 170, 180) the robust bit streams to a receiver device (200) in a backward compatible manner separately from or in conjunction with the regular bit stream on a fixed bandwidth communication channel; Current receiver apparatus (200) is capable of receiving and processing packets of the robust bit stream as null packets. The method of claim 12, And the receiver device comprises a new receiver capable of receiving and processing packets of the robust bit stream at a lower TOV than a standard bit stream. The method of claim 12, The step 400 of processing the robust packets, Receiving the robust packets and interleaving the robust packets of an input data stream (401); Formatting 402 robust packets according to the symbol mapping scheme 380 used for the robust packets, whether or not backward compatibility with the current receiver device has been selected, The formatting step reads the robust bytes 411, 450 from the interleaver and corresponds to each robust packet 450 so as to facilitate robust encoding at the trellis encoder unit. Generating the above data blocks (412a, 412b). The method of claim 14, The formatting step further comprises arranging the information bits of each robust byte at least significant bit (LSB) positions of the two or more data blocks for robust encoding at the trellis encoder unit, And subsequently determining the remaining bits at the most significant bit (MSB) positions is based on the symbol mapping scheme employed. The method of claim 14, The packet formatting step is performed to the second FEC encoding unit 125 when selected to ensure backward compatibility at various locations in each of the two or more data blocks 451 ', 452', 453 '. Inserting a plurality of placeholder bytes (460a, 460b, 460c) for eventually receiving the parity bytes provided by the digital signal transmission method. The method of claim 16, The packet formatting step further includes inserting three header bytes 454 into each data block 451 ', 452', 453 'to identify the packet at the receiver device, Placeholder bytes include a predetermined location in each of the two or more data blocks for eventually receiving the three header bytes. The method of claim 16, The plurality of placeholder bytes are inserted at one or more positions including byte positions interspersed over each data block, And wherein said one or more locations of placeholder bytes in each said data block are positioned to result in placing parity bytes at byte locations adjacent to the end of said packet in a subsequent interleaving step. The method of claim 17, De-interleaving the bytes obtained after trellis encoding for robust packets when selected to ensure backward compatibility; Obtaining parity byte position information for each robust packet; Generating the parity bytes from the second FEC unit; Placing the parity bytes in the robust packet at the placeholder positions. The method of claim 12, Multiplexing (210, 405) regular stream packets with robust packets according to a predefined algorithm. The method of claim 12, The step of mapping trellis encoded data bits of the robust packets to symbols includes symbol mapping selected from the group comprising a pseudo 2-VSB symbol mapping scheme, a 4-VSB symbol mapping scheme, and an H-VSB mapping scheme. Using a scheme (370, 380). A high definition digital television signal transmission system 201, 300 for transmitting encoded MPEG-compliant data packets for reception by a digital television receiver device, wherein the packets are regular bits and robust bits for transmission as a regular bit stream. A high definition digital television signal transmission system comprising robust packets containing information for transmission as a stream, comprising: A first forward error correction (FEC) encoding unit (110) for formatting packets belonging to each of said robust and regular bit streams; A robust processor unit (115, 205) for receiving robust packets (207) containing priority data to generate the robust bit stream and for processing the packets; A trellis encoder unit 330 for generating a stream of trellis encoded data bits corresponding to the bits of the regular and robust streams, the encoder according to one or more symbol mapping schemes; Said trellis encoder unit (330) employing means (380) for mapping encoded data bits of robust packets to symbols; An optional second forward error correction (FEC) encoding unit for guaranteeing backward compatibility with the receiver apparatus by reading only packets of the robust bit stream to enable generation of parity bytes only for the robust stream packets; 125); A digital television signal transmitter device (160, 170, 180) for transmitting said robust bit streams to a receiver device (200) separately or together with said regular stream on a fixed bandwidth communication channel; Means for transmitting bits for reception by the receiver apparatus comprising information enabling the receiver to correctly decode robust packet symbols according to the symbol mapping scheme employed; The current receiver device 200 can receive and process the packets of the robust bit stream as null packets, and the new receiver device receives and processes the packets of the robust bit stream with a lower TOV compared to the standard bit stream. High-definition digital television signal transmission system that can handle. The method of claim 22, The transmitted bits for reception by the receiver device 200 include information bits that characterize the digital signal transmission mode according to the number of robust packets, modulation type, and redundant level inserted for trellis encoding. , High-definition digital television signal transmission system. The method of claim 22, Each said transmitted information bit is spread spectrum encoded prior to transmission, said bits being encoded for transmission in a reserved bit portion of a data field sync segment (138). The method of claim 22, The mode information bits indicate a symbol mapping technique employed for the robust packets, The symbol mapping techniques 370, 380 include one selected from 2-VSB, 4-VSB and H-VSB symbol mapping modes, and an indication of whether the optional second FEC encoding unit was used. Television signal transmission system.