CA2404404A1 - An improved digital transmission system for an enhanced atsc 8-vsb system - Google Patents

An improved digital transmission system for an enhanced atsc 8-vsb system Download PDF

Info

Publication number
CA2404404A1
CA2404404A1 CA 2404404 CA2404404A CA2404404A1 CA 2404404 A1 CA2404404 A1 CA 2404404A1 CA 2404404 CA2404404 CA 2404404 CA 2404404 A CA2404404 A CA 2404404A CA 2404404 A1 CA2404404 A1 CA 2404404A1
Authority
CA
Canada
Prior art keywords
robust
packets
bytes
stream
packet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA 2404404
Other languages
French (fr)
Inventor
Dagnachew Birru
Vasanth R. Gaddam
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US32448201P priority Critical
Priority to US60/324,482 priority
Priority to US10/127,531 priority
Priority to US10/127,531 priority patent/US7111221B2/en
Application filed by Koninklijke Philips NV filed Critical Koninklijke Philips NV
Publication of CA2404404A1 publication Critical patent/CA2404404A1/en
Application status is Abandoned legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network, synchronizing decoder's clock; Client middleware
    • H04N21/438Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving MPEG packets from an IP network
    • H04N21/4382Demodulation or channel decoding, e.g. QPSK demodulation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/20Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
    • H04N21/23Processing of content or additional data; Elementary server operations; Server middleware
    • H04N21/238Interfacing the downstream path of the transmission network, e.g. adapting the transmission rate of a video stream to network bandwidth; Processing of multiplex streams
    • H04N21/2383Channel coding or modulation of digital bit-stream, e.g. QPSK modulation

Abstract

A digital transmission system and method that improves upon the ATSC A/53 H1DTV signal transmission standard includes: a first forward error correction (FEC) unit for encoding packets belonging to each of robust and normal data bit streams; a robust processor unit for receiving robust packets comprising priority data and processing the packets for generating the robust bit stream; a trellis encoder unit for producing a stream of trellis encoded data bits corresponding to bits of the normal and robust streams, the encoder employing mapping of encoded data bits of said robust packets into symbols according to one or more symbol mapping schemes; and, an optional second forward error correction (FEC) encoding unit for ensuring backward compatibility with a receiver device by reading in only packets of the robust bit stream and enabling generation of parity bytes only for the robust stream packets; and, a transmitter device for transmitting the robust bit streams in a backwards compatible manner, separately or in conjunction with said normal bit stream over a fixed bandwidth communications channel to a receiver device, wherein an existing receiver device is capable of receiving and processing packets of the robust bit stream as null packets.

Description

1 ' 28.08.2002 An improved digital transmission system for an enhanced ATSC 8-VSB system The present invention relates to digital signal transmission systems and particularly, to the Advanced Television Systems Committee (ATSC) Digital Television (DTV) standard (A/53). The invention describes a method for transmitting a robust bit-stream along with the standard bit-stream using the ATSC standard in a backward compatible manner.
The ATSC standard for high-definition television (HDTV) transmission over terrestrial broadcast channels uses a signal that comprises a sequence of twelve (12) independent time-multiplexed trellis-coded data streams modulated as an eight (8) level vestigial sideband (VSB) symbol stream with a rate of 10.76 MHz. This signal is converted to a six (6) MHz frequency band that corresponds to a standard VHF or UHF
terrestrial television channel, over which the signal is broadcast at a data rate of 19.39 million bits per second (Mbps). Details regarding the (ATSC) Digital Television Standard and the latest revision A/53 is available at htt~//www.atsc.or~/.
Fig. 1 is a block diagram generally illustrating an exemplary prior art high definition television (HDTV) transmitter 100. MPEG compatible data packets are first randomized in a data randomizer 105 and each packet is encoded for forward error correction (FEC) by a Reed Solomon (RS) encoder unit 110. The data packets in successive segments of each data field are then interleaved by data interleaver 120, and the interleaved data packets are then further interleaved and encoded by trellis encoder unit 130. Trellis encoder unit 130 produces a stream of data symbols having three (3) bits each. One of the three bits is pre-coded and the other two bits are produced by a four (4) state trellis encoder.
The three (3) bits are then mapped to an 8-level symbol.
As known, a prior art trellis encoder unit 130 comprises twelve (12) parallel trellis encoder and pre-coder units to pravide twelve interleaved coded data sequences. In multiplexer 140 the symbols of each trellis encoder unit are combined with "segment sync"
ar.~d "field sync" synchronization bit sequences 150 from a synchronization unit (not shown).
A small in-phase pilot signal is then inserted by pilot insertion unit 160 and optionally pre-2 28.08.2002 equalized by filter device 165. The symbol stream is then subjected to vestigial sideband (VSB) suppressed carrier modulation by VSB modulator 170. The symbol stream is then finally up-converted to a radio frequency by radio frequency (RF) converter 180.
Fig. 2 is a block diagram illustrating an exemplary prior art high definition television (HDTV) receiver 200. The received RF signal is down-converted to an intermediate frequency (IF) by tuner 210. The signal is then filtered and converted to digital foam by IF filter and detector 220. The detected signal is then in the form of a stream of data symbols that each signify a level in an eight (8) level constellation. The signal is then provided to NTSC rejection filter 230 and to synchronization unit 240. Then the signal is filtered in NTSC rejection filter 230 and subjected to equalization and phase tracking by equalizer and phase tracker 250. The recovered encoded data symbols are then subjected to trellis decoding by trellis decoder unit 260. The decoded data symbols are then further de-interleaved by data de-interleaver 270. The data symbols are then subjected to Reed Solomon decoding by Reed Solomon decoder 280. This recovers the MPEG compatible data packets transmitted by transmitter 100.
While the existing ATSC 8-VSB A/53 digital television standard is sufficiently capable of transmitting signals that overcome numerous channel impairments such as ghosts, noise bursts, signal fades and interferences in a terrestrial setting, there exists a need for flexibility in the ATSC standard so that streams of varying priority and data rates may be accommodated.
It is thus an object of the present invention to provide in an ATSC digital trmsmission system, a technique for transmitting a new robust bit-streams along with the standard ATSC bit-stream, wherein the new bit-stream has a lower Threshold of Visibility (T'OV) compared to the ATSC stream, and consequently can be used for transmitting high priority information bits.
It is a fiuther object of the present invention to provide a flexible ATSC
digital transmission system and methodology that is backward compatible with existing digital receiver devices.
It is another object of the present invention to provide a flexible ATSC
digital transmission system and methodology that provides a parity-byte generator mechanism for enabling backwards compatibility with the existing receiver devices.

P~fUS010464 3 28.08.2002 In accordance with the preferred embodiments of the invention, there is provided a digital transmission system and method that improves upon the ATSC

HDTV signal transmission standard and includes:
- a first forward error correction (FEC) encoding unit for formatting packets belonging to each of robust and normal data bit streams;
- a robust processor unit for receiving robust packets comprising priority data and processing the packets for generating the robust bit stream;
- a trellis encoder unit for producing a stream of trellis encoded data bits corresponding to bits of the normal and robust streams, the encoder employing mapping of encoded data bits of said robust packets into symbols according to one or more symbol mapping schemes; and, - an optional second forward error correction (FEC) encoding unit for ensuring backward compatibility with a receiver device by reading in only packets of the robust bit stream and enabling generation of parity bytes only for the robust stream packets; and, a transmitter device for transmitting the robust bit streams in a backwards compatible manner, separately or in conjunction with said normal bit stream over a fixed bandwidth communications channel to a receiver device, wherein an existing receiver device is capable of receiving and processing packets of the robust bit stream.
To insure backward compatibility with existing receivers from various manufacturers, an optional non-systematic Reed-Solomon encoder is employed to add the parity bytes to the robust bit-stream packets. The standard 8-VSB bit-stream will be encoded using the ATSC FEC scheme (A/53). Packets transmitted using the new bit-stream will be ignored by the transport layer decoder of the existing receiver.
Details of the invention disclosed herein shall be described below, with the aid of the figures listed below, in which:
Fig. 1 illustrates a block diagram of an exemplary high definition television (HDTV) transmitter according to the prior art;
Fig. 2 illustrates a block diagram of an exemplary high definition television (HDTV) receiver according to the prior art;
Fig. 3 is a top-level diagram of a first embodiment 201 of the improved ATSC
standard according to the present invention.

PFiLJS010464 4 28.08.2002 Fig. 4 is a top-level diagram of a second embodiment 300 of the improved A'CSC standard according to the present invention.
Fig. 5 is a block diagram illustrating a trellis encoding scheme 330 implemented in the transmission systems of Figs. 3 and 4.
Fig. 6 is a simplified block diagram illustrating the outer coding circuit 335 of the modified trellis encoder 330 according to the invention.
Fig. 7 illustrates in detail the Robust packet interleaver block 400 which is shown including an interleaver 401 and a packet formatter unit 402;
Figs. 8(a) and 8(b) illustrate the basic formatter function of duplicating the bytes of a packet into two bytes when MODE=2 or 3, and respectively for the case when NRS= 0 (Fig. 8(a)) and NRS= 1 (Fig. 8(b));
Figs. 9(a) and 9(b) illustrate the basic formatter function of rearranging the bits of an input packet into two bytes when the MODE = 1, and respectively for the case when NRS= 0 (Fig. 9(a)) and NRS= 1 (Fig. 9(b)); and, Fig. 10 illustrates the parity 'place-holder' insertion mechanism for an example scenario.
A new approach for the ATSC digital transmission system standard comprising the means and methodology for transmitting a new "robust" bit-stream along with the standard ATSC (8-bit) bit-stream, wherein the new bit-stream has a lower Threshold of Visibility (TOV) compared to the standard 8-VSB ATSC stream, and consequently can be used for transmitting high priority information bits, is described in co-assigned, co-pending United States Patent Application No. 10/078933 [US010173, Attorney Docket No.15062]
entitled Improved ATSC digital television system, the whole contents and disclosure of which is incorporated by reference as if fully set forth herein.
Most notably, the new features provided with the proposed ATSC digital tr<~nsmission system and methodology described in herein incorporated co-pending United States Patent Application No. 60/280782 [US010173, Attorney Docket No.15062], include the mechanism for enabling a trade-off of the standard bit-stream's data rate for the new bit-stream's robustness which will enable new receiver devices to decode robust packets without errors even under severe static and dynamic multi-path interference environments at a reduced CNR and reduced TOV, and further, a mechanism that enables backward compatible transmission with existing digital receiver devices. The system described particularly PIiUS010464 28.08.2002 improves upon the current ATSC digital transmission system standard by enabling flexible transmission rates for Robust and Standard streams for accommodating a large range of cwrier-to-noise ratios and channel conditions.
Fig. 3 is a top-level diagram of a first embodiment 201 of the improved ATSC

5 standard according to the present invention. As shown in Fig. 3, the improved ATSC digital signal transmission standard according to a first embodiment includes the data randomizer element 105 for first changing the input data byte value according to a known pattern of pseudo-random number generation. According to the ATSC standard, for example, the data randomizer XORs all the incoming data bytes with a 16-bit maximum length pseudo random binary sequence (PRBS) which is initialized at the beginning of a data field.
The output r~~ndomized data is then input to the Reed Solomon (RS) encoder element 110 which operates on a data block size of 187 bytes, and adds twenty (20) RS parity bytes for error correction to result in a RS block size total of 207 bytes transmitted per data segment. It is these bytes that will then be post processed and sent using robust constellations. After the RS
encoding, the 2~D7 byte data segment is then input to a new block 115 comprising a robust interleaves, packet formatter and packet multiplexor elements for further processing/reformatting the robust input bytes. Details regarding the operation of the individual elements of the packet formatter block is described in greater detail in herein incorporated co-pending United States Patent Application No. 10/078933 [Attorney Docket No.US010173, D#15062] and, in commonly owned, co-pending United States Patent Application Serial No.

[Attorney Docket No. US010278, D#15061] entitled Packet identification mechanism at the tt~ansmitter and receiver for an enhanced ATSC 8-VSB system, the whole contents and disclosure of which is incorporated by reference as if fully set forth herein.
Most generally, the robust interleaves, packet formatter and packet multiplexor elements for reformatting incoming bytes are responsive to a mode signal 113 which indicates whether the incoming byte is processed (for robust bytes) or not (for normal bytes). After interleaving robust packets in the robust interleaves, the data bytes belonging to the incoming robust bit-stream are buffered and grouped in the packet formatter device into groups of a pre-defined number of bytes, e.g., 207 bytes. In general, for robust packets, only 4 bits of each byte at the packet fi~rmatter output, the LSBs (6,4,2,0), correspond to the incoming stream. The other 4 bits of each byte, the MSBs (7,5,3,1), may be set to any value for reasons as will be explained in greater detail herein. After byte re-formatting in the packet formatter 115, the bytes belonging to robust packets are multiplexed with the bytes belonging to the standard stream.
The multiplexed stream 116 of robust and standard bytes are next input to the convolutional 6 28.08.2002 interleaves mechanism 120 where data packets in successive segments of each data field are further interleaved for scrambling the sequential order of the data stream according to the A'CSC A/53 standard. As will be explained in greater detail, bytes associated with each robust packet or standard packet is tracked in concurrent processing control blocks (not shown). As S fiurther shown in Fig. 3, the interleaved, RS-encoded and formatted data bytes 117 are then trellis coded by a novel trellis encoder device 330. Trellis encoder unit 330 is particularly responsive to the mode signal 113 and cooperatively interacts with a backwards compatibility parity-byte generator element 125, herein referred to as a backward compatibility (optional R;i encoder) block 125 in the manner as will be explained in greater detail herein, to produce an output trellis encoded output stream of data symbols having three (3) bits each mapped to an 8-level symbol. The trellis encoded output symbols are then transmitted to multiplexor unat 140 where they are combined with the "segment sync" and "field sync"
synchronization bit sequences 138 from a synchronization unit (not shown). A pilot signal is then inserted by the pilot insertion unit 160. The symbol stream is then subjected to vestigial sideband (VSB) suppressed corner modulation by VSB modulator 170 and the symbol stream is then finally up~-converted to a radio frequency by the radio frequency (RF) converter 180.
Fig. 4 is a top-level diagram of a second embodiment 300 of the improved A'TSC standard according to the present invention. As shown in Fig. 4, the improved ATSC
digital television transmission standard according to the second embodiment includes identical functioning blocks as the first embodiment depicted in Fig. 3, however, the front en.d of the system 300 of Fig. 4 comprises new blocks including a Robust processor element 205 for processing bytes belonging to a robust packets received from an input robust bit stream 207 and forwarding them into an MPEG multiplexor unit 210, which additionally receives bytes belonging to a normal (standard) bit stream 208. The multipiexor unit 210 multiplexes robust and standard packets for input to the standard data randomizer element 1 CIS that changes the input data byte values according to pseudo-random generated patterns, for instance. The output randomized data are then input to the Reed Solomon (RS) encoder element 110 which operates on a data block size of 187 bytes, for instance, and adds twenty (20) RS parity bytes for error correction to result in a RS block size total of 207 bytes transmitted per data segment. After the RS encoding, the 207 byte data segments 214 are then input to an optional byte permute block 215 which further processes only the packets of a robust bit stream and passes the normal packets unaltered. This byte permute block 21 S
functions to replace the parity bytes added by the preceding RS encoder block 110 with zesroes, and permutes the 207 bytes such that after the data interleaves, the 184 data bytes 7 28.08.2002 created by the robust processor (excluding the header bytes) will come before the parity bytes. As shown in Fig. 4, the new byte permute block 215 is particularly responsive to the mode signal 113 which indicates whether the incoming bytes will be processed by this block or not. As in the first approach described with respect to Fig. 3, data segments of robust and standard bytes 216 output from the byte permute block 215 are next input to the convolutional interleaves mechanism 120 where data packets in successive segments of each data field are further interleaved for scrambling the sequential order of the data stream according to the ATSC A/53 standard. As further shown in Fig. 4, the interleaved, RS-encoded and formatted data bytes 217 are then trellis coded by a novel trellis encoder device 330. As described in greater detail herein, the trellis encoder unit 330 cooperatively interacts with a backwards compatibility (optional RS encoder) block 125, to produce an output trellis encoded output stream of data symbols having three (3) bits each mapped to an 8-level symbol. The trellis encoded output symbols are then transmitted to multiplexor unit 140 where they are combined with the "segment sync" and "field sync"
synchronization bit sequences 138 from a synchronization unit (not shown). The pilot signal is then inserted by the pilot insertion unit 160, the symbol stream is then subjected to vestigial sideband (VSB) suppressed carrier modulation by VSB modulator 170 and, the symbol stream is up-converted to a radio frequency by the radio frequency (RF) converter 180.
As shown in Fig. 4, the Robust processor element 205 includes an input for receiving the MPEG data packets 207 to be communicated as a robust stream.
This robust processor block 205 includes the following components: a Reed-Solomon encoder, followed by an interleaves device, and, followed with a formatter block to form 188-byte length packets (MPEG compatible packets). The last block (MPEG packet formation) inserts redundancy bits to form a 184-byte packet, then adds four (4) MPEG header bytes to form a complete 188 MPEG packet. The robust packets 206 out of the processor block 205 are multiplexed with normal packets of the MPEG packet stream 208 for transmission as an A'TSC stream 209 comprising both normal and robust packets, via MPEG
multiplexor device 210. Preferably, the normal stream packets are multiplexed with the robust packets according to a pre-defined algorithm, an exemplary algorithm of which will be described in greater detail herein. For purposes of discussion, and, as explained in greater detail in commonly-owned, co-pending United States Patent Application Serial No. 10/118876 [Attorney Docket No. US010278, D#15061], the contents and disclosure of which is incorporated by reference as if fully set forth herein, a control mechanism is provided for tracking the type of packets transmitted, i.e., normal or robust. Thus, as shown in Fig. 3 and 4, associated with each byte P:HUS010464 28.08.2002 there is generated a normal/robust ("N/R") signal which comprises a bit 211 used to track the progression of the bytes and identify the bytes in the enhanced ATSC digital signal transmission scheme.
Generally, for the embodiment of the ATSC system described with respect to Fig. 4, transmission of robust packets requires knowledge of the manner by which the robust packets 206 are multiplexed with the normal packets 208 at the MPEG
multiplexor element 210. The packets need to be inserted in such a manner that they improve the dynamic and static multipath performance of a receiver device. One exemplary algorithm governing the rrmltiplexing of robust stream packets with the normal stream packets in the robust processor block 205 of Fig. 4, is now described with respect to the Table 1. The packet insertion algorithm is enabled to exploit the robust packets to enable better and robust receiver design.
At the beginning of an MPEG field, a group of robust packets is placed contiguously, then the rest the packets are inserted using a predetermined algorithm, as now described with respect to Table 1. The first group of packets will help the equalizer in faster acquisition in both static and dynamic channels. This robust packet insertion algorithm is irnplemented before interleaving for every field. With respect to the example robust packet insertion algorithm of Table 1, the following quantities and terms are first defined: a first quantity referred to as "NRP" represents the number of robust segments occupied by robust packets per field (i.e., indicates the Number of Robust Packets in a frame);
the quantity referred to as "M" is the number of contiguous packet positions occupied by robust bit-sixeam immediately following the field sync; the character "U" represents the union of two sc;ts; and, "floor" represents the truncation of a decimal so that values are rounded to an integer value. As shown in Table 1, the algorithm comprises performing the following evaluations to determine the placement of the robust packet in the bit stream:

9 28.08.2002 If 0<NRP<_M,then robust packet position =
{0, 1, . .., NRP-1 }
I:f M < NRP S floor((312-M)/4)+M, then robust packet position =
{0, 1, ..., M-1 } U {M+4i, i = 0, l, ..., (NRP - M-1)}
If floor((312-M)/4)+M < NRP <_ floor((312-M-2)/4)+floor((312-M)/4)+M, then robust packet number =
{0, l, . . ., M-1 } U {M+4i, i = 0, 1, . . ., floor((312-M)/4) -1 } U {M+2+4i, i =
0, 1, ..., NRP - (floor((312-M)/4)+M) - 1 }
If floor((312-M-2)/4)+floor((312-M)/4)+M < NRP <_ 312, then robust packet number =
{ 0, 1, ..., M-1 } U {M+4i, i = 0, l, ..., floor((312-M)/4) -1 } U {M+2+4i, i =
0, 1, ..., floor((312-M-2)/4)-1 } U {M+1+2i, i =
0, 1, .. ., NRP - (M+ floor((312-M)/4) + floor((312-M-2)/4))-1 }
Table 1 Thus, in an example implementation for the case when M=18, the above algorithm results in the following algorithm for robust packet placement:
If 0<NRP <_ 18, then robust packet position = {0, 1, . . ., NRP-1 }
If 18 < NRP <_ 91, then robust packet position = {0, 1, ..., 17} U{18+4i, i = 0, 1, ..., (NRP -19)};
If 91 < NRP <_ 164, then robust packet position = {0, 1, .. ., 17} U { 18+4i, i = 0, 1, .. ., 72}
U {20+4i,i = 0, 1,..., NRP - 92}
If 164 < NRP 5 312, then robust packet position = { 0, 1, ..., 17} U {18+4i, i = 0, 1, ..., 72} U
{20+4i,i = 0, l, ..., 72}
U {19+2i, i = 0, 1, ..., NRP - 165}

28.08.2002 In each of the first and second embodiments of Figs. 3 and 4, a backward compatibility Parity Byte Generator element 125 (additionally referred to as the optional non-systematic RS encoder) is provided to read bytes from the trellis decoder.
Particularly, this block 125 comprises a byte de-interleaves block and an optional "non-systematic" RS
5 encoder block for reading in a packet from the byte de-interleaves block and then RS
encoding it to generate the parity bytes. It generates the parity bytes only for robust stream packets used for backward compatibility. An exemplary algorithm used to perform this function is now provided with respect to Table 2:
L>efine an array 'data bytes' of size 52 X 207, vutialize the variables 'byte no', 'row no', 'col no', 'row add' to zero, IjFbyte_no = 207*52 then set the 'read flag' and 'start flag' to 1, If start flag = 1 then set read flag =1 every 208 bytes (see packet formatter block description for exceptions to this rule), If start_flag = 1 then read out a packet in order whenever read flag is set beginning v~rith packet 0 (row no = 0), Place the message byte (output of trellis encoder) in data bytes[row no][col no]
W crement byte no if 'byte stb' (signal from the trellis encoder) = 1, Update 'row no' and 'col no' variables using the following conditional logic hP byte no = 207* 52 then byte no = 0;
row add = 0;
col no = 0;
row no = 0;
Else if (byte no mod 208) = 0 then row add = (row add+1 ) mod 52;
col no = row add;
row no = row add;
F'or all other cases col no = (col no+52) mod 207;
row no = (row no-1) mod 52; (if row no-1 < 0 then add 52 to the result) CTo to step 3 10 Table 2 PI~LJS010464 11 28.08.2002 For some packets (e.g., 1 to 7 mod 52), it will be necessary to have prior information about the randomized header bytes, since not all the header bytes for these packets will be available at the time of RS encoding. That is, for this set of packets, it is the case that some of the header bytes follow the parity bytes at the convolutional interleaver output. Therefore, instead of waiting for these header bytes to calculate the 20 parity bytes, prior information about the header bytes is used (they are deterministic) which are then used instead to calculate the parity bytes.
As explained in the book "Error Control Techniques for Digital Communication", 1984, John Wiley, NY. by Arnold Michelson & Allen Levesque, an (N, K) R;i decoder can correct up to (N 112 errors or erasure fill up to {N I~
erasures, where " N "is code word length and " K " is message word length. In general, if there are EQ
erasures and Eb errors in a code word of length N, then the decoder can completely recover the code word as long as (Ea + 2*Eb) is less than or equal to (N K) as set forth in equation ( 1 ) as follows:
~Ea+2xEb)<_(N-K) (1) where Ep and Eb are the number of erasures and number of errors in the code word respectively.
This property of RS codes may be used to generate the 20 parity bytes. The 20 panty byte locations are then calculated for use as the erasures' location for the RS decoder.
The procedure for the calculation of the parity byte locations is similar to the one used in the packet formatter. The bytes belonging to a packet {with zeroes in parity byte locations) are passed on to the RS decoder as the input code word. The decoder, in the process of erasure filling, calculates the bytes for the erasure locations. These bytes correspond to the 20 parity bytes. Thus, the Parity byte Generator block also generates the parity byte location in:fonnation. The parity bytes and the header bytes are always encoded as standard 8-VSB
symbols.
The parity bytes and their location information for each packet are then sent to a modified trellis encoder device for mapping robust bytes according to new symbol mapping schemes. It should be understood that, for some packets (e.g., packets 1 to 7), it is necessary to have prior infornation about the randomized header bytes, since all the header bytes for these packets will not be available at the time of RS encoding.
The top-level operation of the modified trellis encoder is governed by the hale described in section 4.2.5 of the ATSC A/53 transmission standard. This top-level operation is related to trellis interleaving, symbol mapping, the manner in which bytes are read into 12 28.08.2002 each trellis encoder, etc. Trellis encoding of the normal 8-VSB packets is not altered.
However, the trellis encoder block according to the ATSC A/53 standard is modified in order to perform functions of 1) by-passing the pre-coder if the bytes belong to the robust bit-str~eam; 2) deriving each MSB bit if the byte belongs to the robust stream and then sending the new byte to the 'byte de-interleaver' block; 3) reading the parity bytes from 'byte de-ini:erleaver' block and using them (if they belong to robust stream) for encoding; and 4) utilizing modified mapping schemes to map symbols belonging to the robust bit-stream. It should be understood that, preferably, parity bytes are mapped onto eight (8) levels.
With regard to the functions of bypassing the pre-coder and forming the byte, this process is mode dependent as will now be described with respect to modified trellis encoder diagrams of Figs. 5 and 6.
Particularly, Fig. 5 is a block diagram illustrating a trellis encoding scheme 330 implemented in the transmission systems of Figs. 3 and 4. For enhanced 8-VSB (E-VSB), or 2-VSB streams, each trellis encoder receives a byte, of which only 4-bits (LSBs) comprise information bits. When a byte that belongs to the robust stream is received by the trellis encoder, the information bits (LSBs, bits (6,4,2,0)), (after encoding for robust modes) are placed on Xi. The bit to be placed on XZ to obtain the particular symbol mapping scheme is then determined. Once X2 and Xl are detenmined, all the bits of a byte are then determined fo:r the purpose of subsequent "non-systematic" RS encoding. This byte is then passed to the backwards compatibility parity-byte generator 125 (i.e., the "non-systematic"
Reed-Solomon encoder) via datalines 355. The parity bytes of the "non-systematic" Reed-Solomon encoder and PID bytes will however be encoded using the 8-VSB encoding scheme. The operation in the upper trellis encoding block 335 of the trellis encoder 330 for each of the digital signal modulation modes is now described with respect to Fig. 6.
The upper trellis encoding block 335 shown in Fig. 6 calculates the pre-coder 360 inputs, X2 and Xl, of the standard trellis encoder block 359, so that the desired symbol mapping or encoding scheme is achieved. For example, these encoding schemes are for the standard 8-VSB, (enhanced) E-VSB and 2-VSB and the "8/2" control bits 353 are provided for indicating the correct encoding (symbol mapping scheme). The output bits of this block are grouped into their respective bytes, and eventually fed into the "non-systematic" RS
encoder block for parity byte generation. The Normal/Robust control bits 211 needed to configure the multiplexers 336a,...,336d in Fig. 6 are provided by the tracking/control mechanism blocks in respective Figs. 3 and 4.

13 28.08.2002 Thus, for the Normal (standard) 8-VSB symbol mapping mode, the input bits X"2 and X'1 received from the previous interleaver block and input to the upper coder 335 of trf;llis encoder 330 are passed unaltered to the normal trellis encoder comprising pre-coder 3fi0 and encoder 370 units. This is achieved by making the N/R bit 211 select the N input of the multiplexers. The 8/2 bit 353 is a further control bit indicating the trellis mapping scheme to be employed when N/R bit is R (robust).
For the 2-VSB mode and 4-VSB symbol mapping modes, the MSB does not carry any information. To satisfy mapping requirements, the Z2 bit is calculated first and then modulo-2 summed with pre-coder memory content 363 (Fig. 5) to derive the MSB
X2. A new b3~te is formed from the calculated MSB and the input information bit Xl. The memory element is then updated with Z2. Thus, in this case, the trellis encoder outputs Z2 and Zl are made equal to the information bit. That is, input XZ is calculated such that, when pre-coded, the output of the pre-coder Z2 equals the information bit. This operation is implemented in the upper coding circuit 335 illustrated in Fig. 6. In addition, X1 is made equal to the information bit. These operations, combined with the existing symbol mapping scheme enabled by trellis encode symbol mapper 380, result in symbols from the alphabet {-7,-5,.5,7}. This is essentially a 2-VSB signal in the sense that the information bit is transmitted as the sign of this symbol. The actual symbol is a valid trellis coded 4-level symbol capable of being decoded by existing trellis decoders. For example, to achieve 2-VSB
encoding, N/R
bit 211 is set to select the R input and the 8/2 switch 353 is set to select the '2' input of the multiplexers 336a,...,336d.
For the Enhanced 8-VSB mode (E-VSB) mode, X2 and Xl correspond to the outputs of the enhanced coder (i.e., upper coder 335). These bits have to be used in forming the bytes instead of the actual inputs. Accordingly, in this mode, Z2 is made equal to the information bit by putting a trellis-coded version of the information bit on Xl. In order to do this, X2 is calculated such that, when pre-coded, it results in the information bit. The information bit is also passed through an additional trellis encoder to produce Xl. Overall, for E 8-VSB, the outer coder 335 and the normal trellis encoder 359 will be equivalent to a higher state (e.g., 16-state) 1/3 rate trellis encoder. The resulting symbol is an 8-level trellis coded symbol. To achieve Enhanced 8-VSB encoding, the N/R bit 211 is set to select the R
input and the 8/2 switch 353 is set to select the "8" input of the multiplexers 336a,...,336d.
In each of these modes, the symbol to byte converter introduces a delay of 12 bytes.

14 28.08.2002 With regard to the function of reading parity bytes from the byte de-interleaver, this is implemented only when NRS = 1 (i.e., non-systematic RS
encoding is implemented). The behavior of this functional unit is the same for different modes. The trellis encoder 330 obtains the parity bytes and their location information for each packet from the parity byte generator 125. The trellis encoder 330 may then determine if a particular byte that it is going to encode belongs to the set of parity bytes. If the byte belongs to the robust stream parity byte set, then it reads a byte from the byte de-interleaver and uses it instead to trellis encode. The symbols generated from the parity bytes are always mapped into eight (8) levels using the original encoding and mapping scheme.
With more particularity, parity 'place-holders' are inserted by the packet formatter element of the transmission systems of Figs. 3 and 4.
Fig. 7 illustrates in greater detail, the Robust packet processor block 400 which is shown including an interleaver 401, a packet formatter unit 402, and a normal/robust multiplexor (N/R MUX) 405. The robust packet interleaver 401 preferably interleaves only the robust packets. The Packet formatter 402 processes the robust packets according to whether the "non-systematic" RS encoder is used to ensure backward compatibility for legacy receivers. If it is determined that NRS=1, then the "non-systematic" RS
encoder is used and the packet formatter 402 reads 184 bytes from the interleaver and splits these bytes into two 184-byte data blocks. In general, only 4 bits of each robust byte, the LSBs (6,4,2,0), correspond to the incoming stream. The other 4 bits of each byte, the MSBs (7,5,3,1), are set to any value. After packet splitting is done, three randomized null packet ID
(or 3 NULL
P1D) bytes are then inserted at the beginning of each of the two 184-byte length data blocks.
Then, twenty (20) "place-holder" parity bytes are added to each data block to create a 207-byte packet. In creating the 207 bytes, the 184 bytes including the information stream and the tv~renty (20) "place-holder" parity bytes are permuted in such a way that after the standard 8-VSB data interleaver, these 20 bytes will appear at the end of the 184 bytes containing the information bits. At this stage, the values of the twenty (20) bytes can be set to zero. This option, incorporated for the purpose of ensuring backward compatibility with legacy receivers, reduces the effective data rate since 23 bytes (20 parity bytes and 3 header bytes) have to be added per packet. The result is about a 12% reduction in payload.
If it is determined that NRS=0, then the "non-systematic" RS encoder is not used. In this case, the packet formatter 402 reads 207 bytes from the interleaver and splits these bytes into two 207-b~~te packets. In general, only 4 bits of each byte, the LSBs (6,4,2,0), correspond to the incoming stream. The other 4 bits of each byte, the MSBs (7,5,3,1 ), can be set to any value.

15 28.08.2002 In both cases, it is understood that the RobustlNormal packet MUX 405 is a packet (207 byte) level multiplexer. It multiplexes the robust and normal packets on a packet-by-packet basis.
The packet formatter's functionality depends on MODE and NRS parameters.
If NRS = 0, then the packet formatter basically performs the fimction of byte duplication or byte rearrangement. If NRS = 1 then it also inserts 'place holders' for the additional header and parity bytes. Table 3 summarizes the packet formatter functionality for different combinations of the MODE and the NRS parameters.
NxtS MODE Number of Number of Functionality input packetsoutput packets 0 2,3 1 2 Byte duplication 0 1 2 2 Rearrange bits 1 2,3 4 9 Byte duplication, Insert "place holders"

1 1 8 9 Rearrange bits, Insert "place holders"

Table 3 where the "MODE" parameter includes specification of the robust packets and is used in identifying the format of the robust packets; and, as mentioned, the "NRS"
parameter indicates whether the non-systematic RS coder is not to be used (when NRS=0) resulting in on.e robust packet being coded into two symbol segments by the FEC block, for example, or, whether the non-systematic RS coder is to be used (when NRS=1) resulting, for example, in a group of four robust packets being coded into nine packet segments by the FEC
block. With respect to the MODE parameter, two bits are preferably used to identify four possible modes:
e.g., MODE 00 indicating a standard stream with no robust packets to be transmitted; MODE
Ol indicating an H-VSB stream; MODE 10 indicating an 4-VSB stream; and MODE 11 inncating a pseudo 2-VSB stream. If MODE = 00 then rest of the parameters may be ignored.
More specifically, the packet formatter block 402 includes three functional units: 1) a basic formatter; 2) a parity byte location calculator; and, 3) a 'place holder' inserter. As shown in Figs. 8(a) and 8(b), when the MODE=2 or 3, and respectively for the case when NRS= 0 16 28.08.2002 (Fig. 8(a)) and NRS= 1 (Fig. 8(b)) MODE = 2 or 3, the basic formatter duplicates the bytes of a packet 411 into two bytes 412a, 412b. If the MODE = 1 as shown in respective Figs. 9(a) and 9(b) for the respective cases of NR.S= 0 (Fig. 9(a)) and NRS= 1 (Fig.
9(b)), the basic fovrmatter rearranges the bits of an input packet. The rearranging of bits is performed in the H-~VSB mode, for example, to ensure that bits 415 belonging to the 'robust stream' always go into MSB bit positions and the bits 417 belonging to the 'embedded stream' always go into LSB bit positions of the reformatted packets 418a, 418b, as shown in Figs.
9(a) and 9(b).
As mentioned, the packet formatter unit 402 of Fig. 7 includes a parity 'place-holder' inserter function. The parity 'place-holder' inserter block is used only when NRS = 1 (i.e., when the additional panty byte generator is used). It specifically transforms eight (8) packets into nine (9) packets by inserting three (3) header bytes and twenty (20) 'place holders' for parity bytes unto each of the eight formed packets. The header bytes are always placed in positions 0, 1 and 2 of each packet, and are scrambled. The byte locations corresponding to the parity byte locations may be first filled with zeroes when formed. All the other remaining byte locations m;ay be filled with the message bytes in order.
Fi,g. 10 illustrates the parity 'place-holder' insertion mechanism for an example scenario (1\fRS=1). The basic formatter converts one data packet 450 of 207 bytes into 414 bytes (i.e., equivalent to two (2) packets). The parity byte place holder locations 460a, 460b and 460c for each packet are then determined according to equation 2) as follows:
m = (52*n + (k mod 52)) mod 207 (2) where m is the output byte number and n is the input byte number, e.g., n = 0 to 206, and k =
0 to 311 corresponds to the packet number. To ensure that the location of the 20 parity bytes for each packet always correspond to the last 20 bytes of that packet, the 'm' values for parity byte locations may be computed for n = 187 to 206 only (these values of n correspond to the last 20 bytes of a packet). As an example, substituting k = 0 and n = 187 to 206 will give parity byte locations for packet 0 as 202, 47, 99, 1 S 1, 203, 48, 100, 152, 204, 49, 101, 153, 205, S0, 102, 154, 206, 51, 103, 155. This indicates that the parity byte PBO
should be placed at location 202 in packet 0 so that its position after the interleaves is 187 in packet 0.
Similarly, parity byte PBI has to be placed at location 47 and so on.
It is observed that for some packets, the parity bytes may fall into packet header positions (m _ ~0, 1 or/and 2), i.e., "m" should not equal to 0. 1 or 2, since the first three locations of a packet are reserved for the three null header bytes. To avoid this situation, the range of 'n' m:ay be increased by the number of parity bytes falling into header positions (up to 3). Thus, when calculating 20 values of "m" for different packet numbers, it is observed that when "k 17 28.08.2002 mod 52" =1-7, some of these "m" values are 0, 1 and/or 2. For instance, when "k mod 52" _ 0, it is observed that none of the "m" values fall in the header bytes' location. In this case, all the 20 "m" values are designated as the parity place holder locations. When "k mod 52" =1, it is observed that one of the "m" values is 0 (which is a header byte). In this case, the "n"
range is extended by 1 such that "n" becomes 186-206. Thus, 21 "m" values are calculated arid those "m" values that fall into header bytes location are discarded. The remaining 20 "m"
values are designated as parity place holder locations. When "k mod 52" = 2, it may be observed that two of the calculated "m" values happen to be 0 and 1 (which are header bytes). In this case, the "n" range is extended by 2 such that "n" is now 185-206. Thus, 22 "rn" values (20 + 2 additional) are calculated and the "m" values that fall into header byte locations are discarded. The remaining 20 "m" values are designated as parity place holder locations. Table 4 gives the packets numbers for all other exception cases. It also gives the ntunber of additional 'm' values to be calculated.
Additional 'm' Range of 'n' Packet values to be number mod calculated 8-51 0 ~ 187-206 Table 4 More particularly, as shown in Fig. 10, as each packet 450 comprises 207 bytes, the basic formatter will split this into two new packets 451, 452 each comprising 207.
The parity placeholder insertion mechanism performed by the packet formatter particularly processes each of the new packets 451,452 to include 20 parity bytes at interleaved locations 460a, 460b,...,etc. and 3 header bytes 454. Thus, from new packets 451, 452, the packet PIiLTS010464 18 28.08.2002 formatter will generate new packets 451 ', 452' so as to accommodate all parity and header bits. Thus, new packet 451' of 207 bytes include 184 bytes of 451, 20 parity place holders and 3 null header bytes 454. As shown in Fig. 10, this implies that one original data packet 450 will be mapped into three new packets 451', 452' and a third 453' with first two completely filled while the third 453' being only partially filled. Before inserting a data byte into the new packet 451', 452',453', the location is checked to see if it belongs to a parity byte. If the location doesn't correspond to any of the parity bytes' location then the data byte is placed in that location. If the location belongs to a parity byte then that byte location is skipped and the next byte position is checked. The process is repeated until all the bytes are placed in the new packets. As a result of this translation, each of the 9 output packets include 92 bytes from the input packets (e.g., input packet 450). In one embodiment, a minimum granularity of 9 segments is chosen for NRP when NRS = 1. When data is read in at the randomizer, 4 packets of a 9-packet block will contain information bytes while the remaining 5 packets will not contain any information. The packet formatter spreads the information in the 4 packets 1 S into 9 packets through the process described above. This ensures that the payload data rate will not be given up any more than is necessary.
With the newly proposed technique of the invention, several bits have to be transmitted to a receiver device so that the receiver device may decode the correct mode of transmission. This mode typically includes the number of robust packets, the type of modulation and the level of redundancy inserted for trellis encoding. This information may be transmitted in the reserved bit portion of the field sync segment 138.
Particularly, in order to reliably detect the transmitted information, additional encoding bits are necessary. According to a preferred embodiment, a spread-spectrum type code is provided to encode each information bit into N bits as now illustrated:
For example, bit 1 may be encoded as b, where b={ 1 1 0 0 1 1 0 0}. In this case N=8. Then, a bit 0 may be encoded as { 1 1 1 1 1 1 1 1 } xor b, resulting in {0 0 1 1 0 0 1 1 } . Each bit is encoded in this manner and inserted in the field sync. Thus, at the HDTV
receiver, standard correlation algorithms may be employed to detect the transmitted bits. This encoding technique provides a means by which detection of the information bits may be achieved under extremely severe interference conditions using simple decoding hardware.
The proposed DTV systems require transmission of a number of bits. For example, 2 bits for representing the modulation type, 1 bit for representing the trellis coding redundancy, 4 bits for representing the number of robust packets per field, and 1 bit for representing Reed-Solomon information. A total of 8 bits need to be transmitted in this PF(LTS010464 19 28.08.2002 example. If each bit is encoded into 8 bits, then a total of 64 bits is needed in the field sync segment (i.e., 82). As this would occupy most of the reserved bits in the data segment sync, th<;n as a way of reducing the number of bits occupied by these bits, the encoded bits may be grouped into two, each of 32-bit length. Then one group will be sent during an even field transmission (e.g., when the middle PN63 of the A53 ATSC standard is not inverted) and the other 32 bits may be sent during the odd field transmission (when the middle PN63 is inverted). In this manner, the existing field sync sequence structure is exploited to reduce the number of bits needed to be transmitted per field.
An alternative technique may require the addition of one (1) encoded bit that conveys the type information carned by the group of bits. In this manner, the group of bits need not be tied with the type of the field sync.
While there has been shown and described what is considered to be preferred embodiments of the invention, it will, of course, be understood that various modifications and changes in form or detail could readily be made without departing from the spirit of the invention. It is therefore intended that the invention be not limited to the exact forms described and illustrated, but should be constructed to cover all modifications that may fall within the scope of the appended claims.

Claims (25)

1. A digital signal transmission system (201,300) for transmitting encoded data packets including normal packets for transmission as a normal bit stream and robust packets comprising information for transmission as a robust bit stream, said system comprising:
- a first forward error correction (FEC) unit (110) for encoding packets belonging to each said robust and normal data bit streams;
- a robust processor unit (115,205) for receiving robust packets (207) comprising priority data and processing said packets for generating said robust bit stream;
- a trellis encoder unit (330) for producing a stream of trellis encoded data bits corresponding to bits of said normal and robust streams, said encoder employing means (380) for mapping encoded data bits of said robust packets into symbols (R) according to one or more symbol mapping schemes;
- an optional second forward error correction (FEC) encoding unit (125) for ensuring backward compatibility with a receiver device by reading in only packets of said robust bit stream and enabling generation of parity bytes only for the robust stream packets;
and, - a transmitter device (160,170,180) for transmitting said robust bit streams in a backwards compatible manner, separately or in conjunction with said normal bit stream over a fixed bandwidth communication channel to a receiver device (200), - wherein a receiver device includes an existing receiver device (200) capable of receiving and processing packets of said robust bit stream as null packets.
2. The digital signal transmission system (300,400) as claimed in Claim 1, wherein said receiver device includes a new receiver device capable of receiving and processing packets of said robust bit stream at a lower TOV compared to the standard bit-stream.
3. The digital signal transmission system as claimed in Claim 1, wherein said robust processor unit (115,205,400) for processing said robust packets comprises:

- a device (401) for receiving said robust packets and interleaving said robust packets of an input data stream; and, - a packet formatter device (402) for processing robust packets (450) in accordance with a symbol mapping scheme employed for said robust packets and, whether backward compatibility with an existing receiver device is optioned;
- said formatter device (402) including means for reading robust bytes (411) fibm the robust interleaver and generating two or more data blocks (412a, 412b) corresponding to each robust packet (450) to facilitate robust encoding in said trellis encoder unit.
4. The digital signal transmission system as claimed in Claim 3, wherein said packet formatter (402) further comprises:
- means for arranging information bits of each said robust byte into least significant bit (LSB) positions of said two or more data blocks (412a, 412b) for robust encoding in said trellis encoder unit, - wherein remaining bits in most significant bit (MSB) positions are subsequently determined based on a symbol mapping scheme employed.
5. The digital signal transmission system as claimed in Claim 4, wherein said packet formatter further comprises means for inserting a plurality of placeholder bytes (460a, 460b) at various locations in each said two or more data blocks, said placeholder bytes for eventually receiving said parity bytes provided by said second FEC encoding unit (125) when optioned to ensure backward compatibility.
6. The digital signal transmission system as claimed in Claim 5, wherein said packet formatter (402) further comprises: means for inserting three header bytes (454) in each data block for identifying the packet at a receiver device, wherein placeholder bytes include a pre-specified location in each said two or more data blocks (451,452) for eventually receiving said three header bytes.
7. The digital signal transmission system as claimed in Claim 5, wherein said placeholder bytes are inserted at one or more locations comprising byte positions dispersed throughout each. data block (451,452), said one or more locations of placeholders bytes in each said data block are located to result in placement of parity bytes in contiguous byte positions at the end of that packet when interleaved.
8. The digital signal transmission system as claimed in Claim 6, further including parity byte generator device (125) for de-interleaving bytes obtained from after trellis encoding for robust packets (330) when optioned to ensure backward compatibility, said generator further obtaining parity byte location information (460a, 460b, 460c) for each robust packet, generating said parity bytes from said second FEC unit, and placing said parity bytes in said robust packet at said placeholder locations.
9. The digital signal transmission system as claimed in Claim 1, further including multiplexor device (405, 210) for multiplexing normal stream packets with the robust packets according to a pre-defined algorithm.
10. The digital signal transmission system as claimed in Claim 1, wherein said one or more symbol mapping schemes (370, 380) includes one selected from the group comprising: a pseudo 2-VSB symbol mapping scheme, 4-VSB symbol mapping scheme, and H-VSB mapping scheme.
11. The digital signal transmission system as claimed in Claim 1, wherein said parity bytes are mapped into one of 8-VSB levels according to Advanced Television Systems Committee (ATSC) standard 8-VSB bit stream standard.
12. A method for transmitting digital signals (201, 300) comprising encoded data packets including normal packets for transmission as a normal bit stream and robust packets comprising information for transmission as a robust bit stream, said method comprising the steps of:
a) encoding packets belonging to each said robust and normal data bit streams in a first forward error correction (FEC) unit (110);
b) receiving robust packets comprising priority data and processing said packets for generating said robust bit stream (115, 205);
c) producing a stream of trellis encoded data bits (330) corresponding to bits of said normal and robust streams, and mapping (380) trellis encoded data bits of said robust packets into symbols according to one or more symbol mapping schemes;

d) optionally ensuring backward compatibility (with a receiver device by reading in only packets of said robust bit stream and enabling generation of parity bytes only for the robust stream packets in a second forward error correction (FEC) encoding unit (125);
and, e) transmitting said robust bit stream (160, 170, 180) in a backwards compatible manner, separately or in conjunction with said normal bit stream over a fixed bandwidth communications channel to a receiver device, wherein an existing receiver device (21)0) is capable of receiving and processing packets of said robust bit stream as null packets.
13. The method for transmitting digital signals as claimed in Claim 12, wherein said receiver device includes a new receiver device capable of receiving and processing packets of said robust bit stream at a lower TOV compared to the standard bit-stream.
14. The method for transmitting digital signals as claimed in Claim 12, wherein said step of processing said robust packets (400) comprises:
- receiving said robust packets and interleaving said robust packets of an input data stream (401); and, - formatting said robust packets (402) in accordance with a symbol mapping scheme (380) employed for said robust packets and whether backward compatibility with a receiver device is optioned, wherein said formatting step includes the step of reading robust bytes (411, 450) from the interleaver and generating two or more data blocks (412a, 412b) corresponding to each robust packet to facilitate robust encoding in said trellis encoder unit.
15. The method for transmitting digital signals as claimed in Claim 14, wherein said formatting step further includes the step of arranging information bits of each said robust byte into least significant bit (LSB) positions of said two or more data blocks for robust encoding in said trellis encoder unit, and subsequently determining remaining bits in most significant bit (MSB) positions are based on a symbol mapping scheme employed.
16. The method for transmitting digital signals as claimed in Claim 14, wherein said packet formatting step further comprises the step of inserting a plurality of placeholder bytes (460a, 460b, 460c) at various locations in each said two or more data blocks (451', 452', 453'), said placeholder bytes for eventually receiving said parity bytes provided by said second FEC encoding unit when optioned to ensure backward compatibility.
17. The method for transmitting digital signals as claimed in Claim 16, wherein said packet formatting step further comprises the step of inserting three header bytes (454) in each data block (451', 452', 453') for identifying the packet at a receiver device, wherein placeholder bytes include a pre-specified location in each said two or more data blocks for eventually receiving said three header bytes.
18.. The method for transmitting digital signals as claimed in Claim 16, wherein said plurality of placeholder bytes are inserted at one or more locations comprising byte positions dispersed throughout each data block, said one or more locations of placeholders bytes in each said data block are located to result in placement of parity bytes in contiguous byte positions at the end of that packet in a subsequent interleaving step.
19. The method for transmitting digital signals as claimed in Claim 17, further including the steps of:
- de-interleaving bytes obtained from after trellis encoding for robust packets when optioned to ensure backward compatibility, - obtaining parity byte location information for each robust packet, - generating said parity bytes from said second FEC unit, and - placing said parity bytes in said robust packet at said placeholder locations.
20. The method for transmitting digital signals as claimed in Claim 12, further including the step of multiplexing (210, 405) normal stream packets with the robust packets according to a pre-defined algorithm.
21. The method for transmitting digital signals as claimed in Claim 12, wherein said step of mapping trellis encoded data bits of said robust packets into symbols includes utilizing a symbol mapping scheme (370, 380) selected from the group comprising: a pseudo 2=VSB symbol mapping scheme, 4-VSB symbol mapping scheme, and H-VSB mapping scheme.
22. A high-definition digital television signal transmission system (201, 300) for transmitting encoded MPEG-compatible data packets for receipt by a digital television receiver device, said packets including normal packets for transmission as a normal bit stream and robust packets comprising information for transmission as a robust bit stream, said system comprising:
- a first forward error correction (FEC) encoding unit (110) for formatting packets belonging to each said robust and normal data bit streams;
- a robust processor unit (115, 205) for receiving robust packets comprising priority data and processing said packets for generating said robust bit stream;
- a trellis encoder unit (330) for producing a stream of trellis encoded data bits corresponding to bits of said normal and robust streams, said encoder employing means (380) for mapping encoded data bits of said robust packets into symbols according to one or more symbol mapping schemes;
- an optional second forward error correction (FEC) encoding unit (125) for ensuring backward compatibility with a receiver device by reading in only packets of said robust bit stream and enabling generation of parity bytes only for the robust stream packets;
and, - a digital television signal transmitter device (160, 170, 180) for transmitting said robust bit streams in a backwards compatible manner, separately or in conjunction with said normal bit stream over a fixed bandwidth communications channel to said receiver device, and, - means for transmitting bits for receipt by said receiver device including information to enable the receiver to correctly decode the robust packets symbols according to the symbol mapping scheme employed, - wherein an existing receiver device (200) is capable of receiving and processing packets of said robust bit stream as null packets and a new receiver device is capable of receiving and processing packets of said robust bit stream at a lower TOV
compared to the standard bit-stream.
23. The high-definition digital television signal transmission system (201, 300) as claimed in Claim 22, wherein said transmitted bits for receipt by said receiver device (200) includes information bits characterizing a digital signal transmission mode according to a number of robust packets, a type of modulation, and a level of redundancy inserted for trellis encoding.
24. The high-definition digital television signal transmission system as claimed in Claim 22, wherein each said transmitted information bit is spread spectrum encoded prior to transmission, said bits encoded for transmission in a reserved bit portion of a data field sync segment (138).
25. The high-definition digital television signal transmission system as claimed in Claim 22, wherein said mode information bits represent a symbol mapping technique employed for said robust packets, said symbol mapping techniques (370, 380) including one selected from 2-VSB, 4-VSB and H-VSB symbol mapping modes, and, an indication of whether said optional second FEC encoding unit was utilized.
CA 2404404 2001-04-02 2002-09-20 An improved digital transmission system for an enhanced atsc 8-vsb system Abandoned CA2404404A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US32448201P true 2001-09-24 2001-09-24
US60/324,482 2001-09-24
US10/127,531 2002-04-22
US10/127,531 US7111221B2 (en) 2001-04-02 2002-04-22 Digital transmission system for an enhanced ATSC 8-VSB system

Publications (1)

Publication Number Publication Date
CA2404404A1 true CA2404404A1 (en) 2003-03-24

Family

ID=26825726

Family Applications (1)

Application Number Title Priority Date Filing Date
CA 2404404 Abandoned CA2404404A1 (en) 2001-04-02 2002-09-20 An improved digital transmission system for an enhanced atsc 8-vsb system

Country Status (2)

Country Link
KR (1) KR100950015B1 (en)
CA (1) CA2404404A1 (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1793607A2 (en) * 2005-11-26 2007-06-06 LG Electronics Inc. Digital television transmitter/receiver and method of processing data in digital television
US7873104B2 (en) 2006-10-12 2011-01-18 Lg Electronics Inc. Digital television transmitting system and receiving system and method of processing broadcasting data
US7876835B2 (en) 2006-02-10 2011-01-25 Lg Electronics Inc. Channel equalizer and method of processing broadcast signal in DTV receiving system
US7881408B2 (en) 2007-03-26 2011-02-01 Lg Electronics Inc. Digital broadcasting system and method of processing data
US7940855B2 (en) 2007-03-26 2011-05-10 Lg Electronics Inc. DTV receiving system and method of processing DTV signal
US8042019B2 (en) 2007-07-04 2011-10-18 Lg Electronics Inc. Broadcast transmitting/receiving system and method of processing broadcast data in a broadcast transmitting/receiving system
US8099654B2 (en) 2007-08-24 2012-01-17 Lg Electronics Inc. Digital broadcasting system and method of processing data in the digital broadcasting system
US8213544B2 (en) 2007-03-30 2012-07-03 Lg Electronics Inc. Digital broadcasting system and method of processing data
US8238486B2 (en) 2004-07-15 2012-08-07 Samsung Electronics Co., Ltd. Digital broadcasting transmission/reception system having improved receiving performance and signal processing method thereof
US8351497B2 (en) 2006-05-23 2013-01-08 Lg Electronics Inc. Digital television transmitting system and receiving system and method of processing broadcast data
US8370728B2 (en) 2007-07-28 2013-02-05 Lg Electronics Inc. Digital broadcasting system and method of processing data in digital broadcasting system
US8429504B2 (en) 2006-04-29 2013-04-23 Lg Electronics Inc. DTV transmitting system and method of processing broadcast data
US8433973B2 (en) 2007-07-04 2013-04-30 Lg Electronics Inc. Digital broadcasting system and method of processing data

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2597706A1 (en) 2005-02-16 2006-08-24 Electronics And Telecommunications Research Institute Improved encoder of e-8vsb forward error correction for digital television system of atsc
CA2562206C (en) 2005-10-05 2012-07-10 Lg Electronics Inc. A method and digital broadcast transmitter for transmitting a digital broadcast signal
CA2562202C (en) 2005-10-05 2013-06-18 Lg Electronics Inc. Method of processing traffic information and digital broadcast system
US7840868B2 (en) 2005-10-05 2010-11-23 Lg Electronics Inc. Method of processing traffic information and digital broadcast system
US7720062B2 (en) 2005-10-05 2010-05-18 Lg Electronics Inc. Method of processing traffic information and digital broadcasting system
CA2562220C (en) 2005-10-05 2013-06-25 Lg Electronics Inc. Method of processing traffic information and digital broadcast system
US7668209B2 (en) 2005-10-05 2010-02-23 Lg Electronics Inc. Method of processing traffic information and digital broadcast system
US8077791B2 (en) 2005-07-11 2011-12-13 Electronics And Telecommunications Research Institute Optimal TCM codec search method for dual stream systems, and encoder/decoder using the same
KR100706608B1 (en) 2005-07-19 2007-04-13 한국전자통신연구원 Optimal encoder and encoding method for dual stream system
WO2007011161A1 (en) * 2005-07-19 2007-01-25 Electronics And Telecommunications Research Institute Optimal encoder and encoding method for dual stream system
KR101191181B1 (en) 2005-09-27 2012-10-15 엘지전자 주식회사 Transmitting/receiving system of digital broadcasting and data structure
KR101147759B1 (en) 2005-10-05 2012-05-25 엘지전자 주식회사 Transmitting/receiving system of digital broadcasting
CA2562209C (en) 2005-10-05 2011-11-22 Lg Electronics Inc. Method of processing traffic information and digital broadcast system
KR101147760B1 (en) 2005-10-06 2012-05-25 엘지전자 주식회사 Transmitting/ receiving system and method of digital broadcasting, and data structure
KR100756036B1 (en) * 2005-10-11 2007-09-07 삼성전자주식회사 Method for robust transmission of Digital broadcasting transport stream and Digital broadcasting transmission/reception system and signal processing method thereof
KR100758999B1 (en) * 2005-10-21 2007-09-17 삼성전자주식회사 System for processing and transmitting digital broadcasting signal and method thereof
KR100794790B1 (en) * 2005-10-21 2008-01-21 삼성전자주식회사 Trellis encoding device for encoding dual tranmission stream and method thereof
KR100759002B1 (en) * 2005-10-21 2007-09-17 삼성전자주식회사 System for processing and transmitting digital broadcasting signal and method thereof
KR101319868B1 (en) 2005-10-31 2013-10-18 엘지전자 주식회사 Digital broadcasting system and processing method
KR101147767B1 (en) * 2005-12-23 2012-05-25 엘지전자 주식회사 Digital broadcasting system and processing method
US7797607B2 (en) 2005-12-27 2010-09-14 Lg Electronics, Inc. DTV transmitter and method of coding main and enhanced data in DTV transmitter
US7823051B2 (en) * 2006-01-03 2010-10-26 Samsung Electronics Co., Ltd. Digital broadcasting transmission system and method thereof
KR100811186B1 (en) * 2006-04-04 2008-03-07 삼성전자주식회사 A device for generating dual transport stream and a method thereof
KR101227506B1 (en) * 2006-06-16 2013-01-30 엘지전자 주식회사 Digital broadcasting system and processing method
WO2007145411A1 (en) 2006-06-16 2007-12-21 Lg Electronics Inc. Digital broadcasting system and method of processing data
KR101227507B1 (en) * 2006-06-20 2013-01-30 엘지전자 주식회사 An apparatus and a method for tranmitting a digital broadcasting signal
CA2656976C (en) 2006-07-07 2012-03-20 Lg Electronics Inc. Digital broadcasting system and method of processing data
KR101276820B1 (en) 2006-09-15 2013-06-18 엘지전자 주식회사 Digital broadcasting system and data processing method
KR101405966B1 (en) 2007-06-26 2014-06-20 엘지전자 주식회사 Digital broadcasting system and method of processing data in digital broadcasting system
KR101456002B1 (en) 2007-06-26 2014-11-03 엘지전자 주식회사 Digital broadcasting system and method of processing data in digital broadcasting system
KR101490194B1 (en) * 2007-07-05 2015-02-06 삼성전자주식회사 Apparatus for processing streams and method thereof
CA2695548C (en) 2007-08-24 2013-10-15 Lg Electronics Inc. Digital broadcasting system and method of processing data in digital broadcasting system
CA2697453C (en) 2007-08-24 2013-10-08 Lg Electronics Inc. Digital broadcasting system and method of processing data in digital broadcasting system
CN101785302B (en) 2007-08-24 2013-07-17 Lg电子株式会社 Digital broadcasting system and method of processing data in digital broadcasting system
KR100949973B1 (en) * 2009-01-16 2010-03-29 엘지전자 주식회사 Broadcasting transmitter/receiver and method of processing broadcasting signal
KR100908065B1 (en) * 2009-01-16 2009-07-15 엘지전자 주식회사 Broadcast transmitter / receiver and a broadcast signal processing method
KR100904445B1 (en) * 2009-01-16 2009-06-26 엘지전자 주식회사 Broadcasting transmitter/receiver and method of processing broadcasting signal
KR100925446B1 (en) * 2009-01-16 2009-11-06 엘지전자 주식회사 Broadcasting transmitter/receiver and method of processing broadcasting signal
KR100925448B1 (en) * 2009-01-16 2009-11-06 엘지전자 주식회사 Broadcasting transmitter/receiver and method of processing broadcasting signal

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7206352B2 (en) * 2001-04-02 2007-04-17 Koninklijke Philips Electronics N.V. ATSC digital television system
US20030099303A1 (en) 2001-06-04 2003-05-29 Koninklijke Philips Electronics N.V. Digital television (DTV) transmission system using enhanced coding schemes

Cited By (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8885770B2 (en) 2004-07-15 2014-11-11 Samsung Electronics Co., Ltd. Digital broadcasting transmission/reception system having improved receiving performance and signal processing method thereof
US8238486B2 (en) 2004-07-15 2012-08-07 Samsung Electronics Co., Ltd. Digital broadcasting transmission/reception system having improved receiving performance and signal processing method thereof
US8848832B2 (en) 2004-07-15 2014-09-30 Samsung Electronics Co., Ltd. Digital broadcasting transmission/reception system having improved receiving performance and signal processing method thereof
US8855238B2 (en) 2004-07-15 2014-10-07 Samsung Electronics Co., Ltd. Digital broadcasting transmission/reception system having improved receiving performance and signal processing method thereof
US8855237B2 (en) 2004-07-15 2014-10-07 Samsung Electronics Co., Ltd. Digital broadcasting transmission/reception system having improved receiving performance and signal processing method thereof
US8855239B2 (en) 2004-07-15 2014-10-07 Samsung Electronics Co., Ltd. Digital broadcasting transmission/reception system having improved receiving performance and signal processing method thereof
EP1793607A3 (en) * 2005-11-26 2010-10-20 LG Electronics Inc. Digital television transmitter/receiver and method of processing data in digital television
US7962840B2 (en) 2005-11-26 2011-06-14 Lg Electronics Inc. Digital television transmitter/receiver and method of processing data in digital television transmitter/receiver
EP1793607A2 (en) * 2005-11-26 2007-06-06 LG Electronics Inc. Digital television transmitter/receiver and method of processing data in digital television
US8438464B2 (en) 2005-11-26 2013-05-07 Lg Electronics Inc. Digital television transmitter/receiver and method of processing data in digital television transmitter/receiver
US8054891B2 (en) 2006-02-10 2011-11-08 Lg Electronics Inc. Channel equalizer and method of processing broadcast signal in DTV receiving system
US10277255B2 (en) 2006-02-10 2019-04-30 Lg Electronics Inc. Channel equalizer and method of processing broadcast signal in DTV receiving system
US8204137B2 (en) 2006-02-10 2012-06-19 Lg Electronics Inc. Channel equalizer and method of processing broadcast signal in DTV receiving system
US8526508B2 (en) 2006-02-10 2013-09-03 Lg Electronics Inc. Channel equalizer and method of processing broadcast signal in DTV receiving system
US7876835B2 (en) 2006-02-10 2011-01-25 Lg Electronics Inc. Channel equalizer and method of processing broadcast signal in DTV receiving system
US9185413B2 (en) 2006-02-10 2015-11-10 Lg Electronics Inc. Channel equalizer and method of processing broadcast signal in DTV receiving system
US8355451B2 (en) 2006-02-10 2013-01-15 Lg Electronics Inc. Channel equalizer and method of processing broadcast signal in DTV receiving system
US8984381B2 (en) 2006-04-29 2015-03-17 LG Electronics Inc. LLP DTV transmitting system and method of processing broadcast data
US8689086B2 (en) 2006-04-29 2014-04-01 Lg Electronics Inc. DTV transmitting system and method of processing broadcast data
US9425827B2 (en) 2006-04-29 2016-08-23 Lg Electronics Inc. DTV transmitting system and method of processing broadcast data
US9178536B2 (en) 2006-04-29 2015-11-03 Lg Electronics Inc. DTV transmitting system and method of processing broadcast data
US8429504B2 (en) 2006-04-29 2013-04-23 Lg Electronics Inc. DTV transmitting system and method of processing broadcast data
US9680506B2 (en) 2006-04-29 2017-06-13 Lg Electronics Inc. DTV transmitting system and method of processing broadcast data
US10057009B2 (en) 2006-05-23 2018-08-21 Lg Electronics Inc. Digital television transmitting system and receiving system and method of processing broadcast data
US9564989B2 (en) 2006-05-23 2017-02-07 Lg Electronics Inc. Digital television transmitting system and receiving system and method of processing broadcast data
US8804817B2 (en) 2006-05-23 2014-08-12 Lg Electronics Inc. Digital television transmitting system and receiving system and method of processing broadcast data
US8351497B2 (en) 2006-05-23 2013-01-08 Lg Electronics Inc. Digital television transmitting system and receiving system and method of processing broadcast data
US10454616B2 (en) 2006-10-12 2019-10-22 Lg Electronics Inc. Digital television transmitting system and receiving system and method of processing broadcasting data
US8611731B2 (en) 2006-10-12 2013-12-17 Lg Electronics Inc. Digital television transmitting system and receiving system and method of processing broadcast data
US9392281B2 (en) 2006-10-12 2016-07-12 Lg Electronics Inc. Digital television transmitting system and receiving system and method of processing broadcasting data
US9831986B2 (en) 2006-10-12 2017-11-28 Lg Electronics Inc. Digital television transmitting system and receiving system and method of processing broadcasting data
US7873104B2 (en) 2006-10-12 2011-01-18 Lg Electronics Inc. Digital television transmitting system and receiving system and method of processing broadcasting data
US8731100B2 (en) 2007-03-26 2014-05-20 Lg Electronics Inc. DTV receiving system and method of processing DTV signal
US8218675B2 (en) 2007-03-26 2012-07-10 Lg Electronics Inc. Digital broadcasting system and method of processing
US8223884B2 (en) 2007-03-26 2012-07-17 Lg Electronics Inc. DTV transmitting system and method of processing DTV signal
US10070160B2 (en) 2007-03-26 2018-09-04 Lg Electronics Inc. DTV receiving system and method of processing DTV signal
US10244274B2 (en) 2007-03-26 2019-03-26 Lg Electronics Inc. DTV receiving system and method of processing DTV signal
US9736508B2 (en) 2007-03-26 2017-08-15 Lg Electronics Inc. DTV receiving system and method of processing DTV signal
US8068561B2 (en) 2007-03-26 2011-11-29 Lg Electronics Inc. DTV receiving system and method of processing DTV signal
US9924206B2 (en) 2007-03-26 2018-03-20 Lg Electronics Inc. DTV receiving system and method of processing DTV signal
US7881408B2 (en) 2007-03-26 2011-02-01 Lg Electronics Inc. Digital broadcasting system and method of processing data
US8488717B2 (en) 2007-03-26 2013-07-16 Lg Electronics Inc. Digital broadcasting system and method of processing data
US9912354B2 (en) 2007-03-26 2018-03-06 Lg Electronics Inc. Digital broadcasting system and method of processing data
US9198005B2 (en) 2007-03-26 2015-11-24 Lg Electronics Inc. Digital broadcasting system and method of processing data
US7940855B2 (en) 2007-03-26 2011-05-10 Lg Electronics Inc. DTV receiving system and method of processing DTV signal
US8023047B2 (en) 2007-03-26 2011-09-20 Lg Electronics Inc. Digital broadcasting system and method of processing data
US8532222B2 (en) 2007-03-30 2013-09-10 Lg Electronics Inc. Digital broadcasting system and method of processing data
US9521441B2 (en) 2007-03-30 2016-12-13 Lg Electronics Inc. Digital broadcasting system and method of processing data
US8213544B2 (en) 2007-03-30 2012-07-03 Lg Electronics Inc. Digital broadcasting system and method of processing data
US8433973B2 (en) 2007-07-04 2013-04-30 Lg Electronics Inc. Digital broadcasting system and method of processing data
US9094159B2 (en) 2007-07-04 2015-07-28 Lg Electronics Inc. Broadcasting transmitting system and method of processing broadcast data in the broadcast transmitting system
US8954829B2 (en) 2007-07-04 2015-02-10 Lg Electronics Inc. Digital broadcasting system and method of processing data
US9660764B2 (en) 2007-07-04 2017-05-23 Lg Electronics Inc. Broadcast transmitter and method of processing broadcast service data for transmission
US9444579B2 (en) 2007-07-04 2016-09-13 Lg Electronics Inc. Broadcast transmitter and method of processing broadcast service data for transmission
US8042019B2 (en) 2007-07-04 2011-10-18 Lg Electronics Inc. Broadcast transmitting/receiving system and method of processing broadcast data in a broadcast transmitting/receiving system
US9184770B2 (en) 2007-07-04 2015-11-10 Lg Electronics Inc. Broadcast transmitter and method of processing broadcast service data for transmission
US8201050B2 (en) 2007-07-04 2012-06-12 Lg Electronics Inc. Broadcast transmitting system and method of processing broadcast data in the broadcast transmitting system
US8370728B2 (en) 2007-07-28 2013-02-05 Lg Electronics Inc. Digital broadcasting system and method of processing data in digital broadcasting system
US8099654B2 (en) 2007-08-24 2012-01-17 Lg Electronics Inc. Digital broadcasting system and method of processing data in the digital broadcasting system
US8370707B2 (en) 2007-08-24 2013-02-05 Lg Electronics Inc. Digital broadcasting system and method of processing data in the digital broadcasting system

Also Published As

Publication number Publication date
KR100950015B1 (en) 2010-03-29
KR20030026236A (en) 2003-03-31

Similar Documents

Publication Publication Date Title
CA2707816C (en) Vsb reception system with enhanced signal detection for processing supplemental data
US8130833B2 (en) VSB transmission system for processing supplemental transmission data
CA2560362C (en) Method of processing data in digital television transmitter
US7100182B2 (en) Digital VSB transmission system
CA2680187C (en) Digital broadcast transmitter/receiver having improved receiving performance and signal processing method thereof
KR101058038B1 (en) Robust signal transmission in digital television broadcasting
US8019011B2 (en) Digital broadcast transmitting/receiving system having an improved receiving performance and signal processing method thereof
CA2529960C (en) Enhanced vsb transmitter and receiver
US8644398B2 (en) Digital broadcast transmission and receiving system having an improved receiving performance and signal processing method thereof
US7092447B2 (en) Communication system in digital television
US7962840B2 (en) Digital television transmitter/receiver and method of processing data in digital television transmitter/receiver
CN101686317B (en) Digital broadcast receiver having an improved receiving performance and signal processing method thereof
KR101138275B1 (en) Digital broadcast transmission apparatus and method for processing stream thereof
JP4668987B2 (en) Digital broadcast transmission / reception system with improved reception performance and equalization performance and signal processing method thereof
KR100928423B1 (en) Digital Television System
KR20100016556A (en) Apparatus and method for encoding and decoding signals
US8054903B2 (en) Digital broadcasting transmission/reception devices capable of improving a receiving performance and signal processing method thereof
US7085324B2 (en) Communication system in digital television
US6980603B2 (en) Digital VSB transmission system
US7020828B2 (en) Trellis encoder with rate 1/4 and 1/2 for a backward compatible robust encoding ATSC DTV transmission system
CA2565863C (en) Digital broadcasting transmission/reception devices capable of improving a receiving performance and signal processing method thereof
US7823052B2 (en) Trellis encoding device for encoding transmission stream and method thereof
KR100771631B1 (en) Broadcasting system and method of processing data in a Broadcasting system
US8638860B2 (en) Digital television transmission and receiving apparatus and method using 1/4 rate coded robust data
KR100657819B1 (en) Double Stream Structure Digital Television Transmission and Receiving Method using Hybrid of E-8VSB, E-4VSB and P-2VSB

Legal Events

Date Code Title Description
FZDE Dead