KR20030023488A - Silicon semiconductor substrate and preparation thereof - Google Patents

Silicon semiconductor substrate and preparation thereof Download PDF

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KR20030023488A
KR20030023488A KR1020020052526A KR20020052526A KR20030023488A KR 20030023488 A KR20030023488 A KR 20030023488A KR 1020020052526 A KR1020020052526 A KR 1020020052526A KR 20020052526 A KR20020052526 A KR 20020052526A KR 20030023488 A KR20030023488 A KR 20030023488A
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semiconductor substrate
silicon
atoms
silicon semiconductor
nitrogen
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KR100566824B1 (en
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다찌가와아키요시
이카리아쓰시
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와커 실트로닉 아게
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02Elements
    • C30B29/06Silicon
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B15/00Single-crystal growth by pulling from a melt, e.g. Czochralski method
    • C30B15/20Controlling or regulating
    • C30B15/206Controlling or regulating the thermal history of growing the ingot
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/12All metal or with adjacent metals
    • Y10T428/12493Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
    • Y10T428/12674Ge- or Si-base component

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  • Crystallography & Structural Chemistry (AREA)
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  • General Physics & Mathematics (AREA)
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Abstract

PURPOSE: To provide a silicon semiconductor substrate having structure which has an oxide deposition defect being a gettering site with high density with the defect-free region of void system crystal right under it, and to provide a method for manufacturing the same. CONSTITUTION: A substrate is obtained through heat treatment of the silicon semiconductor substrate obtained by silicon monocrystal grown by Czochralski method. When setting the defect-free region of an oxide deposition crystal defect to be Oi DZ and a region free from the void system defect of a size >=0.11 μm to be COP DZ, the relation (Oi DZ)-(COP DZ)<=10 μm is satisfied and the oxide deposition crystal defects number >=5x10¬8/cm¬3 in the silicon semiconductor substrate. The silicon semiconductor substrate is obtained from silicon single crystal grown by Czochralski method by using silicon melt containing nitride >=5x10¬7 atoms/cm¬3 and <=5x10¬19 atoms/cm¬3. The manufacturing method performs the heat treatment of the silicon semiconductor substrate in a non-oxidizing atmosphere for not shorter than one hour at a maximum temperature >=1,150°C.

Description

실리콘 반도체기판 및 그의 제조방법{Silicon semiconductor substrate and preparation thereof}Silicon semiconductor substrate and preparation method thereof

본 발명은 실리콘 반도체기판 및 그 제조방법에 관한 것이다.The present invention relates to a silicon semiconductor substrate and a method of manufacturing the same.

상세히는, 보이드계 제품의 무결함 영역 직하에 큰 게터링층을 가진 실리콘 반도체기판 및 그의 제조방법에 관한 것이다.Specifically, the present invention relates to a silicon semiconductor substrate having a large gettering layer directly under a defect-free region of a void-based product and a method of manufacturing the same.

종래, 반도체기판의 게터링 효과의 개선으로서는, 초크랄스키법에 의해 견인된 실리콘 단결정에서 떼어낸 실리콘 웨이퍼에 있어서, 거울면의 표층부의 격자간 산소농도가 2 ×1017atoms/cm3이하이며, 거울면 표면에서 깊이 10㎛이상에 걸친 깊이의 무결함층이 형성되며, 무결함층의 산소석출물등의 미소결함 밀도가 105개/cm3이하이며, 그 무결함층 보다도 깊은 영역에는 미소결함이 108개/cm3이상 형성된 내부 게터링층을 가지며, 거울면의 이면측에는 외부 게터링층을 갖지 않는 것을 특징으로 하는 실리콘 웨이퍼가 알려져 있다(일본국 특개평6-252154호 공보).Conventionally, in order to improve the gettering effect of a semiconductor substrate, in the silicon wafer detached from the silicon single crystal pulled by the Czochralski method, the interstitial oxygen concentration of the surface layer portion of the mirror surface is 2 × 10 17 atoms / cm 3 or less On the mirror surface, a defect-free layer with a depth of 10 µm or more is formed, and the density of micro defects such as oxygen precipitates of the defect-free layer is 10 5 / cm 3 or less, and in the region deeper than the defect-free layer, A silicon wafer is known which has an internal gettering layer in which at least 10 8 defects / cm 3 are formed and does not have an external gettering layer on the back side of the mirror surface (Japanese Patent Laid-Open No. 6-252154).

한편, 보이드계 결함의 무결함층의 개선과 게터링 효과의 양자를 개선한 것으로서, 초크랄스키법에 의해 질소를 도프(dope)하여 성장된 실리콘 단결정을 슬라이스하여 얻은 실리콘 단결정 웨이퍼이며, 그 실리콘 단결정 웨이퍼의 게터링 열처리후 또는 디바이스 제조 열처리후의 무결함층 깊이가 2 ~ 12㎛이며, 또 그의 내부결함 밀도가 1 ×108~ 2 ×1010개/cm3인 것을 특징으로 하는 실리콘 단결정 웨이퍼가 알려져 있다(일본국 특개2000-211995호 공보).On the other hand, a silicon single crystal wafer obtained by slicing silicon single crystals grown by doping nitrogen by the Czochralski method, which has improved both a void-free defect-free layer and a gettering effect. A silicon single crystal wafer characterized in that the depth of the defect-free layer is 2 to 12 µm after the gettering heat treatment or the device fabrication heat treatment of the single crystal wafer, and its internal defect density is 1 x 10 8 to 2 x 10 10 pieces / cm 3 . Is known (Japanese Patent Laid-Open No. 2000-211995).

그러나, 전자(발명)는 질소첨가에 대하여는 아무 시사도 않고 있으며, 또 보이드계 결함의 무결함층에 대하여도 전혀 시사 않되고 있다. 한편, 후자(발명)는 보이드계결정 결함과 산소석축물 결함의 표면에서의 깊이를 함께 제어하여 질소농도 및 실리콘 단결정 견인시에 1100℃의 온도영역을 통과시의 냉각속도(이하 냉각속도만을 기술)의 최적화에 대하여는 아무 시사도 않하고 있다.However, the former (invention) has no suggestion regarding the addition of nitrogen, and has no suggestion at all about the defect-free layer of void defects. On the other hand, the latter (invention) controls the depth at the surface of the void crystal defects and oxygen oxide defects together, the cooling rate when passing through the temperature range of 1100 ℃ during nitrogen concentration and silicon single crystal traction (hereinafter described only cooling rate) There is no suggestion for the optimization of).

즉, 종래의 기술에 의하면, 보이드계결정 결함의 무결함 영역 깊이를 깊게 하려면, 어닐링 작업시간을 장시간화 하든가 또는 어닐링 온도를 고온화함으로써 대응하고 있으나, 그 경우에 산소의 외방확산이 증진되어, 산소석출물의 무결함 영역폭이 보다 깊게되고, 산소석출물도 용해되여 게터링 효과를 약화시키는 결점이 있었다.That is, according to the prior art, in order to deepen the defect-free region depth of void crystal defects, annealing operation time is extended for a long time or annealing temperature is increased, but in this case, outward diffusion of oxygen is enhanced and oxygen The defect-free area width of the precipitate became deeper, and the oxygen precipitates also dissolved, thereby weakening the gettering effect.

따라서, 본 발명의 목적은 새로운 실리콘 반도체기판 및 그 제조방법을 제공하는 것이다.Accordingly, it is an object of the present invention to provide a novel silicon semiconductor substrate and a method of manufacturing the same.

본 발명의 또다른 목적은 보이드계 결정의 무결함 영역 직하에 게터링 사이트로 되는 산소석출물 결함을 고밀도로 구비한 구조를 가진 실리콘 반도체기판 및 그 제조방법을 제공하는데 있다.It is still another object of the present invention to provide a silicon semiconductor substrate having a structure having a high density of oxygen precipitate defects, which become a gettering site, directly below the defect-free region of the void-based crystal, and a method of manufacturing the same.

상기의 목적은 다음 (1) ~ (6)에 의해 달성된다.The above object is achieved by the following (1) to (6).

(1) 초크랄스키법 또는 자장인가 초크랄스키법에 의해 성장한 실리콘 단결정에서 얻은 실리콘 반도체기판을 열처리한 기판에 있어서, 산소석출물결정 결함의 무결함 영역을 Oi DZ로 하고, 0.11㎛이상 크기의 보이드계 결함이 없는 영역을 COP DZ로 하였을때에,(1) In a substrate on which a silicon semiconductor substrate obtained from a silicon single crystal grown by the Czochralski method or the magnetic field-applied Czochralski method is heat-treated, the defect-free region of the oxygen precipitate crystal defect is defined as Oi DZ and has a size of 0.11 mu m or more. When the area without void type defect is set to COP DZ,

(수식 4)(Formula 4)

(Oi DZ) - (COP DZ)10㎛(Oi DZ)-(COP DZ) 10 μm

의 관계식을 만족하고, 또 산소석출물결정 결함이 5 ×108개/cm3이상인 것을 특징으로 하는 실리콘 반도체기판.A silicon semiconductor substrate satisfying the relational formula and having an oxygen precipitate crystal defect of 5 × 10 8 holes / cm 3 or more.

(2) 표면에서 5㎛이상의 깊이에 2차 이온질량 분석법(SIMS)에 의한 질소분석에서 평균 신호강도의 2배 이상의 신호강도를 나타내는 질소편석에 의한 국소농화부를 가진 것을 특징으로 하는 상기 (1)식에 기재된 실리콘 반도체기판의 제조방법.(2) Said (1) characterized in that it has a local enrichment part by nitrogen segregation which shows the signal intensity of 2 times or more of the average signal intensity in nitrogen analysis by secondary ion mass spectrometry (SIMS) at a depth of 5 micrometers or more from the surface (1) A method for producing a silicon semiconductor substrate according to the formula.

(3) 질소농도가 5 ×1014atoms/cm3이상, 1 ×1016atoms/cm3이하인 실리콘 반도체기판을 비산화성 분위기에서 열처리한 후에 기판중심의 표면에서 1㎛깊이에 산소농도가 7 ×1016atoms/cm3이며, 또 포면에서 5㎛이상의 깊이에 2차 이온질량 분석법(SIMS)에 의한 질소분석에서 평균 신호강도의 2배 이상의 신호강도를 나타내는 질소편석에 의한 국소농화부를 가진 것을 특징으로 하는 상기 (1)식에 기재된 실리콘 반도체기판의 제조방법.(3) A silicon semiconductor substrate having a nitrogen concentration of 5 × 10 14 atoms / cm 3 or more and 1 × 10 16 atoms / cm 3 or less is subjected to heat treatment in a non-oxidizing atmosphere, and then the oxygen concentration is 7 × at the surface of the substrate center. It is 10 16 atoms / cm 3 and has a localized thickening part by nitrogen segregation which shows a signal intensity of 2 times or more the average signal intensity in nitrogen analysis by secondary ion mass spectrometry (SIMS) at a depth of 5 µm or more at the surface. The method for producing a silicon semiconductor substrate according to the above (1).

(4) 5 ×1017atoms/cm3이상, 1.5 ×1019atoms/cm3이하의 질소를 함유한 실리콘 융액을 사용하여 초크랄스키법 또는 자장인가 초크랄스키법에 의한 성장한 실리콘 단결정에서 얻은 실리콘 반도체기판을 최고 도달온도 1150℃이상의 온도에서 1시간 이상 비산화성 분위기에서 열처리함으로써 그 기판중심에서의 표면에서 1㎛깊이의 산소농도가 7 ×1016atoms/cm3이하이며, 또 표면에서의 5㎛의 깊이에 2차 이온질량 분석법(SIMS)에 의한 질소분석에서 평균 신호강도의 2배 이상의 신호강도를 나타내는 질소편석에 의한 국소농화부를 가진 것을 특징으로 하는 상기 (1)에 기재된 실리콘 반도체기판의 제조방법.(4) Obtained from silicon single crystals grown by Czochralski method or magnetic field applied Czochralski method using silicon melt containing 5 × 10 17 atoms / cm 3 or more and 1.5 × 10 19 atoms / cm 3 or less The silicon semiconductor substrate is heat-treated in a non-oxidizing atmosphere for at least 1 hour at a temperature of at least 1150 ° C. to reach an oxygen concentration of 1 μm deep at the surface at the center of the substrate, and at most 7 × 10 16 atoms / cm 3 . The silicon semiconductor substrate according to the above (1), wherein the silicon semiconductor substrate has a local concentration portion by nitrogen segregation that exhibits a signal intensity of at least twice the average signal intensity in nitrogen analysis by secondary ion mass spectrometry (SIMS) at a depth of 5 µm. Manufacturing method.

(5) 5 ×1017atoms/cm3이상, 1.5 ×1019atoms/cm3이하의 질소를 함유한 실리콘 융액을 사용하여 초크랄스키법 또는 자장인가 초크랄스키법에 의해 견인시의 냉각속도가 5℃/분 이상에서 성장한 최대 보이드체적이 열처리전의 실리콘 기판의 질소농도를 Natoms/cm3또 견인시의 냉각속도를 CR℃/분으로 했을때에,(5) Cooling rate during traction by the Czochralski method or the magnetic field or Czochralski method using a silicon melt containing 5 × 10 17 atoms / cm 3 or more and 1.5 × 10 19 atoms / cm 3 or less When the maximum void volume grown at 5 ° C / min or more is the nitrogen concentration of the silicon substrate before heat treatment at Natoms / cm 3 and the cooling rate at the time of traction is CR ° C / min,

(수식 5)(Formula 5)

8620000 ×(CR)-1.4×EXP(-3.3E-15 ×[N])100000㎚3 8620000 × (CR) -1.4 × EXP (-3.3E-15 × [N]) 100000 nm 3

로 나타내는 관계식을 만족하는 냉각속도와 질소농도에서 얻어진 실리콘 반도체기판을 최고 도달온도 1150℃이상의 온도로 1시간 이상 비산화성 분위기에서 열처리를 하는 것을 특징으로 하는 상기 (1)식에 기재된 실리콘 반도체기판의 제조방법.The silicon semiconductor substrate according to the above formula (1), wherein the silicon semiconductor substrate obtained at the cooling rate and the nitrogen concentration satisfying the relational expression is heat treated in a non-oxidizing atmosphere for at least 1 hour at a temperature of at least 1150 ° C. Manufacturing method.

(6) 1 ×1018atoms/cm3이상, 1.5 ×1019atoms/cm3이하의 질소를 함유한 실리콘 융액을 사용하여 초크랄스키법 또는 자장인가 초크랄스키법에 의해 견인시 냉각속도가 1℃/분이상, 5℃/분미만에서 성장한 최대 보이드체적이 열처리전의 실리콘 기판의 질소농도를 Natoms/cm3또 견인시의 냉각속도를 CR℃/분으로 했을때에,(6) Cooling rate during traction by the Czochralski method or the magnetic field or Czochralski method using silicon melt containing 1 × 10 18 atoms / cm 3 or more and 1.5 × 10 19 atoms / cm 3 or less When the maximum void volume grown at 1 ° C / min or less but less than 5 ° C / min is the nitrogen concentration of the silicon substrate before heat treatment at Natoms / cm 3 and the cooling rate at the time of traction is CR ° C / min,

(수식 6)(Formula 6)

8620000 ×(CR)-1.4×EXP(-3.3E-15 ×[N])150000㎚3 8620000 × (CR) -1.4 × EXP (-3.3E-15 × [N]) 150000 nm 3

으로 나타내는 관계식을 만족하는 냉각속도 및 질소농도에서 얻어진 실리콘 반도체기판을 최고 도달온도 1200℃이상의 온도로 1시간 이상 비산화성 분위기에서 열처리하는 것을 특징으로 하는 상기 (1)식에 기재된 실리콘 반도체기판의 제조방법.Manufacture of a silicon semiconductor substrate according to the above formula (1), wherein the silicon semiconductor substrate obtained at a cooling rate and nitrogen concentration satisfying the relational expression is heat treated at a temperature of at least 1200 ° C. for at least 1 hour in a non-oxidizing atmosphere. Way.

본 발명에 의한 실리콘 반도체기판은 초크랄스키법(이하, "CZ법"이라 함)또는 자장인가 초크랄스키법(이하, "자장인가 CZ법"이라 함)에 의해 성장한 실리콘 단결정봉을 소정의 두께로 슬라이스하여 얻어지는 것이다.The silicon semiconductor substrate according to the present invention is a silicon single crystal rod grown by a Czochralski method (hereinafter referred to as "CZ method") or a magnetic field or Czochralski method (hereinafter referred to as "magnetic field CZ method"). It is obtained by slicing to a thickness.

즉, CZ법은 석영도가니에 수용된 단결정 실리콘 원료의 융액에 종결정을 접속시켜, 이것을 회전시키면서 서서히 견인하여 소정 직경의 실리콘 단결정봉을 성장시키는 방법이며, 미리 석영도가니내에 질화물을 넣어 두둔가 실리콘 융액에 질화물을 투입하는가 또는 분위기 가스를 질소를 함유한 분위기로 하는 등에 의해 견인 결정에 질소를 도프(dope)할 수가 있다.In other words, the CZ method is a method in which a seed crystal is connected to a melt of a single crystal silicon raw material contained in a quartz crucible, and gradually pulled while rotating it to grow a silicon single crystal rod of a predetermined diameter. Nitrogen can be doped into the traction crystal by adding nitride or by setting the atmosphere gas to an atmosphere containing nitrogen.

이 경우, 질화물의 양, 질소가스의 온도 또는 도입시간등을 조정함으로써 결정의 도프량을 제어할 수 가 있다. 또, 자장인가 CZ법의 경우에도 석영도가니내에 자장을 인가하면서 실시하는 이외에는 CZ법의 경우와 동일하다. 이와 같이하여, 실리콘 반도체기판의 경우는 5 ×1014~ 1 ×1016atoms/cm3, 또는 견인시의 실리콘 융액의 경우는 5 ×1018~ 1.5 ×1019atoms/cm3의 질소농도로 제어하는 것도 용이하게 실시할 수가 있다.In this case, the doping amount of the crystal can be controlled by adjusting the amount of nitride, the temperature of nitrogen gas or the introduction time. The magnetic field or the CZ method is also the same as the CZ method except that the magnetic field is applied in the quartz crucible. Thus, in the case of a silicon semiconductor substrate, a nitrogen concentration of 5 x 10 14 to 1 x 10 16 atoms / cm 3 or 5 x 10 18 to 1.5 x 10 19 atoms / cm 3 for the silicon melt at the time of towing. Control can also be easily performed.

또, 본 발명에서는 CZ법 또는 자장인가 CZ법에 의해 질소를 도프한 실리콘 단결정봉을 성장시키는 경우, 단결정봉에 함유되는 산소농도를 6.5 ×1017~ 1 ×1018atoms/cm3의 범위로 제어하는 것이 바람직하다. 실리콘 단결정봉을 성장시키는 경우에 함유되는 산소농도를 상기 범위로 저하시키는 방법은 종래로부터 관용되고 있는 방법에 의하면 된다. 예를 들면, 도가니 회전수의 감소, 도입가스 유량의 증가, 분위기 압력의 저하, 실리콘 융액의 온도분포 및 대류의 조정등의 수단에 의해 간단히 상기 산소농도 범위로 할 수가 있다.In the present invention, when growing a silicon single crystal rod doped with nitrogen by the CZ method or the magnetic field or CZ method, the oxygen concentration contained in the single crystal rod is in the range of 6.5 × 10 17 to 1 × 10 18 atoms / cm 3 . It is desirable to control. The method of lowering the oxygen concentration contained in the above range in the case of growing a silicon single crystal rod may be in accordance with a conventionally accepted method. For example, the oxygen concentration range can be simply set by means of decreasing the crucible rotation speed, increasing the flow rate of the introduced gas, lowering the atmospheric pressure, adjusting the temperature distribution of the silicon melt and convection.

또, 본 발명에서는, CZ법 또는 자장인가 CZ법에 의해 질소를 도프한 실리콘단결정봉을 성장시키는 경우에 결정 성장중의 1100℃의 온도영역을 통과시의 냉각온도를 1~15℃/분으로 제어하는 것이 바람직하다. 실제로 이와 같은 결정 제조조건을 실현하기 위하여는, 예로써 결정의 견인속도를 조정하여 결정의 성장속도를 증감시키는 방법에 의해 시행하는 것이 가능하다. 또는, CZ법 또는 자장인가 CZ법에 의해 실리콘 단결정장치의 챔버내에 결정을 임의의 냉각속도로 냉각할 수 있는 불어 넣어 결정을 냉각할 수 있는 장치 또는 융액면상의 일정위치에 결정을 둘러싸도록 수냉링을 배치하는 등의 방법을 적용하면 된다. 이 경우, 상기 냉각법과 결정의 견인속도를 조정함으로써 상기 냉각속도 범위내로 할 수가 있다.In the present invention, in the case of growing a silicon single crystal rod doped with nitrogen by the CZ method or the magnetic field application CZ method, the cooling temperature when passing through the temperature range of 1100 ° C during crystal growth is set to 1 to 15 ° C / min. It is desirable to control. In practice, in order to realize such crystal manufacturing conditions, it is possible to carry out by a method of increasing or decreasing the growth rate of the crystal by adjusting the pulling speed of the crystal. Alternatively, a water cooling ring to surround the crystal at a predetermined position on the melt surface or a device capable of cooling the crystal by blowing the crystal into the chamber of the silicon single crystal device by an arbitrary cooling rate by the CZ method or the magnetic field applying CZ method. It may be applied to a method such as arranging. In this case, the cooling method and the pulling speed of the crystal can be adjusted to fall within the cooling rate range.

이와 같은 CZ법 또는 자장인가 CZ법에 있어서, 소망농도의 질소가 도프되고, 소망농도의 산소를 함유하며, 소망의 냉각속도로 결정 설장된 실리콘 단결정봉을 얻을 수가 있다. 실리콘 단결정봉을 통상의 방법에 따라, 내주슬라이서 (internally peripheral slicer) 또는 와이어톱등의 절단장치로 슬라이스한 후, 면치기(chamfering), 래핑, 에칭, 연마등의 공정을 경유하여 실리콘 단결정 웨이퍼로 가공한다.In such a CZ method or a magnetic field applying CZ method, a silicon single crystal rod can be obtained in which a desired concentration of nitrogen is doped, containing a desired concentration of oxygen, and crystal-installed at a desired cooling rate. The silicon single crystal rod is sliced with a cutting device such as an internally peripheral slicer or a wire saw according to a conventional method, and then, into a silicon single crystal wafer via a process such as chamfering, lapping, etching, and polishing. Processing.

물론, 이들의 공정은 예시를 위해 인용된 것이며, 세정등의 여러 다른 공정의 채택도 고려될 수 있다. 또, 공정순의 변경, 일부생략등 목적에 따라 공정은 적절하게 변경 사용되고 있다.Of course, these processes are cited for illustrative purposes, and the adoption of various other processes such as cleaning may also be considered. In addition, the process is suitably changed and used according to the purpose of change of a process sequence, a part omission, and the like.

다음, 이와 같이 얻어진 실리콘 단결정 웨이퍼를 그후의 게터링 열처리 및/또는 디바이스 제조열처리등 열처리를 실시함으로써 산소석출물결정 결함의 무결함 영역을 Oi DZ로 하고, 0.11㎛이상의 크기의 보이드계 결함없는 영역을 COP DZ로 하였을때,Then, the silicon single crystal wafer thus obtained is subjected to heat treatment such as subsequent gettering heat treatment and / or heat treatment for device fabrication, so that the defect-free region of the oxygen precipitate crystal defect is defined as Oi DZ, and the void-free region having a size of 0.11 µm or more is obtained. When set to COP DZ,

(수식 7)(Formula 7)

(Oi DZ) - (COP DZ)10㎛(Oi DZ)-(COP DZ) 10 μm

의 관계식을 만족하고, 또 산소석출물결정 결함이 5 ×108개/㎤이상, 바람직하게는 1 ×109~ 1 ×1010개/㎤의 실리콘 반도체가 얻어진다.Satisfies the relational formula and a silicon semiconductor having an oxygen precipitate crystal defect of 5 × 10 8 / cm 3 or more, preferably 1 × 10 9 to 1 × 10 10 / cm 3.

또, 여기서 Oi DZ(산소석출물 무결함층)의 치는 BMD분석기(MO4)에 의한 측정결과의 무결함층 깊이(DZ)이며, 측정조건으로써 10%의 ND필터를 통하여, 부피부분의 산소석출물 결함밀도의 30%의 밀도인 깊이를 산소석출물 결함의 무결함층(Oi DZ)으로 한다.In this case, the value of Oi DZ (oxygen precipitate free layer) is the depth of defect free layer (DZ) of the measurement result by the BMD analyzer (MO4), and the oxygen precipitate defect in the volume portion is determined through a 10% ND filter as a measurement condition. The depth which is 30% of the density is made into the defect free layer of oxygen precipitate defect (Oi DZ).

본 발명에 있어서, (수식 2) 및 (수식 3)으로 열처리전의 실리콘 반도체기판의 최대 보이드체적의 상한을 규정하고 있으나, 실시예에서는 그 보이드체적을 OPP(적외선 간섭법, infrared interference method)최대 신호강도에서도 계산하고 있다.In the present invention, the upper limit of the maximum void volume of the silicon semiconductor substrate before heat treatment is defined by (Formula 2) and (Formula 3), but in the embodiment, the void volume is defined by the OPP (infrared interference method) maximum signal. It is also calculated in strength.

보이드체적을 TEM에 의해 실제로 구하는 것은 비용 및 시간의 관점에서 곤란함으로 실제로 소정의 보이드체적으로 되어 있는가를 금후 확인하기 위해 TEM관찰에 의해 구한 평가 웨이트중에서의 최대 보이드체적과 OPP최대 신호강도간의 관계를 분명하게 하였다.It is difficult to obtain the void volume by TEM in terms of cost and time, so it is clear that the relationship between the maximum void volume and OPP maximum signal strength among evaluation weights obtained by TEM observation in order to confirm whether the void volume is actually a predetermined void volume in the future. It was made.

OPP최대 신호강도에서 보이드체적을 계산하는 계산식은 냉각속도가 1℃/분이상 3℃/분미만, 3℃/분이상 5℃/분미만, 5℃/분이상의 경우와 질소농도에 의해 환산식이 다음과 같이 변화하는 것이 TEM관찰에 의한 보이드체적의 측정과 OPP최대 신호강도의 일치에서 확인되고 있다.The formula for calculating the void volume at the OPP maximum signal strength is based on the case of cooling rate of 1 ℃ / minute or more and less than 3 ℃ / minute, 3 ℃ / minute or more and less than 5 ℃ / minute, or more than 5 ℃ / minute and nitrogen concentration. The following changes have been confirmed in agreement between the measurement of void volume by TEM observation and the maximum signal strength of OPP.

그 결과에 의하면, 냉각속도가 5℃/분 이상이며, 또 열처리전 실리콘 반도체기판의 질소농도가 5 ×1014atoms/㎤미만 또는 냉각속도가 1℃/분이상 3℃/분미만이고 또 질소농도가 2 ×1014atoms/㎤미만의 경우,As a result, the cooling rate is 5 ° C / min or more, and the nitrogen concentration of the silicon semiconductor substrate before the heat treatment is less than 5 x 10 14 atoms / cm 3 or the cooling rate is 1 ° C / min or more and less than 3 ° C / min and nitrogen If the concentration is less than 2 x 10 14 atoms / cm 3,

(수식 8)(Equation 8)

보이드체적(㎚3) = 110000 ×(OPP최대 신호강도)1.1 Void volume (nm 3 ) = 110000 × (OPP maximum signal strength) 1.1

로 표시된다.Is displayed.

냉각속도가 5℃/분이상이고 열처리전의 실리콘 반도체기판중의 질소농도가 5 ×1014이상 1 ×1016atoms/㎤이하 또는 냉각속도가 3℃/분이상 5℃/분미만에서 열처리전 실리콘 반도체기판의 질소농도가 2 ×1014이상 2 ×106atoms/㎤미만, 또는 냉각속도가 1℃/분이상 3℃/분미만이며, 또 열처리전 실리콘 반도체기판의 질소농도 2 ×1014이상 1 ×1015atoms/㎤미만의 경우,Silicon before heat treatment at a cooling rate of 5 ° C / min or more and a nitrogen concentration in the silicon semiconductor substrate before heat treatment of 5 × 10 14 or more and 1 × 10 16 atoms / cm 3 or less or a cooling rate of 3 ° C / minute or more and less than 5 ° C / minute The nitrogen concentration of the semiconductor substrate is 2 × 10 14 or more, but less than 2 × 10 6 atoms / cm 3, or the cooling rate is 1 ° C./minute or more and less than 3 ° C./minute, and the nitrogen concentration of the silicon semiconductor substrate before heat treatment is 2 × 10 14 or more. If less than 1 x 10 15 atoms / cm 3

(수식 9)(Formula 9)

보이드체적(㎚3) = 20000 ×(OPP 최대신호강도)1.6으로 표시된다.Void volume (nm 3 ) = 20000 × (OPP maximum signal strength) 1.6 .

냉각속도가 1℃/분이상 3℃/분미만에서 열처리전 실리콘 웨이퍼의 질소농도가 1 ×1015atoms/㎤이상, 또는 냉각속도가 3℃/분이상 5℃/분미만에서 열처리전 실리콘기판의 질소농도 2 ×1015atoms/㎤이상 1 ×1016atoms/㎤이하의 경우,Silicon substrate before heat treatment at a cooling rate of 1 ° C./min and less than 3 ° C./minute, and nitrogen concentration of the silicon wafer before heat treatment at 1 × 10 15 atoms / cm 3 or more, or a cooling rate of 3 ° C./minute or more and less than 5 ° C./minute. When the nitrogen concentration of 2 × 10 15 atoms / cm 3 or more and 1 × 10 16 atoms / cm 3 or less

(수식 10)(Formula 10)

보이드체적(㎚3) = 110 ×(OPP 최대신호강도)3.6으로 표시된다.Void volume (nm 3 ) = 110 × (OPP maximum signal strength) 3.6 .

본 관계식을 사용함으로써, 질소를 첨가한 경우의 실리콘 반도체기판의 보이드계 결함의 최대 크기를 구할 수 있으며, 열처리전 제조한 실리콘 반도체기판이 본 발명에서 규정한 보이드계 결함의 크기로 제어되는 것을 확인할 수 있다.By using this relational expression, it is possible to obtain the maximum size of the void-based defects of the silicon semiconductor substrate when nitrogen is added, and confirm that the silicon semiconductor substrate manufactured before the heat treatment is controlled to the size of the void-based defects defined in the present invention. Can be.

실시예에서는 OPP 최대신호강도에서 구한 측정웨이퍼의 최대 보이드체적이 본 실시예에 기재된 냉각속도 및 질소농도를 (수식 2) 및 (수식 3)을 적용하여 계산한 치와 거의 같은 정도이며, 그 치는 각각 (수식 2) 및 (수식 3)에서 제한된 100000㎚3및 150000㎚3이하인 것이 제시되었으며, 한편 비교예에서는 상기 치이상의 보이드체적 보다도 큰것이 나타났으며, 그 실시예 및 비교예에 의해 청구항 1에 기재된 (수식 1)을 만족하는 실리콘 반도체기판을 얻기 위하여는 냉각속도 및 질소농도가 본 발명의 범위에 있는 것이 필요한 것으로 나타나고 있다.In the embodiment, the maximum void volume of the measuring wafer obtained from the maximum signal intensity of OPP is approximately equal to the value calculated by applying the cooling rate and the nitrogen concentration described in this example by using the following equations (2) and (3). It was shown that the formula is limited to 100000 nm 3 and 150000 nm 3 or less in (Formula 2) and (Formula 3), respectively, while in the comparative example, it was found that the void volume was larger than the above-mentioned value. In order to obtain a silicon semiconductor substrate that satisfies the formula (1), it is shown that the cooling rate and the nitrogen concentration are required to be within the scope of the present invention.

또, 본 발명에 의한 실리콘 반도체기판은, 편석한 질소가 BMD분석기로 측정안될 만큼 미소한 산소석출물 결함을 형성함으로써, 표면의 무결함층을 확실하게 확보하기 위해, 표면에서 5㎛이상의 깊이에 2차 이온질량분석법(SIMS)에 의한 질소분석에서 평균신호강도의 2배이상의 신호강도를 나타내는 질소편석에 의한 국소농화부를 구비하는 것이 바람직하다.In addition, the silicon semiconductor substrate according to the present invention forms a small oxygen precipitate defect such that segregated nitrogen cannot be measured by the BMD analyzer, so that the defect free layer on the surface is reliably secured at a depth of 5 µm or more on the surface. In nitrogen analysis by differential ion mass spectrometry (SIMS), it is preferable to provide a local enrichment part by nitrogen segregation which shows a signal intensity of at least twice the average signal intensity.

또, 본 발명에 의한 실리콘 반도체기판은 질소농도가 5 ×1014atoms/㎤ ~ 1 ×1016atoms/㎤이며, 또 실리콘 반도체기판을 비산화성 분위기에서 예로써 수소, 질소, 아르곤, 헬륨, 이들 가스의 1종 또는 2종이상의 혼합가스등의 분위기에서 열처리한 후에 그 기판중심에서의 표면에서 1㎛ 깊이의 산소농도가 7 ×1016atoms/㎤이하이며, 상기의 이유에 의해 표면에서 5㎛이상의 깊이에 2차 이온질량분석법(SIMS)에 의한 질소분석에서, 평균신호강도의 2배이상의 신호강도를 나타내는 질소편석에 의한 국소농화부를 구비하는 것이 또한 바람직하다. 여기서 질소농도의 상한을 1 ×1016atoms/㎤로 결정한 이유는 질소농도가 1 ×1016atoms/㎤을 넘으면, 실리콘 단결정봉을 견인할때, 다결정화하는 염려가 있는 것을 피하기 위한 것이다.In addition, the silicon semiconductor substrate according to the present invention has a nitrogen concentration of 5 x 10 14 atoms / cm 3 to 1 x 10 16 atoms / cm 3, and the silicon semiconductor substrate is exemplified by hydrogen, nitrogen, argon, helium, and the like in a non-oxidizing atmosphere. After heat treatment in an atmosphere of one kind or two or more kinds of gas, the oxygen concentration of 1 占 퐉 depth at the surface of the substrate center is 7 x 10 16 atoms / cm 3 or less, and for the above reason, In nitrogen analysis by secondary ion mass spectrometry (SIMS) at depth, it is also preferred to have a local enrichment by nitrogen segregation which exhibits a signal intensity of at least twice the average signal intensity. The reason for determining the upper limit of the nitrogen concentration of 1 × 10 16 atoms / ㎤ is to avoid that a fear that, when the crystallization exceeds the nitrogen concentration is 1 × 10 16 atoms / ㎤, pulling a silicon single crystal ingot.

이와 같이, 본 발명은 디바이스 활성층인 보이드계결정 결함의 무결함영역의 깊이를 제어하면서, 그 직하에 게터링 사이트로 되는 산소석출물계 결함을 형성할 수 있는 것을 특징으로 하며, 다음 수식을 만족하도록 제어할 수 있는 것을 특징으로 한다.As described above, the present invention is characterized in that an oxygen precipitate based defect, which is a gettering site, can be formed directly under the defect while controlling the depth of the defect-free region of the void crystal defect, which is a device active layer, so as to satisfy the following equation. It can be controlled.

(수식 11)(Equation 11)

BMD밀도5 ×1014/㎤ 및BMD density 5 × 10 14 / cm 3 and

(Oi - DZ) - (COP DZ)10㎛(Oi-DZ)-(COP DZ) 10 μm

이와 같은 물성을 가진 실리콘 반도체기판은 잉곳 견인시의 냉각속도가 5℃/분이상의 경우는 5 ×1017~ 1.5 ×1019atoms/㎤, 냉각속도가 1℃/분이상 5℃/분미만의 경우는 1 ×1018~ 1.5 ×1019atoms/㎤의 질소를 함유한 융액을 사용하여, CZ법 또는 자장인가 CZ법에 의해 성장한 실리콘 단결정에서 얻은 실리콘 반도체기판을 최고 도달온도 1150℃이상, 바람직하게는 1200 ~ 1250℃의 온도에서 1시간이상 상기 비산화성 분위기에서 열처리 함으로써 제조되는 것이 바람직하다.Silicon semiconductor substrates with such physical properties have 5 × 10 17 to 1.5 × 10 19 atoms / cm 3 when the cooling rate during ingot traction is 5 ° C./minute or more, and the cooling rate is less than 5 ° C./minute to 1 ° C./minute or more. In this case, a silicon semiconductor substrate obtained from a silicon single crystal grown by a CZ method or a magnetic field applied CZ method using a melt containing nitrogen of 1 x 10 18 to 1.5 x 10 19 atoms / cm 3 is preferably at least 1150 DEG C or higher. Preferably it is prepared by heat treatment in the non-oxidizing atmosphere for 1 hour or more at a temperature of 1200 ~ 1250 ℃.

또, 본 발명에 의한 실리콘 반도체기판을 보다 확실하게 실현하기 위하여는, 5 ×1017atoms/㎤ ~ 1.5 ×1019atoms/㎤의 질소를 함유한 실리콘 융액을 사용하여 CZ법 또는 자장인가 CZ법에 의해 견인시 1100℃에서의 냉각속도가 5℃/분이상, 바람직하게는 5 ~ 15℃/분에서 성장한 최대 보이드체적이 열처리전의 실리콘기판의 질소농도를 Natoms/㎤, 또 견인시의 1100℃의 온도영역을 통과할때의 냉각속도를 CR℃/분으로 했을때에,In order to reliably realize the silicon semiconductor substrate according to the present invention, the CZ method or the magnetic field applying CZ method using a silicon melt containing nitrogen of 5 x 10 17 atoms / cm 3 to 1.5 x 10 19 atoms / cm 3 The maximum void volume at which the cooling rate at 1100 ° C. at the time of towing is 5 ° C./min or more, preferably 5 to 15 ° C./min is the nitrogen concentration of the silicon substrate before heat treatment at Natoms / cm 3 and 1100 ° C. at the time of towing. When the cooling rate at the temperature range of

(수식 12)(Formula 12)

8620000 ×(CR)-1.4×EXP(-3.3E-15 ×[N])100000㎚3 8620000 × (CR) -1.4 × EXP (-3.3E-15 × [N]) 100000 nm 3

으로 나타내는 관계식을 만족하는 냉각속도와 질소농도에서 얻어진 실리콘 반도체기판의 경우는, 최고 도달온도 1150℃이상에서 1시간 이상, 바람직하게는 1200 ~ 1250℃의 온도에서 0.5시간이상, 바람직하게는 1 ~ 2시간 비산화성 분위기에서 열처리를 함으로써 제조하는 것이 바람직하다.In the case of a silicon semiconductor substrate obtained at a cooling rate and a nitrogen concentration satisfying the relational expression shown in Fig. 1, at least 1 hour at a maximum achieved temperature of 1150 ° C or higher, preferably at least 0.5 hour at a temperature of 1200 to 1250 ° C, preferably 1 to 1 ° C. It is preferable to manufacture by heat-processing in non-oxidizing atmosphere for 2 hours.

또, 냉각속도가 5℃/분미만으로 늦어지는 경우는, 보이드계 결함이 크게됨으로, 보이드를 축소시키기 위해 보다 다량의 질소를 필요로 하며, 또 냉각속도가 느린 경우 보다도 두꺼운 내벽산화막을 열처리로 확산시킴으로 열처리 온도는 보다 고온이 바람직하다. 따라서, 생산성 좋게 본 발명의 청구항 1의 실리콘 반도체기판을 확실하게 얻기 위하여는, 1 ×1018atoms/㎤ ~ 1.5 ×1019atoms/㎤의 질소를 함유한 실리콘 융액을 사용하여 CZ법 또는 자장인가 CZ법에 의해 냉각속도가 1℃/분미만, 바람직하게는 3 ~ 5℃/분에서 성장한 실리콘 반도체기판의 최대 보이드체적이 열처리전의 실리콘기판의 질소농도를 Natoms/㎤, 견인시에 1100℃의 온도영역을 통과할때의 냉각속도를 CR℃/분으로 했을때에.In addition, when the cooling rate is slowed to less than 5 ° C / min, the void-based defects become large, so that a larger amount of nitrogen is required to reduce the voids. By diffusion, the heat treatment temperature is preferably higher. Therefore, in order to reliably obtain the silicon semiconductor substrate of claim 1 with high productivity, the CZ method or the magnetic field is applied using a silicon melt containing 1 x 10 18 atoms / cm 3 to 1.5 x 10 19 atoms / cm 3 of nitrogen. The maximum void volume of a silicon semiconductor substrate grown at a cooling rate of less than 1 ° C./min, preferably 3 to 5 ° C./min, by CZ method is a nitrogen concentration of Natoms / cm 3 before the heat treatment, When the cooling rate when passing through the temperature range is CR ℃ / min.

(수식 13)(Equation 13)

8620000 ×(CR)-1.4×EXP(-3.3E-15 ×[N])150000㎚3 8620000 × (CR) -1.4 × EXP (-3.3E-15 × [N]) 150000 nm 3

로 나타내는 관계식을 만족하는 냉각속도 및 질소농도에서 얻은 실리콘 반도체기판을 최고 도달온도 1200℃이상, 바람직하게는 1200 ~ 1250℃의 온도에서 1시간이상, 바람직하게는 1 ~ 2시간 비산화성 분위기에서 열처리를 함으로써 제조하는 것이 바람직하다.The silicon semiconductor substrate obtained at the cooling rate and the nitrogen concentration satisfying the relational expression is heat-treated in a non-oxidizing atmosphere for 1 hour or more, preferably 1 to 2 hours at a temperature of at least 1200 ° C, preferably at 1200 to 1250 ° C. It is preferable to manufacture by making.

본 발명의 제조법에 의해 제조된 실리콘 반도체기판은, 그 웨이퍼 중에서 표면으로부터 1㎛ 깊이의 산소농도가 7 ×1016atoms/㎤이하이며는, COP DZ가 5㎛이상 확보되며, 불순물의 게터링에 우수하며, 또 (수식 1)의 관계식을 만족하는 실리콘 반도체기판이 제조된다.In the silicon semiconductor substrate produced by the manufacturing method of the present invention, the oxygen concentration of 1 占 퐉 depth from the surface of the wafer is 7 x 10 16 atoms / cm 3 or less, and COP DZ is ensured at 5 占 퐉 or more, and the gettering of impurities A silicon semiconductor substrate is produced which is excellent and satisfies the relational expression (1).

(실시예)(Example)

다음, 본 발명을 실시예 및 비교예를 들어 보다 구체적으로 설명한다. 그러나, 본 발명은 이들 실시예에 제한된 것은 아니다.Next, the present invention will be described in more detail with reference to Examples and Comparative Examples. However, the present invention is not limited to these examples.

CZ법에 의해, 직경 6인치의 결정 견인에는 18인치의 석영도가니에 또 직경 8인치 결정 견인에는 22인치의 석영도가니에 원료로서 다결정 실리콘을 장전하고, 표 1에 나타난 것같이, 직경 6인치 및 8인치 P형, 방위<100>, 저항율 8.5 ~11.5Ω·㎝의 실리콘 단결정봉을 질소농도, 산소농도, 평균 SL 및 냉각속도의 조건을 변경하여 제조하였다.By the CZ method, polycrystalline silicon was loaded as a raw material into a 18-inch quartz crucible for a 6-inch diameter crystal pulley and a 22-inch quartz crucible for a 8-inch diameter crystal pull, and as shown in Table 1, 6-inch diameter and An 8-inch P-type, azimuth <100>, and a silicon single crystal rod having a resistivity of 8.5 to 11.5 Ω · cm were prepared by changing the conditions of nitrogen concentration, oxygen concentration, average SL, and cooling rate.

질소도프량의 제어는 원료중에 미리 소정량의 질화규소막을 가진 실리콘 웨이퍼를 투입하여 놓음으로 실행하였다.The control of the nitrogen dope amount was carried out by putting a silicon wafer having a predetermined amount of silicon nitride film in the raw material in advance.

산소농도의 제어는 견인시 도가니회전을 제어함으로써 실행하였다. 냉각속도의제어는 단결정봉의 견인속도를 변화시키고, 결정의 성장속도를 변화시킴으로써 실행하였다. 얻어진 실리콘 단결정봉의 측정치는 표 1에 나타난 것과 같다.Control of the oxygen concentration was carried out by controlling the crucible rotation during towing. The cooling rate was controlled by changing the pulling speed of the single crystal rods and changing the growth rate of the crystals. The measured value of the obtained silicon single crystal rod is as shown in Table 1.

이와 같이하여 얻어진 단결정에서 와이어톱을 사용하여 떼내어, 면치기, 래핑, 에칭, 거울면 연마가공을 실시하여 질소의 도프량, 신소농도 및 냉각속도 이외의 조건은 거의 동일하게 한 실리콘 단결정 거울면 웨이퍼를 각각 복수개의 제조하였다.The silicon single crystal mirror surface obtained by stripping, chamfering, lapping, etching, and mirror polishing by using a wire saw from the thus obtained single crystal was almost the same except for the amount of nitrogen doping, new concentration, and cooling rate. A plurality of wafers were each produced.

이와 같이하여 얻어진 실리콘 단결정 웨이퍼에 게터링 열처리를 실시하였다. 이 경우의 게터링 열처리는 수소 20vol.%와 아르곤 80vol.%로 형성된 분위기에서, 800 ~ 1000℃의 온도영역에서는 8℃/분의 승온율, 1000 ~ 1100℃의 온도영역에서는 4℃/분의 승온율, 1100 ~ 1150℃의 온도영역에서는 1℃/분의 승온율, 1150 ~ 1200℃의 온도영역에서는 1℃/분의 승온율로 승온하며, 최고 도달온도가 1150℃에서는4시간 또는 8시간 유지, 또 1200℃까지 승온한 경우는 30분에서 2시간 유지한다. 유지후, 1200 ~ 1150℃의 온도영역에서는 1℃분의 강온율, 1150 ~ 1100℃의 온도영역에서는 1℃/분의 강온율, 1100 ~ 800℃의 온도영역에서는 4℃/분의 강온율로 냉각함으로써 실시하였다. 또한, 그 열처리의 경우 비산화성 분위기는 아르곤 및 수소 vol.%의 비율을 변경하여도 동일하였으며, 극단으로는 아로곤 100vol.% 또는 수소 100vol.%에서도 손상되지 않았다.The gettering heat treatment was performed on the silicon single crystal wafer thus obtained. In this case, the gettering heat treatment is performed in an atmosphere formed of 20 vol.% Hydrogen and 80 vol.% Argon. The temperature rising rate is 8 ° C / min in the temperature range of 800 to 1000 ° C and 4 ° C / min in the temperature range of 1000 to 1100 ° C. Temperature increase rate, the temperature increase rate of 1 ° C./min in the temperature range of 1100 to 1150 ° C., the temperature increase rate of 1 ° C./min in the temperature range of 1150 to 1200 ° C., and the maximum achieved temperature is 4 hours or 8 hours at 1150 ° C. The fats and oils are maintained at 30 minutes for 2 hours when the temperature is raised to 1200 ° C. After holding, the temperature reduction rate of 1 ° C./min in the temperature range of 1200 to 1150 ° C., the temperature reduction rate of 1 ° C./min in the temperature range of 1150 to 1100 ° C., and the temperature drop rate of 4 ° C./min in the temperature range of 1100 to 800 ° C. It carried out by cooling. In the case of the heat treatment, the non-oxidizing atmosphere was the same even if the ratio of argon and hydrogen vol.% Was changed, and at the extreme, it was not damaged even at 100 vol.% Of argon or 100 vol.% Of hydrogen.

계속하여, 이들의 실리콘 단결정웨이퍼의 무결함층 깊이를 평가하였다. 표면에서의 연마제거량을 변경한 웨이퍼를 준비하였다. 그리고, SC-1혼합액(암모니아수(NH4OH)와 과산화수소수(H2O2) 및 초순수의 1 : 1 : 20의 혼합액)으로 웨이퍼를 온도약 80℃에서 1시간 세정함으로써 미소한 COP를 가시화시켜 웨이퍼 표면을 KLA/Tencor사제 SP1 입자측정장치로, 그 웨이퍼 표면에 존재하는 크기가 0.11㎛이상의 COP(Crystal Originated Particle)에 대해서 COP수를 카운트하여 측정하였다.Subsequently, the defect free layer depth of these silicon single crystal wafers was evaluated. The wafer which changed the removal amount on the surface was prepared. Then, the fine COP is visualized by washing the wafer with an SC-1 mixture (a mixed solution of ammonia water (NH 4 OH), hydrogen peroxide solution (H 2 O 2 ), and ultrapure water 1: 1: 20) at a temperature of about 80 ° C. for 1 hour. The surface of the wafer was measured using a SP1 particle measuring apparatus manufactured by KLA / Tencor Co., Ltd., and the COP number was counted for COP (Crystal Originated Particle) having a size of 0.11 µm or more.

그리고, 그 SC-1혼합액으로 세정을 10회 반복하여, 세정전의 COP수에서 10회 세정후에 측정한 COP수의 증가분을 SC-1혼합액으로 에칭에 의해 제거한 체적으로 제하여 COP 체적밀도를 계산하였다. 또한, 재연마에 의한 연마제거 두께는 1, 3, 5, 7, 12㎛의 깊이까지 실시되었다.The washing was repeated 10 times with the SC-1 mixture, and the COP volume density was calculated by subtracting the increase in the COP number measured after washing 10 times from the COP water before washing by the volume removed by etching with the SC-1 mixture. . In addition, the polishing removal thickness by repolishing was performed to the depth of 1, 3, 5, 7, 12 micrometers.

또, 무결함층 두께에 대하여는 상기와 동일하게 표면에서의 연마제거량을 변경한 웨이퍼에 대하여, 산화막내압 품질을 평가하여 실시하였다. 산화막내압 품질은 TZDB(Time Zero Dielectric Breakdown)의 C모드 수율, 상세하게는 인도프폴리실리콘전극(산화막 두께 25㎚, 전극 면적 20㎟)을 제조하여, 판정전류치 100㎃/㎠로 평가한 절연파괴전계 11㎷/㎝이상의 것을 양품으로 하고, 웨이퍼면내의 모든 전극에 대하여 양품율을 조사하였다.In addition, about the thickness of a defect-free layer, the oxide film breakdown voltage quality was evaluated about the wafer which changed the removal amount on the surface similarly to the above. The dielectric breakdown voltage quality was obtained by C mode yield of TZDB (Time Zero Dielectric Breakdown), in detail, an in-doped polysilicon electrode (oxide thickness of 25 nm, electrode area of 20 mm2), and the dielectric breakdown value evaluated at a determination current of 100 mA / cm 2. A good product having an electric field of 11 mA / cm or more was regarded as a good product, and a good yield was examined for all the electrodes in the wafer surface.

또, 산소석출물 결함밀도 및 Oi Dz를 조사하기 위하여, 본 발명품인 실리콘 단결정 웨이퍼에 디바이스 열처리와 유사한 열처리를 실시하였다. 그 열처리는 실리콘 단결정 웨이퍼를 질소분위기에서 8000℃의 열처리를 4시간 실시한 후, 또 1000℃의 산화열처리를 16시간 실행함으로서 달성하였다.In addition, in order to investigate the oxygen precipitate defect density and Oi Dz, a heat treatment similar to the device heat treatment was applied to the silicon single crystal wafer of the present invention. The heat treatment was accomplished by subjecting the silicon single crystal wafer to a nitrogen atmosphere for 4 hours at 8000 ° C., followed by an oxidation heat treatment at 1000 ° C. for 16 hours.

또, 견인되고 거울화된 열처리전 실리콘 단결정 웨이퍼의 내부 미소결함중 최대 신호강도를 가진 결함의 크기를 평가 하였다. 그 내부 미소결함밀도의 측정은 OPP(Optical Precipitate Prpfiler)법으로 실시되었으며, 그 OPP법은 노르말스키(Normalski)형 미분간섭 현미경을 응용한 것이다. 먼저, 광원에서 나온 레이저관을 편광프리즘에서 2개의 직교하는 90°위상이 다른 직선 편관의 빔으로 분리하여, 웨이퍼경면측에서 입사시킨다. 이때, 1개의 빔이 결함을 가로지르면 위상시프트가 생기며, 다른 1개의 빔과의 위상차가 발생한다.In addition, the size of the defects with the maximum signal strength among the internal microdefects of the pulled and mirrored silicon single crystal wafer before heat treatment was evaluated. The internal microdefect density was measured by the OPP (Optical Precipitate Prpfiler) method, and the OPP method is a normalski-type microdispersive microscope. First, the laser tube emitted from the light source is separated into two straight orthogonal beams of two orthogonal 90 ° phases in the polarizing prism, and incident on the wafer mirror surface side. At this time, when one beam crosses the defect, a phase shift occurs, and a phase difference with the other beam occurs.

빔이 웨이퍼의 이면을 통과후에 그 위상차를 편광분석기에 의해 검출함으로써 결함을 검출한다.After the beam passes through the backside of the wafer, defects are detected by detecting the phase difference with a polarization analyzer.

이와 같이하여 얻어진 측정결과를 표 2 ~ 표 6에 나타냈었다.The measurement results thus obtained were shown in Tables 2 to 6.

여기서 무결함층 결함층깊이의 평가에 대하여는, COP수에 의한 평가는 상기 SC-1혼합물에 의한 반복 세정에 의해 이루어지며, 웨이퍼면내의 COP체적 밀도가 2×105개/㎤이하 일것, 또 산화막내압(TZDB)에 의한 평가로 양품율이 90%이상을 만족하는 깊이를 무결함층으로 하여 평가하고 있다.In the evaluation of the defect free layer depth, the COP number is evaluated by repeated washing with the SC-1 mixture, and the COP volume density in the wafer surface is 2 × 10 5 pieces / cm 3 or less. The depth by which the yield rate satisfies 90% or more by evaluation by oxide film breakdown voltage (TZDB) is evaluated as a defect free layer.

여기서, 표 2 및 표 3의 데이터를 6인치의 직경을 가진 본 발명품의 실시예이며, 청구항 1 및 2를 만족하는 실리콘 반도체기판임과 동시에 3항에서 5항까지의 제조조건을 만족하고 있다. 즉, 냉각속도 5℃/분이상이고 질소농도가 5 ×1014atoms/㎤이상이며, 또 비산화성 분위기에서 1150℃이상의 온도로 1시간 이상의 열처리를 실시하며, 열처리후 표층으로부터 1㎛ 깊이에서의 산소농도가 SIMS에 의한 측정에서 7 ×1017atoms/㎤이하인 조건을 만족하고 있다.Here, the data of Table 2 and Table 3 is an embodiment of the present invention having a diameter of 6 inches and is a silicon semiconductor substrate satisfying Claims 1 and 2, and at the same time satisfying the manufacturing conditions of paragraphs 3 to 5. That is, the cooling rate is 5 ° C./min or more, the nitrogen concentration is 5 × 10 14 atoms / cm 3 or more, and the heat treatment is performed for 1 hour or more at a temperature of 1150 ° C. or more in a non-oxidizing atmosphere. The oxygen concentration satisfies the condition of 7 × 10 17 atoms / cm 3 or less in the measurement by SIMS.

또한, 본 실시예에서 어닐링조건이 1200℃ ×0시간의 조건은, 1150℃ ~ 1200℃에서의 승강온시간이 합계로 100분(미온도 영역에서의 승강온율은 1℃/분 임으로)이며, 본 발명의 제조조건인 1150℃이상에서 1시간 이상인 조건을 만족하고 있다.In the present embodiment, the annealing condition is 1200 占 폚 for 0 hours, and the elevated temperature rise time at 1150 占 폚 to 1200 占 폚 is 100 minutes in total (elevation rate in the non-temperature range is 1 占 폚 / min), It satisfies the conditions of 1 hour or more at 1150 degreeC or more which is the manufacturing conditions of this invention.

표에 나타낸 계산 보이드체적은 각각의 실시예에 나타낸 냉각속도 및 질소농도에 의해 (수식 2)의 좌변의 계산식에서 구한 열처리전 실리콘 반도체기판의 최대 보이드체적이다. 또, 표중의 OPP계산 보이드체적은 OPP측정에 의한 최대 신호강도에서 (수식 8)부터 (수식 10)에 의해 구해진 치이다. 그 보이드체적은 상기 (수식 2)의 좌변에서 계산된 최대 보이드체적(표중의 계산 보이드체적)과 유사하게, (수식 2)의 좌변에 나타낸 최대 허용보이드체적 100000㎚3이하를 만족하고 있으며,OPP에 의한 평가에 의해 얻어진 열처리전 실리콘 반도체기판이 본 발명에서 규정된 범위인 것이 확인된다. 또한, OPP측정에서 구한 최대 신호강도는 측정장치상에서의 디지털화된 측정치로만 얻어진다. 그 때문에, OPP최대 신호강도에서 구한 보이드체적과 (수식 2)에서 구한 보이드체적은 완전히 동일한 치로는 않된다.The calculated void volume shown in the table is the maximum void volume of the silicon semiconductor substrate before heat treatment determined from the formula on the left side of Equation 2 by the cooling rate and the nitrogen concentration shown in each example. In addition, the OPP calculation void volume in a table | surface is the value calculated | required by Formula (8)-(10) from the maximum signal intensity by OPP measurement. The void volume satisfies the maximum allowable void volume 100000 nm 3 or less shown on the left side of (Formula 2), similar to the maximum void volume (calculated void volume in the table) calculated on the left side of Equation 2 above, and OPP It is confirmed that the silicon semiconductor substrate before heat treatment obtained by the evaluation by is in the range specified in the present invention. In addition, the maximum signal strength obtained from OPP measurements is obtained only by digitized measurements on the measuring device. For this reason, the void volume obtained from the OPP maximum signal strength and the void volume obtained from Equation 2 are not necessarily the same value.

또, 표 4의 데이터는 본 발명의 실리콘 반도체기판의 조건을 만족하지 않는 비교예에 의한 직경 6인치의 제품에 관한 것이다. 이들은 청구항 3에서 5까지의 제조조건에서 주로 질소농도가 본 발명의 범위외임으로 청구항 1에 기재한 산소석출물결정 결함은 5 ×108개/㎤이하에서 언제나 만족하는 것이 아니며, (Oi DZ) - (COP DZ)10㎛의 관계를 만족 않는다.The data in Table 4 relates to a product having a diameter of 6 inches according to a comparative example which does not satisfy the conditions of the silicon semiconductor substrate of the present invention. They are not always satisfied below 5 x 10 8 pieces / cm 3 as the oxygen precipitate crystal defects described in claim 1 are mainly in the concentration of nitrogen outside the range of the present invention under the manufacturing conditions of claims 3 to 5, (Oi DZ)- (COP DZ) The relationship of 10 mu m is not satisfied.

또한, 표 5의 데이터는 본 발명의 청구항 6의 실시예에 의한 직경 8인치의 제품에 관한 것이며, 이들 제품은 청구항 1을 만족하는 실리콘 반도체기판에 관한 것이다. 즉, 냉각속도 1℃/분이상, 5℃/분미만에서 열처리전 실리콘 반도체기판의 질소농도가 1 ×1015atoms/㎤이상이며, 또 비산화성 분위기에서 1200℃이상의 온도로 1시간 이상의 열처리를 시행하고, 열처리후 표면으로부터 1㎛깊이에서의 산소농도가 SIMS에 의한 측정에서 7 ×1017atoms/㎤이하의 조건을 만족한다.In addition, the data in Table 5 relates to a product having a diameter of 8 inches according to the embodiment of claim 6 of the present invention, these products relates to a silicon semiconductor substrate satisfying claim 1. That is, the nitrogen concentration of the silicon semiconductor substrate before the heat treatment at a cooling rate of 1 ° C./min or less and 5 ° C./min or less is 1 × 10 15 atoms / cm 3 or more, and the heat treatment is performed at a temperature of 1200 ° C. or more for 1 hour or more in a non-oxidizing atmosphere. After the heat treatment, the oxygen concentration at a depth of 1 占 퐉 from the surface satisfies the condition of 7 x 10 17 atoms / cm 3 or less in the measurement by SIMS.

표 5의 계산보이드체적은 각각의 실시예에서 나타난 냉각속도 및 질소농도에 의해 (수식 3)의 좌변의 계산식에서 구한 열처리전 실리콘 반도체기판의 최대 보이드체적이다.The calculated void volume of Table 5 is the maximum void volume of the silicon semiconductor substrate before heat treatment determined from the formula of the left side of Equation 3 by the cooling rate and the nitrogen concentration shown in each example.

또, 표의 OPP계산 보이드체적은 OPP측정에 의한 최대 신호강도를 (수식 8)부터 (수식 10)까지의 관계식에 대입하여 구한 치이며, 그 계산보이드체적 및 그 OPP보이드체적은 (수식 3)의 좌변의 최대 허용보이드체적인 150000㎚3이하 이다.The OPP calculation void volume in the table is obtained by substituting the maximum signal intensity from the OPP measurement into the equation (Eq. 8) to (Eq. 10), and the calculated void volume and the OPP void volume are shown in Equation (3). The maximum allowable void volume of the left side is 150000 nm 3 or less.

표 6의 데이터는 주로 직경 8인치를 가진 본 발명의 청구항 6에 기재된 실리콘 반도체기판의 조건을 만족하지 않는 비교예에 의한 제품에 관한 것이다. 이들은 청구항 6의 제조조건에서 주로 질소농도가 본 발명의 범위외임으로 청구항 1에 기재한 산소석출물결정 결함인 5 ×108개/㎤를 항상 만족하지 않으며, (Oi DZ) - (COP DZ)10㎛의 관계를 만족하지 않는다.The data in Table 6 relates to a product according to a comparative example which does not satisfy the conditions of the silicon semiconductor substrate of claim 6, which mainly has a diameter of 8 inches. They do not always satisfy the 5 × 10 8 defects / cm 3, which is the oxygen precipitate crystal defect described in claim 1, because the nitrogen concentration is mainly outside the scope of the present invention under the manufacturing conditions of claim 6, and (Oi DZ)-(COP DZ) The relationship of 10 mu m is not satisfied.

이상과 같이, 본 발명에 의한 실리콘 반도체기판은 보이드계 결함의 무결함영역의 직하에 게터링 사이트로 되는 산소석출물 결함을 고밀도로 구비하는 구조를 가지도록 보이드계결정 결함의 무결함 영역의 깊이 및 산소석출물 결함의 밀도 및 그 발생깊이를 제어할 수 있는 발명이다. 그리고 이 기술은 열처리전의 실리콘 반도체기판의 질소농도 및 냉각속도의 범위를 본 발명의 범위에 한정시킴으로써 가능하게 되는 것이다.As described above, the silicon semiconductor substrate according to the present invention has a structure in which a high density of oxygen precipitate defects, which become gettering sites, is formed directly below the defect-free regions of void-based defects. It is an invention that can control the density of oxygen precipitate defects and their depth of occurrence. This technique is made possible by limiting the range of nitrogen concentration and cooling rate of the silicon semiconductor substrate before heat treatment to the scope of the present invention.

Claims (6)

초크랄스키법 또는 자장인가 초크랄스키법에 의해 성장된 실리콘 단결정에서 얻은 실리콘 반도체기판을 열처리한 기판에 있어서, 산소석출물결정 결함의 무결함 영역을 Oi DZ로 하고, 0.11㎛이상 크기의 보이드계 결함없는 영역을 COP DZ로 했을때,In a substrate heat-treated with a silicon semiconductor substrate obtained from a silicon single crystal grown by the Czochralski method or the magnetic field-applied Czochralski method, the void region of the oxygen precipitate crystal defect is defined as Oi DZ and has a void type of 0.11 탆 or more. When the area without defects is COP DZ, (수식 1)(Formula 1) (Oi DZ) - (COP DZ)10㎛(Oi DZ)-(COP DZ) 10 μm 의 관계식을 만족하고, 또 산소석출물결정 결함이 5 ×108개/㎤이상인 것을 특징으로 하는 실리콘 반도체기판.And a silicon oxide crystal defect of at least 5 x 10 8 atoms / cm 3. 제 1항에 있어서, 표면에서 5㎛이상의 깊이에 2차 이온질량분석법(SIMS)에 의한 질소분석에서 평균신호강도의 2배이상의 신호강도를 나타내는 질소편석에 의한 국소농화부를 가진 것을 특징으로 하는 실리콘 반도체기판.2. A silicon according to claim 1, characterized in that it has a localized thickening portion by nitrogen segregation which exhibits a signal intensity of at least 5 µm from the surface and at least twice the average signal intensity in nitrogen analysis by secondary ion mass spectrometry (SIMS). Semiconductor substrate. 제 1항에 있어서, 질소농도 5 ×1014atoms/㎤이상, 1.5 ×1016atoms/㎤이하인 실리콘 반도체기판을 비산화성 분위기에서 열처리한 후에 그 기판중심에서의 표면에서 1㎛ 깊이의 산소농도가 7 ×1016atoms/㎤이하이며, 또 표면에서 5㎛이상의 깊이에 2차 이온질량분석법(SIMS)에 의한 질소분석에서 평균신호강도의 2배이상의 신호강도를 나타내는 질소편석에 의한 국소농화부를 가진 것을 특징으로 하는 실리콘 반도체기판의 제조방법.The oxygen concentration of 1 占 퐉 deep at the surface at the center of the substrate after heat treatment in a non-oxidizing atmosphere of a silicon semiconductor substrate having a nitrogen concentration of 5 x 10 14 atoms / cm 3 or more and 1.5 x 10 16 atoms / cm 3 or less. It has a localized thickening part by nitrogen segregation that is 7 × 10 16 atoms / cm 3 or less and has a depth of 5 µm or more on the surface and shows a signal intensity of more than twice the average signal intensity in nitrogen analysis by secondary ion mass spectrometry (SIMS). Method for producing a silicon semiconductor substrate, characterized in that. 제 1항에 있어서, 5 ×1017atoms/㎤이상, 1.5 ×1019atoms/㎤이하의 질소를 함유한 실리콘 융액을 사용하며 초크랄스키법 또는 자장인가 초크랄스키법에 의해 성장한 실리콘 단결정에서 얻은 실리콘 반도체기판을 최고 도달온도 1150℃이상의 온도로 1시간이상 비산화성 분위기에서 열처리함으로써 그 기판중심에서의 표면에서 1㎛ 깊이의 산소농도가 7 ×1016atoms/㎤이하이며, 또 표면에서 5㎛이상의 깊이에 2차 이온질량분석법(SIMS)에 의한 질소분석에서 평균신호강도의 2배이상의 신호강도를 나타내는 질소편석에 의한 국소농화부를 가진 것을 특징으로 하는 실리콘 반도체기판의 제조방법.The silicon single crystal according to claim 1, wherein a silicon melt containing at least 5 x 10 17 atoms / cm 3 and at most 1.5 x 10 19 atoms / cm 3 is grown by Czochralski method or magnetic field applied Czochralski method. The silicon semiconductor substrate thus obtained was heat-treated at a temperature of at least 1150 ° C. for at least 1 hour in a non-oxidizing atmosphere so that an oxygen concentration of 1 μm deep at the surface at the center of the substrate was 7 × 10 16 atoms / cm 3 or less, and 5 at the surface. A method for producing a silicon semiconductor substrate, characterized by having a localized enrichment portion by nitrogen segregation which exhibits a signal intensity of more than twice the average signal intensity in nitrogen analysis by secondary ion mass spectrometry (SIMS) at a depth of not less than µm. 제 1항에 있어서, 5 ×1017atoms/㎤이상, 1.5 ×1019atoms/㎤이하의 질소를 함유한 실리콘 융액을 사용하여 초크랄스키법 또는 자장인가 초크랄스키법에 의해견인하며, 견인시에 1100℃의 온도영역을 통과시의 냉각속도가 5℃/분이상에서 성장한 실리콘 단결정에서 얻은 실리콘 반도체기판이며, 열처리전의 실리콘기판의 질소농도가 Natoms/㎤ 또 견인시의 1100℃의 온도영역을 통과할때의 냉각속도는 CR℃/분으로 했을때의 보이드계 결함의 최대 보이드체적이The method according to claim 1, wherein the silicon melt containing nitrogen of 5 x 10 17 atoms / cm 3 or more and 1.5 x 10 19 atoms / cm 3 or less is used for the towing by the Czochralski method or the magnetic field-applied Czochralski method. A silicon semiconductor substrate obtained from a silicon single crystal with a cooling rate of 5 ° C./min or more when passing through a temperature range of 1100 ° C. during the process, and the nitrogen concentration of the silicon substrate before the heat treatment is Natoms / cm 3, The cooling rate at the time of passage is the maximum void volume of the void system defect at CR ° C / min. (수식 2)(Formula 2) 8620000 ×(CR)-1.4×EXP (-3.3E-15 ×[N])100000㎚3 8620000 × (CR) -1.4 × EXP (-3.3E-15 × [N]) 100000 nm 3 으로 나타내는 관계식을 만족하는 냉각속도와 질소농도에서 얻은 실리콘 반도체기판을 최고 도달온도 1150℃이상의 온도로 1시간이상 비산화성 분위기에서 열처리를 하는 것을 특징으로 하는 실리콘 반도체기판의 제조방법.A method of manufacturing a silicon semiconductor substrate, wherein the silicon semiconductor substrate obtained at a cooling rate and nitrogen concentration satisfying the relational expression is heat-treated in a non-oxidizing atmosphere for at least 1 hour at a temperature of at least 1150 ° C. 1 ×1018atoms/㎤이상, 1.5 ×1019atoms/㎤이하의 질소를 함유한 실리콘 융액을 사용하여 초크랄스키법 또는 자장인가 초크랄스키법에 의해 견인하고 견인시에 1100℃의 온도영역을 통과시의 냉각속도가 1℃/분이상, 5℃/분미만에서 성장한 실리콘 단결정에서 얻어진 실리콘 반도체기판이며, 열처리전의 실리콘기판의 질소농도를 Natoms/㎤ 또 견인할때의 1100℃의 온도영역을 통과시의 냉각속도를 CR℃/분로 햇을때에 보이드계 결함의 최대 보이드체적이Temperature range of 1100 ° C when towed by the Czochralski method or the magnetic field-applied Czochralski method using silicon melt containing nitrogen of 1 × 10 18 atoms / cm 3 or more and 1.5 × 10 19 atoms / cm 3 or less A silicon semiconductor substrate obtained from a silicon single crystal grown at a cooling rate of 1 ° C / minute or more and less than 5 ° C / minute when passing through it, and having a temperature range of 1100 ° C when the nitrogen concentration of the silicon substrate before heat treatment is Natoms / cm 3 or towed. The maximum void volume of the void system defects when the cooling rate at the (수식 3)(Formula 3) 8620000 ×(CR)-1.4 ×EXP (-3.3E-15 ×[N]150000㎚3 8620000 × (CR) -1.4 × EXP (-3.3E-15 × [N] 150000 nm 3 으로 나타내는 관계식을 만족하는 냉각속도 및 질소농도에서 얻어진 실리콘 반도체기판을 최고 도달온도 1200℃이상의 온도로 1시간이상 비산화성 분위기에서 열처리를 하는 것을 특징으로 하는 실리콘 반도체기판의 제조방법.A method of manufacturing a silicon semiconductor substrate, wherein the silicon semiconductor substrate obtained at a cooling rate and nitrogen concentration satisfying the relational expression is heat-treated at a temperature of at least 1200 ° C. for at least 1 hour in a non-oxidizing atmosphere.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7459364B2 (en) * 2004-07-12 2008-12-02 Samsung Electronics Co., Ltd. Methods of forming self-aligned floating gates using multi-etching

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10205084B4 (en) * 2002-02-07 2008-10-16 Siltronic Ag Process for the thermal treatment of a silicon wafer and silicon wafer produced thereby
EP1513193A4 (en) * 2003-02-14 2007-02-28 Sumco Corp Method for manufacturing silicon wafer
WO2004106261A1 (en) * 2003-05-30 2004-12-09 Nagoya Industrial Science Research Institute High-frequency porcelain composition, process for producing the same and planar high-frequency circuit
WO2005013377A1 (en) * 2003-07-25 2005-02-10 Ge Energy (Usa) Llc Semiconductor elements having zones of reduced oxygen
DE10336271B4 (en) * 2003-08-07 2008-02-07 Siltronic Ag Silicon wafer and process for its production
JP5188673B2 (en) * 2005-06-09 2013-04-24 株式会社Sumco Silicon wafer for IGBT and method for manufacturing the same
JP2007022864A (en) * 2005-07-19 2007-02-01 Sumco Corp Method for manufacturing silicon single crystal
JP4760729B2 (en) * 2006-02-21 2011-08-31 株式会社Sumco Silicon single crystal wafer for IGBT and manufacturing method of silicon single crystal wafer for IGBT
US9120088B2 (en) 2008-05-29 2015-09-01 The Board Of Trustees Of The University Of Illinois Heavily doped metal oxides and methods for making the same
EP2309038B1 (en) * 2009-10-08 2013-01-02 Siltronic AG production method of an epitaxial wafer
JP5572569B2 (en) * 2011-02-24 2014-08-13 信越半導体株式会社 Silicon substrate manufacturing method and silicon substrate
JP6652959B2 (en) 2014-07-31 2020-02-26 グローバルウェーハズ カンパニー リミテッドGlobalWafers Co.,Ltd. Nitrogen-doped vacancy-dominant silicon ingot and heat-treated wafer formed therefrom having a density and size of radially uniformly distributed oxygen precipitates
CN105297140B (en) * 2015-09-10 2019-10-25 上海超硅半导体有限公司 Silicon wafer and annealing method

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1242014B (en) * 1990-11-15 1994-02-02 Memc Electronic Materials PROCEDURE FOR THE TREATMENT OF SILICON SLICES TO OBTAIN IN IT CONTROLLED PRECIPITATION PROFILES FOR THE PRODUCTION OF ELECTRONIC COMPONENTS.
JPH0684925A (en) * 1992-07-17 1994-03-25 Toshiba Corp Semiconductor substrate and its treatment
DE69318271T2 (en) * 1992-12-21 1998-12-17 Nippon Steel Corp Process for the growth of compound semiconductors on a silicon wafer
JP3080501B2 (en) * 1993-03-01 2000-08-28 東芝セラミックス株式会社 Silicon wafer manufacturing method
US5833749A (en) * 1995-01-19 1998-11-10 Nippon Steel Corporation Compound semiconductor substrate and process of producing same
JP2687103B2 (en) * 1995-03-24 1997-12-08 科学技術振興事業団 Method for growing Si single crystal with controlled temperature distribution
EP0733726A3 (en) * 1995-03-24 1997-05-02 Koji Izunome Growth of silicon single crystal having uniform impurity distribution along lengthwise or radial direction
JP2760957B2 (en) * 1995-03-24 1998-06-04 科学技術振興事業団 Single crystal growth method with controlled convection field in melt
DE19637182A1 (en) * 1996-09-12 1998-03-19 Wacker Siltronic Halbleitermat Process for the production of silicon wafers with low defect density
US6485807B1 (en) * 1997-02-13 2002-11-26 Samsung Electronics Co., Ltd. Silicon wafers having controlled distribution of defects, and methods of preparing the same
CN1280455C (en) * 1997-04-09 2006-10-18 Memc电子材料有限公司 Low defect density silicon
JPH1160379A (en) * 1997-06-10 1999-03-02 Nippon Steel Corp Production of non-dislocation silicon single crystal
JP3919308B2 (en) * 1997-10-17 2007-05-23 信越半導体株式会社 Method for producing silicon single crystal with few crystal defects and silicon single crystal and silicon wafer produced by this method
EP1052687B1 (en) * 1998-02-02 2016-06-29 Nippon Steel & Sumitomo Metal Corporation Method for manufacturing an soi substrate.
TW589415B (en) * 1998-03-09 2004-06-01 Shinetsu Handotai Kk Method for producing silicon single crystal wafer and silicon single crystal wafer
US6548886B1 (en) * 1998-05-01 2003-04-15 Wacker Nsce Corporation Silicon semiconductor wafer and method for producing the same
JP4084902B2 (en) * 1998-05-01 2008-04-30 シルトロニック・ジャパン株式会社 Silicon semiconductor substrate and manufacturing method thereof
DE19823962A1 (en) * 1998-05-28 1999-12-02 Wacker Siltronic Halbleitermat Method of manufacturing a single crystal
JPH11349393A (en) * 1998-06-03 1999-12-21 Shin Etsu Handotai Co Ltd Silicon single crystal wafer and production of silicon single crystal wafer
US6413310B1 (en) * 1998-08-31 2002-07-02 Shin-Etsu Handotai Co., Ltd. Method for producing silicon single crystal wafer and silicon single crystal wafer
WO2000022197A1 (en) * 1998-10-14 2000-04-20 Memc Electronic Materials, Inc. Epitaxial silicon wafers substantially free of grown-in defects
JP2000256092A (en) * 1999-03-04 2000-09-19 Shin Etsu Handotai Co Ltd Silicon wafer
DE19925044B4 (en) * 1999-05-28 2005-07-21 Siltronic Ag Semiconductor wafer with crystal lattice defects and method of making the same
JP2001144275A (en) * 1999-08-27 2001-05-25 Shin Etsu Handotai Co Ltd Method for producing bonding soi wafer and bonding soi wafer
KR100788988B1 (en) * 1999-10-15 2007-12-28 신에쯔 한도타이 가부시키가이샤 Silicon single-crystal wafer for epitaxial wafer, epitaxial wafer, methods for producing them, and evaluating method
KR100378184B1 (en) * 1999-11-13 2003-03-29 삼성전자주식회사 Silicon wafer having controlled distribution of defects, process for the preparation of the same and czochralski puller for manufacturing monocrystalline silicon ingot
JP2001220291A (en) * 2000-02-01 2001-08-14 Komatsu Electronic Metals Co Ltd Method for producing silicon wafer
JP4463957B2 (en) * 2000-09-20 2010-05-19 信越半導体株式会社 Silicon wafer manufacturing method and silicon wafer
JP4566478B2 (en) * 2001-08-09 2010-10-20 シルトロニック・ジャパン株式会社 Silicon semiconductor substrate and manufacturing method thereof
JP4549589B2 (en) * 2001-09-14 2010-09-22 シルトロニック・ジャパン株式会社 Silicon semiconductor substrate and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7459364B2 (en) * 2004-07-12 2008-12-02 Samsung Electronics Co., Ltd. Methods of forming self-aligned floating gates using multi-etching

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