KR20030022560A - Device for instantaneous protection considered off time of IGCT - Google Patents

Abstract

PURPOSE: A transient protection device is provided to protect a device and prevent spreading of the disorder by interrupting a gate drive signal through sensing of signal variation owing to turn-off fail of the device using a monitoring signal for feeding back a drive state for the gate drive signal. CONSTITUTION: In a device for sensing an error of IGCT and protecting the IGCT used as a high-voltage large-volume switching device, a trigger signal generating part(11) generates a trigger signal which is delayed by a predetermined time, compared with a gate drive signal, at falling edge timing of a gate drive on signal. A latch signal generating and error state displaying part(13) judges a state of a monitoring signal of feeding back a driver state for the gate drive signal at a time when the trigger signal is generated, and displays an error state. At the same time, the latch signal generating and error state displaying part(13) interrupts an input of the gate drive signal. The monitoring signal is supplied to the latch signal generating and error state displaying part(13) via an inverter(15).

Description

Device for instantaneous protection considered off time of IGCT}

The present invention relates to an integrated gate committed thyristor (IGCT) used as a main switching element of a high-voltage large-capacity power circuit, and more particularly, to an instantaneous protection device considering a turn-off time delay.

In general, power silicon switches have been steadily improving, and the first silicon-controlled rectifiers (SCRs) can switch power off only at the end of an AC cycle. The GTO (Gate Turn-Off) thyristor can be switched on or off at any position in the cycle.

This GTO thyristor is composed of thousands of independent switching elements assembled on a silicon wafer. Losses occur in all four states of operation (On, Off, Switching On, and Switching Off), but at high pressure Represents very low on-loss and moderate turn-off loss. However, in consideration of non-homogeneous switching, a snubber circuit is required for stable switching operation, and this snubber circuit takes up a large part of the product, causing design complexity and cost loss. do.

Insulated Gate Bipolar Transistors (IGBTs), on the other hand, are designed for faster switching than GTO thyristors, but the losses in switching are acceptable only in low voltage applications.

In other words, IGBTs have relatively high conduction losses, but the switching is homogeneous, eliminating the need for snubber circuits, but they are not yet directly applied to high voltage applications because the low voltage IGBTs must be connected in series. This is because the system is extremely complex and the losses are increased, making the system less reliable.

Thus, GTO thyristors are still economically applied in most high voltage levels and 3.3kV and 4.16kV class IGBTs are expected to be commercialized soon, but still high losses are expected.

As a result, IGBTs require a large silicon area to overcome the high losses and heat generated, but this increases the cost.

Therefore, a lot of research and development has been conducted to develop an ideal switch that has a fast switching operation like IGBT and has conductivity like a GTO thyristor, and as a result, it is applied to high voltage field by embedding all surrounding circuits necessary for high voltage power devices. For this purpose, IGCT has been developed to improve reliability and convenience.

The IGCT is designed to quickly and simultaneously switch thousands of independent switching structures in a modified GTO thyristor, and maintains a low on / off state loss.

Such IGCT is widely used as a high-voltage large-capacity device because the gate driver and the power device are integrated and have fast switching characteristics, but there is no protection against device failure (Turn-Off failure). There was a disadvantage that it could not cope with the spread of failures.

Therefore, in the prior art, when a failure occurs, the current caused by an arm short circuit rises rapidly, and the detection circuit detects a current change rate to prevent the failure from being prevented by spreading the switch. In the system, there is no effect of instantaneous protection against failure, and there is a problem in that maintenance is difficult because there is no indication of a failure element.

The present invention has been made to solve the above problems of the prior art, by using a monitoring signal for feeding back the state of the drive to the gate drive signal to detect the change in the signal due to the turn-off (Turn-Off) failure of the device Instantaneous protection device by considering the off time of IGCT which is easy to maintain by blocking the gate drive signal in a short time by preventing the device from spreading faults, preventing the spread of failure, and displaying the device which failed to turn off. The purpose is to provide.

The instantaneous protection device considering the off time of the IGCT of the present invention for achieving the above object is an error detection and device protection device of the IGCT used as a high-voltage large-capacity switching device, the polling of the gate drive On (On) signal An error is determined by determining a trigger signal generator that generates a trigger signal delayed by a predetermined time with respect to the gate driving signal at an edge timing, and a state of a monitoring signal which feeds back a driver state with respect to the gate driving signal at the time when the trigger signal is generated. And a latch signal generation and error state display unit which displays a state and simultaneously blocks the input of the gate driving signal.

1 is a configuration of the instantaneous protection device considering the off time of the IGCT of the present invention

2 is a timing diagram of a gate driving signal and a monitoring signal according to the present invention.

3 is a timing diagram for explaining the operation of the trigger signal generator according to the present invention;

4 is a timing diagram for explaining an operation of a latch signal generation and a state display unit;

Explanation of symbols for main parts of the drawings

11: trigger signal generator 11a: counter

11b: first logic device 13: latch signal generation and status display unit

13a: first flip-flop 13b: second logic element

13c: second flip-flop 13d: display unit

Hereinafter, an instantaneous protection device considering the off time of the IGCT of the present invention will be described with reference to the accompanying drawings.

First, the instantaneous protection device considering the off time of the IGCT of the present invention provides a monitoring signal for feeding back the driver's status to the gate driving signal in the IGCT in order to detect a turn-off failure of the device. use.

If the gate driving signal has a constant square wave shape, the state of the monitoring signal can be detected by a simple counter method. However, the gate driving signal is a pulse width modulation (PWM) signal, and the width of the pulse is changed irregularly throughout the entire period. Therefore, the periodic counter method cannot detect the state of the monitoring signal.

In addition, the configuration is too complicated to use other counters for varying pulse widths across the world, and the function is not easy to implement. In addition, instantaneous protection requires the detection of the state of the monitoring signal at the off point.

Accordingly, in the present invention, the turn-off time of the gate driving signal is set as the trigger time in all the sections regardless of the change in the pulse width, and the error state can be detected by determining the state of the monitoring signal at the trigger time.

FIG. 1 is a block diagram of an instantaneous protection device considering an off time of an IGCT of the present invention. The trigger signal generator 11 generates a large delayed trigger signal, and a latch signal is output and turned-on. And an inverter 15 for inverting the latch signal generation and status display unit 13 for indicating the element that failed to be turned off and the monitoring signal.

Here, the trigger signal generator 11 performs a logic operation on the counter 11a and a plurality of output signals output from the counter 11a, and provides the outputs to the latch signal generation and status display 13. A binary ripple counter comprising one logic element 11b, wherein the counter portion 11a uses a gate drive signal as a reset signal and outputs a plurality of outputs Q1, Q2, Q3, and Q4 by a clock signal of 62 ns. It consists of (Binary Ripple Counter).

The first logic element 11b outputs the trigger signal to the latch signal generation and status display unit 13 as a gate of the gate delayed by a predetermined time compared to the gate driving signal.

The latch signal generation and status display unit 13 uses a trigger signal output from the trigger signal generation unit 11 as a clock signal and a first flip that uses the monitoring signal inverted by the inverter 15 as the data input D. A second logic element 13b for logically computing the flop 13a, the output signal Q1 of the first flip-flop 13a, and the inverted monitoring signal, and the output signal of the second logic element 13b. Is a pre-reset signal and an error reset signal is used as a clear signal to output an output signal Q1 and a trip signal for status display, and a second flip-flop 13c, and the second flip-flop ( And a display portion 13d on / off determined according to the status display signal output from 13c).

Here, the first and second flip-flops 13a and 13c are D-flip flops, the second logic element 13b is an OR gate, and the display unit 13d is an LED (Light Emitting). Diode).

Referring to the operation of the instantaneous protection device in consideration of the off time of the IGCT of the present invention configured as described above are as follows.

First, as shown in FIG. 2, the monitoring signal is delayed and fed back for a predetermined time (about 0.4 ms according to the experiment) compared to the gate driving signal, and continues to be turned on when the turn-off fails.

Therefore, when the turn-off time of the gate driving signal is used as a trigger signal, an error state can be instantaneously detected by detecting the state of the monitoring signal at the trigger time.

Thus, the following two cases are considered in the present invention.

First, since the trigger signal is generally triggered on the rising edge of the counter clock, a not gate should be used for triggering in the rising state, and the configuration of logic circuits according to the number of power devices becomes complicated. In view of the foregoing, the second aspect of the present invention is that since the delay of the monitoring signal compared to the gate driving signal is about 0.4 dB, there is a possibility of malfunction due to the operation delay time of the logic element and the glitch caused by noise. In the case of the trigger signal, we consider the time delay necessary for normal operation after the Off signal is supplied, and also consider the On and the minimum Off pulse width of the driving signal at the off time. .

This will be described in more detail with reference to FIG. 3 as follows.

3 is an operation timing diagram of a trigger signal generator according to the present invention. When the gate driving signal checks the state of the monitoring signal only at the turn-off time, the signal of the on period is used as a reset signal of the binary ripple counter. In addition, since the counter starts from the time when the reset is terminated, that is, the time at which the off starts, it is possible to solve the problem of notifying the sick gate or complicated configuration of the logic circuit.

The outputs of the binary ripple counters Q1, Q2, Q3, and Q4 can secure any desired time delay up to the counter clock x 2 ⁿ times by a logic combination, so that the operation delay time of the logic element and the glitch caused by noise The malfunction can be prevented from occurring.

As described above, when the state of the monitoring signal is detected with a trigger signal delayed by a predetermined time compared to the gate driving signal, and an error state is detected, the error state is supplied to a controller (not shown) to block the output of the gate driving signal. It is convenient for maintenance by preventing diffusion and displaying error status by LED.

That is, as shown in FIG. 1, the trigger signal inverted by the inverter 15 is input to the latch signal generation and the first flip-flop 13a of the state display unit 13, and the trigger is delayed by a predetermined time compared to the gate driving signal. The signal is used as the clock signal CLK. The reason for using the inverted monitoring signal as an input signal of the first flip-flop 13a is to check the status of the monitoring signal when an error occurs.

In other words, when a trigger signal delayed by a predetermined time (0.4 ms) relative to the gate driving signal is input to the clock terminal of the first flip-flop 13a, the first flip-flop 13a is a data input terminal in the rising period of the trigger signal. The signal state of (D) is output as it is. In this case, the signal state of the data input terminal D must be logic 0 for the operation of the latch circuit, and when the turn-off fails, the first flip-flop 13a in consideration of the fact that the monitoring signal becomes logic 1. The inverted monitoring signal is always input to the input terminal of).

In this way, the signal state of the data input terminal of the first flip-flop 13a is always at logic 0 in case the turn-off fails, thereby outputting the output signal of the first flip-flop 13a by the trigger signal. Let Q1) always be logic zero.

The output signal Q1 of the first flip-flop 13a and the inverted monitoring signal are input to the second logic element 13b configured with an OR gate, and thus the output thereof becomes logic 0, so that the second flip-flop It is input to the pre-reset terminal PR of 13c.

When logic 0 is input to the pre-reset terminal of the second flip-flop 13c, the output signal Q1 of the second flip-flop 13c becomes logic 1 and the other output signal Q2 becomes logic 0 to latch. do. At this time, when the output signal Q1 of the second flip-flop 13c becomes logic 1, the LED of the display unit 13d is driven to display an error state, and the other output signal Q2 is a controller (not shown). Provided as a trip signal at.

On the other hand, Figure 4 is an operation timing diagram for explaining the operation of the latch signal generation and the state display unit 13, when the gate driving signal is input, the error detection circuit is operated, the off time of the gate driving signal of the monitoring signal In the state, normally, after 0.4 ms, it changes to the level of logic 0 (dotted dashed line) and at the same time the inverted monitoring signal changes to the level of logic 1 (dotted dashed line).

At this time, the 0.9 ㎲ delayed trigger signal is supplied after the complete state change of the monitoring signal to check the state of the inverted monitoring signal, and the output Q1 of the second flip-flop 13c because the inverted monitoring signal at that time is logic 1. ) Becomes logic 0 and the LED is off.

However, when monitoring the state of the monitoring signal at the time of the gate driving signal off, if it is abnormal, the level of logic 1 becomes solid (solid line) after 0.4 ms, and the inverted monitoring signal becomes the level of logic 0 (solid line). . At this time, the 0.9 ㎲ delayed trigger signal is supplied after the complete state change of the monitoring signal to check the state of the inverted monitoring signal, and since the inverted monitoring signal state of the state is at the level of logic 0, the second flip-flop 13c The output (Q1) becomes logic 1, so the LED is on.

As described above, the instantaneous protection device considering the off time of the IGCT of the present invention has the following effects.

Irrespective of the pulse width of the gate driving signal, the gate driving signal is turned off at the trigger point in all sections, and an error state is detected through the detection of the status of the monitoring signal at the triggering time to drive the gate in a short time. By blocking the signal, not only the device protection but also the device which failed to turn off can be displayed to improve the convenience of maintenance.

Claims (3)

In the error detection and device protection device of IGCT used as a high pressure large capacity switching device, A trigger signal generator configured to generate a trigger signal delayed by a predetermined time with respect to the gate driving signal at a falling edge timing of a gate driving on signal; When the trigger signal is generated, the latch signal generation and error state display unit which determines the state of the monitoring signal which feeds back the driver state with respect to the gate driving signal and displays the error state and blocks the input of the gate driving signal Instantaneous protection device considering the off time of the IGCT, characterized in that configured to include. The display device of claim 1, wherein the latch signal generation and error state display unit is configured. A first flip-flop using the inverted signal of the monitoring signal as a data input and using a trigger signal output from the trigger signal generator as a clock signal; A logic element configured to perform a logic operation by inputting the output data of the first flip-flop and the inverted signal of the monitoring signal; A second flip-flop using output data of the logic element as a pre-reset signal and an error reset signal as a clear signal to output data for indicating an error state and output data for blocking a gate driving signal; Instantaneous protection device considering the off (Off) time of IGCT, characterized in that configured to include. The method of claim 1, wherein the trigger signal generator A binary ripple counter using an on section of the gate driving signal as a reset signal and counting starts from the time when the reset signal is turned off; And an AND gate configured to perform a logic operation on the output signals of the binary ripple counter and provide the output as a clock signal of the first flip-flop.