KR101584009B1 - Method for preventing malfunction of failure diagnosis circuit - Google Patents

Method for preventing malfunction of failure diagnosis circuit Download PDF

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Publication number
KR101584009B1
KR101584009B1 KR1020140157230A KR20140157230A KR101584009B1 KR 101584009 B1 KR101584009 B1 KR 101584009B1 KR 1020140157230 A KR1020140157230 A KR 1020140157230A KR 20140157230 A KR20140157230 A KR 20140157230A KR 101584009 B1 KR101584009 B1 KR 101584009B1
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KR
South Korea
Prior art keywords
input
reset signal
signal
programmable logic
cpld
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KR1020140157230A
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Korean (ko)
Inventor
공헌
이영국
김성한
이재원
강건수
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현대자동차주식회사
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B9/00—Safety arrangements
    • G05B9/02—Safety arrangements electric
    • G—PHYSICS
    • G08—SIGNALLING
    • G08B—SIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
    • G08B17/00—Fire alarms; Alarms responsive to explosion
    • G—PHYSICS
    • G08—SIGNALLING
    • G08B—SIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
    • G08B23/00—Alarms responsive to unspecified undesired or abnormal conditions

Abstract

The present invention relates to a method of preventing malfunction of a fault diagnosis circuit, and more particularly, to a method of preventing a malfunction of a fault diagnosis circuit by maintaining a reset signal input to a programmable logic device (CPLD) A malfunction prevention method of a fault diagnosis circuit which can prevent damage of a power element by preventing the fault diagnosis circuit from releasing the PWM OFF signal by the noise-like reset signal by fixing the input reset signal to the normal reset signal only when .
One embodiment of a malfunction prevention method of a failure diagnosis circuit according to the present invention includes: a reset signal determination step of determining whether a reset signal input from a control unit to a programmable logic device (CPLD) is shorter than a predetermined time; A clock determining step of determining whether the reference clock input to the programmable logic device (CPLD) is a rising edge when the reset signal is shorter than a predetermined time; Determining whether a fault signal is input to the programmable logic device (CPLD) when the input reference clock is a rising edge; A signal maintenance determination step of determining whether the input fault signal is maintained for a predetermined time when a fault signal is input to the programmable logic device (CPLD); And a fault diagnosis confirmation step of confirming a fault diagnosis when the input fault signal is maintained for a predetermined period of time; . ≪ / RTI >
In this case, the reset signal determination step may include: a reset signal input step of determining whether the reset signal is input to the control unit rotor programmable logic device (CPLD); A clock input step of determining whether a reference clock input to the programmable logic device (CPLD) is a rising edge when the reset signal is input; A reset signal holding determination step of determining whether the input reset signal is shorter than a predetermined time when the input reference clock is a rising edge; And a reset determination step of determining the input reset signal as a normal reset signal input when the input reset signal is not shorter than a predetermined time; . ≪ / RTI >

Description

FIELD OF THE INVENTION [0001] The present invention relates to a fault diagnosis circuit,

The present invention relates to a method of preventing malfunction of a fault diagnosis circuit, and more particularly, to a method of preventing a malfunction of a fault diagnosis circuit by maintaining a reset signal input to a programmable logic device (CPLD) A malfunction prevention method of a fault diagnosis circuit which can prevent damage of a power element by preventing the fault diagnosis circuit from releasing the PWM OFF signal by the noise-like reset signal by fixing the input reset signal to the normal reset signal only when .

In a hybrid vehicle or an electric vehicle, if the system of the vehicle deviates from a normal operating condition, the vehicle control may be adversely affected and the driving motor may malfunction, so that the safety of the vehicle may become a problem. Therefore, the fault diagnosis circuit 1 is used in order to prevent the control system of the vehicle from malfunctioning by detecting an overvoltage fault or an overcurrent fault of the vehicle system.

In the fault diagnosis logic 1 using a programmable logic device (CPLD), the fault diagnosis logic 1 is synchronized with a reference clock so that fault diagnosis is confirmed when a fault input is maintained for a predetermined time After the fault diagnosis, a reset signal is applied from the outside to terminate the fault diagnosis.

FIG. 1 is a block diagram showing a fault diagnosis circuit using a programmable logic device (CPLD), FIG. 2 is a flowchart showing a fault diagnosis method in a prior art programmable logic device (CPLD) FIG. 2 is a diagram showing that a PWM signal is applied by releasing a PWM OFF signal when a noise-sensitive reset signal is input in a fault diagnosis circuit using a programmable logic device (CPLD).

Referring to FIG. 1, a control unit 10 of a fault diagnosis circuit 1 using a programmable logic device (CPLD) receives a signal from a plurality of sensors and detects a fault using the received signal 11. The control unit 10 continues to apply the PWM signal 12 and 32 to the gate board 40 including the power device 41 even in the failure state 2 due to the overcurrent or the overvoltage in the hybrid vehicle or the electric vehicle The power device 41 may be damaged. Therefore, the fault diagnosis circuit 1 can accurately detect the fault condition 2 and the PWM signal 12 (32) can be applied to the gate board 40 (including the power device 41) ) To be able to quickly block the application.

In the fault diagnosis circuit 1 using the programmable logic element CPLD, the PWM OFF output 21 of the programmable logic element (CPLD) 20 and the PWM OFF output 14 of the controller 10 are connected to the logic element 50 to the Enable terminal 31 of the PWM buffer 30 to promptly interrupt the PWM signal 12 upon confirmation of the failure diagnosis.

Referring to FIG. 2, the conventional fault diagnosis method includes a reset signal input step (S10), a reference clock confirmation step (S20), a fault signal input step (S30), a signal input maintenance judgment step (S40) And a determination step (S50).

In the reset signal input step S10, the reference clock confirmation step S20 and the failure signal input step S30, the programmable logic element 20 receives the reset signal 13 from the control unit 10 The reference clock 3 is raised and the fault signal 21 is received when the sensor signal 11 inputted to the control unit 10 exceeds the predetermined voltage. Thereafter, in the signal input maintenance judgment step (S40) and the fault confirmation step (S50), when the inputted fault signal (21) is maintained for the predetermined time, the programmable logic element (20) confirms the fault diagnosis.

However, if the reset signal 13 is erroneously applied to the programmable logic device 20 or unintentionally applied to the programmable logic device 20 due to ambient noise in the fault-confirmed state, There is a problem that the power element 41 or the like of the vehicle is damaged or the power conversion system malfunctions. 3, when any one of the reset signals 13 for the plurality of sensors is input to the programmable logic device 20 unintentionally by ambient noise, The PWM OFF signal 22 outputted from the PWM OFF signal 22 is released. In this case, the PWM signal 12 from the controller 10 and the PWM signal 32 from the PWM buffer are applied to the power device 41 of the gate board 40 so that the power device 41 is damaged It can be.

Therefore, it is possible to prevent the malfunction of the fault diagnosis circuit, which prevents the fault diagnosis from being unintentionally generated due to the occurrence of the noise-sensitive reset signal 13 which is shorter than the cycle of the reference clock 3 in the fault diagnosis circuit for detecting the fault synchronized with the reference clock A method is needed.

JP 1993-310097 JP 2010-231490

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems, and it is an object of the present invention to provide a programmable logic device (CPLD) It is an object of the present invention to provide a malfunction prevention method for a malfunction diagnosis circuit which prevents malfunction diagnosis circuit from releasing a PWM OFF signal by a noise-like reset signal by fixing an input reset signal to a normal reset signal.

In order to achieve the above object, according to an embodiment of the present invention, there is provided a method for preventing a malfunction of a fault diagnosis circuit, comprising the steps of: determining whether a reset signal input from a control unit to a programmable logic device (CPLD) step; A clock determining step of determining whether the reference clock input to the programmable logic device (CPLD) is a rising edge when the reset signal is shorter than a predetermined time; Determining whether a fault signal is input to the programmable logic device (CPLD) when the input reference clock is a rising edge; A signal maintenance determination step of determining whether the input fault signal is maintained for a predetermined time when a fault signal is input to the programmable logic device (CPLD); And a fault diagnosis confirmation step of confirming a fault diagnosis when the input fault signal is maintained for a predetermined period of time; . ≪ / RTI >

In this case, the reset signal determination step may include: a reset signal input step of determining whether the reset signal is input to the control unit rotor programmable logic device (CPLD); A clock input step of determining whether a reference clock input to the programmable logic device (CPLD) is a rising edge when the reset signal is input; A reset signal holding determination step of determining whether the input reset signal is shorter than a predetermined time when the input reference clock is a rising edge; And a reset determination step of determining the input reset signal as a normal reset signal input when the input reset signal is not shorter than a predetermined time; . ≪ / RTI >

Determining whether the reset signal is not input when the reset signal is not input after the reset signal input step; Can be performed.

Also, after the clock input step, the reset signal determination step may be terminated if the input reference clock is not a rising edge.

Determining whether the reset signal is not input when the input reset signal is shorter than a predetermined time after the reset signal maintenance determination step; Can be performed.

According to the malfunction prevention method of the failure diagnosis circuit according to the present invention, by distinguishing the reset signal inputted to the programmable logic element (CPLD) from the noise-like reset signal, the failure diagnosis circuit cancels the PWM OFF signal by the noise- Thereby preventing the power device from being damaged or malfunctioning the power conversion system.

1 is a block diagram showing a fault diagnosis circuit using a programmable logic device (CPLD);
Figure 2 is a flow diagram illustrating a method of diagnosing faults in a programmable logic device (CPLD)
FIG. 3 is a diagram showing the application of a PWM signal by releasing a PWM OFF signal when a noise-sensitive reset signal is input in a fault diagnosis circuit using a programmable logic device (CPLD) according to the prior art.
4 is a flowchart showing a malfunction prevention method of a fault diagnosis circuit according to the present invention.
5 is a flowchart showing a reset signal determination step of a malfunction prevention method of a failure diagnosis circuit according to the present invention.
6 is a diagram showing that the PWM OFF signal is not released when a noise-based reset signal is input in the malfunction prevention method of the failure diagnosis circuit according to the present invention.

It is noted that the technical terms used herein are used only to describe specific embodiments and are not intended to limit the invention. Also, the technical terms used herein should be interpreted in a sense that is generally understood by those skilled in the art to which the present disclosure relates, unless otherwise specifically defined in the present specification, Or shall not be construed to mean excessively reduced. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. But is to be understood as including all modifications, equivalents, and alternatives falling within the scope of the appended claims.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a malfunction prevention method of a fault diagnosis circuit according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 4 is a flowchart showing a malfunction prevention method of the fault diagnosis circuit according to the present invention, FIG. 5 is a flowchart showing a reset signal judgment step of the malfunction prevention method of the fault diagnosis circuit according to the present invention, The PWM OFF signal is not released when a noise-canceling reset signal is input in the malfunction prevention method of the fault diagnosis circuit.

Referring to FIGS. 4 to 6, an embodiment of a malfunction prevention method for a failure diagnosis circuit according to the present invention includes a reset signal determination step S100, a clock determination step S200, a failure signal input determination step S300, A signal maintenance determination step (S400), and a fault diagnosis determination step (S500).

In the reset signal determination step S100, it is determined whether the reset signal 13 input from the control unit 10 to the programmable logic device (CPLD) 20 is shorter than a predetermined time. That is, in the reset signal determination step S100, the controller 10 outputs the reset signal 13 to the programmable logic device 20 in order to cancel the confirmed trouble diagnosis. The programmable logic device 20 then receives the reset signal 13 from the control unit 10 and determines whether the reset signal 13 is a reset signal 4 normally input from the control unit 10 Or the noise-like reset signal 5. More specifically, the reset signal determination step S100 may include a reset signal input step S110, a clock input step S120, a reset signal maintenance determination step S130, and a reset determination step S140 .

In the reset signal input step S110, the controller 10 determines whether the reset signal 13 is input to the programmable logic device (CPLD) 20. That is, in the reset signal input step S110, when the controller 10 outputs the reset signal 13 to the programmable logic device 20 in order to cancel the determined trouble diagnosis, The controller 20 can determine whether the reset signal 13 is input from the controller 10.

In addition, after the reset signal input step S110, if the reset signal 13 is not input, it is determined that the reset signal 13 is not inputted. More specifically, when the reset signal 13 is not input from the control unit 10 to the programmable logic device 20 after the reset signal input step S110, the programmable logic device 20 It may be determined that the reset signal 13 is not input and the clock determination step S200 may be performed. That is, in the malfunction prevention method according to the present invention, the reset signal 13 is determined as the normal reset signal 4 only when the reset signal 13 is held for the predetermined time, (S600) for releasing the diagnosis of the failure of the vehicle.

In the clock input step S120, when the reset signal 13 is input, it is determined whether the reference clock 3 input to the programmable logic device (CPLD) 20 is a rising edge. That is, the clock input step S120 may determine whether the reference clock 3 input to synchronize the input of the reset signal 13 on the rising edge of the reference clock 3 is a rising edge.

In addition, after the clock input step S120, if the input reference clock 3 is not a rising edge, the reset signal determination step S100 may be terminated. More specifically, after the clock input step S120, if the input reference clock 3 is not a rising edge, it is determined that the reset signal 13 is not inputted to the programmable logic element 20 , And the clock determination step (S200). That is, in the malfunction prevention method according to the present invention, the reset signal 13 is determined as the normal reset signal 4 only when the reset signal 13 is held for the predetermined time, (S600) for releasing the failure diagnosis of the vehicle

In the reset signal maintenance determination step S 130, if the input reference clock 3 is a rising edge, it is determined whether the input reset signal 13 is shorter than a predetermined time. More specifically, in the reset signal maintenance determination step (S130), the programmable logic device (1) determines whether the reset signal (4) or the noise-based reset signal (5) It is determined whether the reset signal 13 inputted to the controller 20 is shorter than a predetermined time. Here, the predetermined time may be obtained through experiments of the actual vehicle in such a time that the normal reset signal 4 and the noise-like reset signal 5 can be distinguished from each other, and may be several microseconds in particular. That is, in the reset signal maintenance determination step S130, the reset signal 13 is determined as a normal reset signal 4 only when the input of the reset signal 13 is maintained for a predetermined time, Thereby preventing malfunction of the fault diagnosis circuit 1 due to the signal 5.

If it is determined that the reset signal 13 is not input when the input reset signal 13 is shorter than the predetermined time after the reset signal maintenance decision step 130, Can be performed. More specifically, when the input reset signal 13 is less than the predetermined time after the reset signal maintenance determination step S 130, it is determined that the reset signal 13 is not input and the clock determination step S200 ). ≪ / RTI > That is, in the malfunction prevention method according to the present invention, the reset signal 13 is determined as the normal reset signal 4 only when the reset signal 13 is held for the predetermined time, (S600) for releasing the failure diagnosis of the vehicle

In the reset determination step S140, if the input reset signal 13 is not shorter than the predetermined time, the input reset signal 13 is determined as a normal reset signal 5 input. That is, when the input of the reset signal 13 is not shorter than the predetermined time, the reset determination step S140 determines the reset signal 13 as a normal reset signal 5 input, (S600) for releasing the fault diagnosis confirmation of the fault diagnosis (S600). Here, in the failure diagnosis release step S600, after the reset signal determination step S100, the reset signal 13 input from the control unit 10 to the programmable logic device 20 is shorter than a predetermined time The fault diagnosis determination of the fault diagnosis circuit may be canceled.

The reset signal determination step S100 determines whether the reset signal 13 input from the control unit 10 to the programmable logic device CPLD 20 is shorter than a predetermined time, And distinguishes the noise-like reset signal 5 shorter than the predetermined time. Referring to FIG. 6, the effect of the malfunction prevention method of the fault diagnosis circuit according to the present invention can be confirmed. 6, when any one of the reset signals 13 for the plurality of sensors is input to the programmable logic element 20 unintentionally by ambient noise, It can be confirmed that the PWM OFF signal 22 outputted from the PWM OFF signal 22 is not released. That is, even when any one of the reset signals 13 for the plurality of sensors is input to the programmable logic element 20 unintentionally due to ambient noise, the output from the programmable logic element 20 The PWM signal 12 from the control unit 10 and the PWM signal 32 from the PWM buffer are applied to the power device 41 of the gate board 40 So that the power device 41 can be prevented from being damaged.

In the clock determination step S200, if the reset signal 13 is shorter than the predetermined time, it is determined whether the reference clock 3 input to the programmable logic device (CPLD) 20 is a rising edge. That is, when the normal reset signal 4 is not input in the reset signal determination step S100, the rising edge of the reference clock 3 is determined to be the fault It is possible to determine whether the input reference clock 3 is a rising edge in order to synchronize the input of the signal 21.

In the failure signal input determination step S300, it is determined whether the failure signal 21 is input to the programmable logic device (CPLD) 20 when the input reference clock 3 is on the rising edge. Here, the failure signal 21 may be a failure signal for a plurality of sensors or devices. That is, the number of the fault signals 21 may be plural.

If the failure signal 21 is input to the programmable logic device (CPLD) 20, the signal maintenance determination step S400 determines whether the input failure signal 21 is maintained for a predetermined period of time. That is, in the signal maintenance determination step S400, when one or more failure signals 21 are input, it is determined whether the input of the one or more failure signals 21 is maintained for a predetermined time. Here, the predetermined time may be determined through an actual vehicle test in such a time that the fault signal 21 can be distinguished from a normal fault signal, and may be several microseconds in particular.

In the fault diagnosis determination step S500, when the input fault signal 21 is maintained for a predetermined time, the fault diagnosis is confirmed. That is, in the fault diagnosis determination step S500, when the reset signal 13 is not present or is short in the reset signal determination step S100 and the failure signal 21 is constant The fault diagnosis can be confirmed for at least one fault signal 21 satisfying the condition.

In addition, after the reset signal determination step S100, if the reset signal 13 is not shorter than the predetermined time, a failure diagnosis release step S600 of canceling the failure diagnosis determination of the failure diagnosis circuit 1 may be performed have.

It will be apparent to those skilled in the art that many other modifications and variations are possible in light of the above teachings and the scope of the present invention should be construed on the basis of the appended claims something to do.

1: Fault diagnosis circuit
2: Failure situation
3: Reference Clock
4: Noise-canceling reset signal
10:
11: Sensor signal input to the control unit
12: PWM signal outputted from the control unit
13: a reset signal
14: PWM OFF signal output from the control unit
20: Complex Programmable Logic Device (CPLD)
21: Fault signal input to CPLD
22: PWM OFF signal output from CPLD
23: Confirmation signal output from CPLD
30: Pulse width modulation (PWM)
31: Enable of PWM buffer 32: PWM buffer output PWM signal
40: gate board
41: Power device
50: Logic element (AND gate)
51: PWM OFF signal output from the logic element

Claims (5)

A method for preventing malfunction of a fault diagnosis circuit,
A reset signal determination step of determining whether a reset signal input from the control unit to the programmable logic device (CPLD) is shorter than a predetermined time;
A clock determining step of determining whether the reference clock input to the programmable logic device (CPLD) is a rising edge when the reset signal is shorter than a predetermined time;
Determining whether a fault signal is input to the programmable logic device (CPLD) when the input reference clock is a rising edge;
A signal maintenance determination step of determining whether the input fault signal is maintained for a predetermined time when a fault signal is input to the programmable logic device (CPLD); And
Determining a fault diagnosis when the input fault signal is maintained for a predetermined period of time;
And a fault diagnosis circuit for detecting a malfunction of the fault diagnosis circuit.
The method according to claim 1,
Wherein the reset signal determination step comprises:
A reset signal input step for determining whether the reset signal is input from the control unit to the programmable logic element (CPLD);
A clock input step of determining whether a reference clock input to the programmable logic device (CPLD) is a rising edge when the reset signal is input;
A reset signal maintenance determination step of determining whether the input reset signal is maintained for a predetermined time when the input reference clock is a rising edge; And
A reset determination step of determining the input reset signal as a normal reset signal input when the input reset signal is not shorter than a predetermined time;
And a fault diagnosis circuit for detecting a malfunction of the fault diagnosis circuit.
3. The method of claim 2,
After the reset signal input step,
A reset non-input determining step of determining that the reset signal is not input when the reset signal is not input;
And a fault diagnosis circuit for detecting a malfunction of the fault diagnosis circuit.
3. The method of claim 2,
After the clock input step,
And terminating the reset signal determination step when the input reference clock is not a rising edge.
3. The method of claim 2,
After the reset signal maintenance determination step,
A reset non-input determining step of determining that the reset signal is not input when the input reset signal is shorter than a predetermined time;
And a fault diagnosis circuit for detecting a malfunction of the fault diagnosis circuit.
KR1020140157230A 2014-11-12 2014-11-12 Method for preventing malfunction of failure diagnosis circuit KR101584009B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113315499A (en) * 2021-06-25 2021-08-27 阳光电源股份有限公司 Driving method, driving circuit and controller of power device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05310097A (en) 1992-05-12 1993-11-22 Fujitsu Ten Ltd Troubleshooting device for air bag
JP3230471B2 (en) * 1997-11-12 2001-11-19 日本電気株式会社 PWM control device and PWM control method
KR100321906B1 (en) * 1999-12-23 2002-01-26 신현준 Integrated controller of AC motor
KR20030022560A (en) * 2001-09-11 2003-03-17 현대중공업 주식회사 Device for instantaneous protection considered off time of IGCT
JP2010231490A (en) 2009-03-27 2010-10-14 Nittan Co Ltd Circuit board for control of failure transfer signal output due to cpu reset
JP4993249B2 (en) * 2004-10-21 2012-08-08 ゼネラル・エレクトリック・カンパニイ Event-based operating system, method, and apparatus for measurement and control systems

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05310097A (en) 1992-05-12 1993-11-22 Fujitsu Ten Ltd Troubleshooting device for air bag
JP3230471B2 (en) * 1997-11-12 2001-11-19 日本電気株式会社 PWM control device and PWM control method
KR100321906B1 (en) * 1999-12-23 2002-01-26 신현준 Integrated controller of AC motor
KR20030022560A (en) * 2001-09-11 2003-03-17 현대중공업 주식회사 Device for instantaneous protection considered off time of IGCT
JP4993249B2 (en) * 2004-10-21 2012-08-08 ゼネラル・エレクトリック・カンパニイ Event-based operating system, method, and apparatus for measurement and control systems
JP2010231490A (en) 2009-03-27 2010-10-14 Nittan Co Ltd Circuit board for control of failure transfer signal output due to cpu reset

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113315499A (en) * 2021-06-25 2021-08-27 阳光电源股份有限公司 Driving method, driving circuit and controller of power device

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