KR20030017751A - Semiconductor device having dual gate insulating layer and method of fabricating the same - Google Patents

Abstract

PURPOSE: A semiconductor device having a dual gate insulating layer and a method for fabricating the same are provided to reduce overlap capacitance by increasing thickness of a gate insulating layer between a gate electrode and a source/drain region. CONSTITUTION: A medium material pattern is formed on a semiconductor substrate(40). The first gate insulating layer(48) is formed on the semiconductor substrate(40). A couple of spacers are formed by depositing and etching the first gate electrode forming material layer on the semiconductor substrate(40). The second gate insulating layer(52) is formed on the semiconductor substrate(40) between the spacers. The second gate electrode forming material layer is deposited on the semiconductor substrate(40). The second gate electrode forming material layer and the second gate insulating layer(52) are etched. A gate electrode including the first gate electrode portion(50), the second gate electrode portion(54), and the third gate electrode portion(56) is formed on the semiconductor substrate(40).

Description

Semiconductor device having dual gate insulating layer and method of fabricating the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a double gate insulating layer and a method of manufacturing the same, and more particularly, to a semiconductor device having a double gate insulating layer and multiple gate electrodes formed in a single MOS transistor, and a fabrication thereof. It is about a method.

Because of their simple structure and low production cost, MOS transistors have emerged as the most important semiconductor devices far ahead of bipolar junction transistors in sales markets and applications.

The MOS transistor is a four-terminal device in which the lateral current flow is controlled by a vertical electric field applied from the outside, where four terminals mean a source, a drain, a gate, and a substrate. When no voltage is applied to the gate, the pn junction formed between the drain and the source hinders the flow of current in each direction, and when a positive voltage is applied to the gate to the substrate, the flowing (-) charge is the metal-oxide interface. Induced below, this carrier forms a conductive channel region between the source and the drain. Therefore, since the current is regulated not only by the lateral electric field but also by the vertical electric field, it is called a field effect transistor (FET).

1 is a cross-sectional view showing a general MOS transistor having a conventional LDD structure.

Referring to FIG. 1, an element isolation region 42, for example, a trench element isolation region, is formed near the surface of the semiconductor substrate 20 to define an element active region, and is defined by the element isolation region 42. In the device active region, a channel region in which carrier charges are induced and a source / drain region spaced apart by a predetermined distance from each other with the channel region interposed therebetween are formed. The source / drain region is formed of a lightly doped drain (LDD) structure. That is, the portions adjacent to the channel region by the first low concentration ion implantation region 30 and the second high concentration ion implantation region 32 are relatively implanted with impurity ions at low concentration, and the further away from the channel region, Relatively high concentrations of impurity ions are injected.

On the other hand, a gate insulating layer 24, for example, a gate oxide layer, is formed on the channel region of the semiconductor substrate 20, and a gate electrode 26, for example, gate polysilicon, is formed on the gate insulating layer 24. Formed. An insulating spacer 28, for example an oxide spacer, is formed on the sidewall of the gate electrode 26. Meanwhile, the first low concentration ion implantation region 30 is formed by an ion implantation process using the gate electrode 26 as an ion implantation mask, and the second high concentration ion implantation region 32 is the gate electrode ( 26 is formed by an ion implantation process after forming the insulating spacers 28 formed on the sidewalls.

On the other hand, according to the trend of high integration of semiconductor devices, design rules are gradually decreasing, and accordingly, the thickness of the gate insulating layer is also getting thinner. In particular, the thickness of the gate insulating layer at the edge of the gate electrode overlapping with the source / drain regions is increased. The thinner the film, the greater the overlap capacitance, which in turn slows the transistor's operating speed, leading to degradation of product performance. This overlap capacitance is one of the most influential parameters for the operating speed of the transistor.

Since the overlap capacitance of the overlapping portions of the gate electrode and the source / drain regions is formally proportional to the effective sectional area overlapping with the dielectric constant of the gate insulating layer as a dielectric material positioned between them, and inversely proportional to the thickness of the gate insulating layer, The lower the thickness of the insulating layer, the greater the overlap capacitance. This causes an increase in the time constant because the time constant for determining the operation speed of the device is proportional to the capacitance, resulting in a slow operation speed of the device.

Conventionally, in order to solve this problem, a method of enhancing annealing time during the post-oxidation process of forming a gate electrode pattern has been used. In this case, the thickness of the gate insulating layer of the portion where the edge of the gate electrode overlaps with the source / drain region is used. The thickening effect has the effect of reducing the overlap capacitance. However, in this conventional method, the saturation drain current may drop because impurity ions are not sufficiently implanted and diffused in the subsequent ion implantation process to form the source / drain regions according to the thickness of the gate insulating layer. Of course, thermal annealing can be sufficiently performed for sufficient diffusion of impurity ions, but there is a limit that thermal annealing time should be minimized due to the limitation of thermal budget in order to direct shallow junction.

SUMMARY OF THE INVENTION An object of the present invention is to overcome the problems of the prior art, and to increase the thickness of the gate insulating layer between the gate electrode and the source / drain region without deliberately increasing the thermal annealing time, thereby reducing the overlap capacitance. A semiconductor device having a layer and a method of manufacturing the same are provided.

1 is a cross-sectional view illustrating a MOS transistor having a conventional lightly doped drain (LDD) structure.

2 to 6 are cross-sectional views illustrating a process of manufacturing a semiconductor device having a double gate insulating layer according to an embodiment of the present invention.

7 is a cross-sectional view illustrating a MOS transistor having an LDD structure having a double gate insulating layer manufactured according to an exemplary embodiment of the present invention.

A semiconductor device having a double gate insulating layer according to the present invention for achieving the object of the present invention includes a semiconductor substrate having a source region and a drain region on both sides of the channel region; A pair of first gate insulating layers respectively formed near a junction between the channel region and the source region and above a junction between the channel region and the drain region; A second gate insulating layer formed between the pair of first gate insulating layers and having a thickness lower than that of the first gate insulating layer; And a gate electrode formed on the pair of first gate insulating layers and the second gate insulating layer.

Preferably, the second gate insulating layer may include a second protrusion protruding at a predetermined height into the gate electrode at each contact portion with the pair of first gate insulating layers, wherein the gate electrode includes: A pair of first gate electrode portions formed on the pair of first gate insulating layers; A second gate electrode part formed on the second gate insulating layer and separated from the first gate electrode part by the second protrusion; And a third gate electrode part formed on the first gate electrode part and the second gate electrode part to connect the first gate electrode part and the second gate electrode part. In addition, the first gate insulating layer may have a first protrusion that protrudes by a predetermined height along the outer walls of the pair of first gate electrodes.

On the other hand, it is preferable that the thickness of the first gate insulating layer is 50 to 100 GPa, and the thickness of the second gate insulating layer is 5 to 30 GPa.

On the other hand, a method of manufacturing a semiconductor device having a double gate insulating layer according to the present invention for achieving the object of the present invention, forming a pattern of the intermediate material for exposing a portion where the gate electrode is to be formed on the semiconductor substrate; Forming a first gate insulating layer on the semiconductor substrate exposed by the intermediate material pattern; The first gate electrode layer forming material layer is deposited on the entire surface of the semiconductor substrate on which the first gate insulating layer is formed, and then etched to the entire surface to form a pair of the first gate electrode part forming material layer on each sidewall of the intermediate material pattern. Exposing the semiconductor substrate therebetween while forming a spacer therebetween; Forming a second gate insulating layer on the semiconductor substrate exposed between the pair of spacers; Depositing a second gate electrode part forming material layer on an entire surface of the semiconductor substrate on which the second gate insulating layer is formed; Etching the entire surface of the second gate electrode forming material layer and the second gate insulating layer to expose a portion of the surface of the spacer; And depositing a third gate electrode part forming material layer on the entire surface of the semiconductor substrate to form a gate electrode in which the first gate electrode part, the second gate electrode part, and the third gate electrode part are electrically connected to each other. do.

The forming of the gate electrode may be performed by etching the third gate electrode forming material layer until the surface of the intermediate material pattern is exposed to planarize the surface, for example, by a chemical mechanical polishing process. After that, the method may further include removing the intermediate material pattern to complete the gate electrode pattern.

The intermediate material pattern may be formed of a material having an etch selectivity with the gate insulating layer and the gate electrode forming material layer, for example, silicon nitride, and the first and second gate insulating layers may be formed of silicon oxide. .

In addition, the thickness of the second gate insulating layer is thinner than the thickness of the first gate insulating layer, preferably, the thickness of the first gate insulating layer is 50 to 100 kPa, and the second gate insulating layer The thickness of can be 5 to 30Å, it can be carried out by a thermal oxidation process or a general deposition process.

According to the present invention, the thickness of the gate insulating layer at the overlapping portion of the gate electrode and the source / drain region than at the upper side of the channel region in the gate electrode forming step regardless of the annealing for the thermal oxidation process performed after the gate electrode is formed. Since the thickness can be thickened, the overlap capacitance can be reduced.

Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments described below may be modified in many different forms, and the scope of the present invention is not limited to the embodiments described below. The embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. In the drawings illustrating embodiments of the present invention, the thicknesses of certain layers or regions are exaggerated for clarity of specification. In addition, where a layer is described as being "top" of another layer or substrate, the layer may be present directly on top of the other layer or substrate, with a third layer intervening therebetween. Moreover, while the terms "first conductivity type" and "second conductivity type" refer to opposite conductivity types, such as N-type or P-type, each embodiment described and described herein also refers to its complementary embodiment. Include. Like numbers refer to like elements throughout.

First, a semiconductor device having a double gate insulating layer according to the present invention will be described. 7 is a cross-sectional view illustrating a MOS transistor having an LDD structure according to an embodiment of the present invention.

Referring to FIG. 7, an element isolation region 42, for example, a trench element isolation region, is formed in the vicinity of the surface of the semiconductor substrate 40 into which the first conductivity type impurity is implanted. In the device active region defined by the isolation region 42, impurities of the second conductivity type, which are spaced apart from each other by a predetermined distance with the channel region interposed therebetween and the channel region where a carrier charge of the second conductivity type is induced on the surface thereof, are formed. An implanted source / drain region is formed. The source / drain regions are formed in a lightly doped drain (LDD) structure to mitigate short-channel effects. The source / drain region having the LDD structure includes a first low concentration ion implantation region 60 formed by primary ion implantation injecting relatively low ion implantation energy and low concentration impurity ions using a gate electrode pattern as an ion implantation mask. ) And the second high concentration formed by the second ion implantation injecting relatively high ion implantation energy and high concentration of impurity ions as the ion implantation mask using the spacer formed on the sidewall of the gate electrode pattern as an ion implantation mask. It is composed of the ion implantation region 62, the portion adjacent to the channel region is implanted with a relatively thin impurity ions at a low concentration, the impurity ions are implanted deeply at a high concentration as the distance away from the channel region.

On the other hand, on the channel region of the semiconductor substrate 40, a double gate insulating layer composed of the first gate insulating layer 48 and the second gate insulating layer 52 is formed of, for example, an oxide film. In addition, on the first and second gate insulating layers 48 and 52, a triple gate electrode including a first gate electrode part 50, a second gate electrode part 54, and a third gate 26 is provided. For example, it is formed of polysilicon.

The first gate insulating layer 48 is formed to a thickness of about 50 kPa to 100 kPa, and the second gate insulating layer 52 is formed to a thickness of about 5 kPa to 30 kPa. In addition, the first gate insulating layer 48 may include a first protrusion protruding upwardly to be substantially similar to the height of the first gate electrode 50 along the outer wall of the first gate electrode 50. The insulating layer 52 may start at the contact portion with the first gate insulating layer 48 and may be disposed along the boundary between the first gate electrode portion 50 and the second gate electrode portion 54. A second protrusion protruding upwards, substantially similar to the height of 54). The first gate electrode part 50 and the second gate electrode part 54 are electrically separated from each other by the second protrusion of the second gate insulating layer 48.

Meanwhile, a third gate electrode part 56 is formed on the first gate electrode part 50 and the second gate electrode part 54, and the first gate electrode is formed by the third gate electrode part 56. The unit 50 and the second gate electrode unit 54 are electrically connected to each other to form one gate electrode pattern. An insulating spacer 58, for example, an oxide spacer, is formed on the sidewall of the gate electrode pattern.

Next, a method of manufacturing a semiconductor device having a double gate insulating layer according to the present invention will be described. 2 to 7 are process cross-sectional views illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention.

First, referring to FIG. 2, a medium material pattern having an opening for exposing a portion where a gate electrode is to be formed is formed on a surface of the semiconductor substrate 40. The intermediate material pattern is a part removed from the final semiconductor device, and is selected from materials having an etch selectivity with respect to polysilicon or silicon oxide formed by a subsequent process. In this embodiment, the silicon nitride layer 46 is used, and the pad oxide layer 44 may be further formed to prevent direct contact between the silicon nitride layer 46 and the semiconductor substrate 40. The thickness of the silicon nitride layer 46 was set in consideration of the height of the gate electrode to be formed, and was formed to a thickness of about 2000 kPa in this embodiment. In addition, the width of the opening of the intermediate material pattern is set in advance in consideration of the width of the gate electrode. After the photoresist is coated on the silicon nitride layer 46, an opening is formed to expose the surface of the semiconductor substrate 40 by a general photolithography process.

On the other hand, before forming the intermediate material pattern, a device isolation process is performed on the semiconductor substrate 40 in advance, so that a device isolation region 42 is formed, and the device active region is formed by these device isolation regions 42. It is limited. In the present embodiment, the device isolation region 42 is a trench device isolation region and is formed by a conventional trench device isolation process.

Subsequently, referring to FIG. 3, the first gate insulating layer 48 is formed on the entire surface of the semiconductor substrate 40 where the opening is formed to be relatively thick, for example, 50 to 100 microns thick. A silicon oxide material may be used as the material for forming the first gate insulating layer 48, and may be formed by a general deposition process or a thermal oxidation process. Subsequently, polysilicon is formed on the entire surface of the semiconductor substrate 40 on which the first gate insulating layer 48 forming material is formed to have a thickness of about 1000 mW as the first gate electrode part 50 forming material, and then the entire surface is etched. Spacers are formed in the sidewalls of the openings of the silicon nitride 46. In this case, the front surface etching process is performed until the semiconductor substrate 40 at the center portion of the opening is exposed.

Meanwhile, by implanting impurities into the exposed semiconductor substrate 40 using the polysilicon spacer as an ion implantation mask, ion implantation for well formation of a transistor or ion implantation for adjusting the threshold voltage of the transistor can be performed. have.

Next, referring to FIG. 4, a material layer for forming a second gate insulating layer 52, for example, a silicon oxide layer, is formed on the entire surface of the semiconductor substrate 40 on which the polysilicon spacer is formed. It is formed by a general deposition process or a thermal oxidation process to a thickness of about 5 ~ 30Å thinner than the thickness. Subsequently, the second gate electrode part 54 forming material, for example, polysilicon, is formed on the second gate insulating layer 52 forming material so that the entirety of the opening is buried.

Next, referring to FIG. 5, the first gate electrode is applied to the polysilicon layer, which is a material layer of the second gate electrode part 54 formed on the uppermost layer of the semiconductor substrate 40, by applying a chemical mechanical polishing process or an etch back process. The height of the second gate insulating layer 52 formed at the boundary between the portion 50 forming material layer and the second gate electrode portion 54 forming material layer is sufficiently reduced, and the height of the material forming layer of the first gate electrode part 50 is reduced. Allow the surface to be at least partially exposed. This is for enabling electrical connection between the first gate electrode part 50 forming material layer and the second gate electrode part 54 forming material layer by the third gate electrode forming material layer formed by a subsequent process. will be.

Subsequently, referring to FIG. 6, the silicon nitride layer may include a material layer forming the third gate electrode part 56 on the entire surface of the semiconductor substrate 40 on which a portion of the surface of the material forming layer of the first gate electrode part 50 is exposed. It is formed thick so that the opening part in 46 may be fully buried. Subsequently, a surface planarization process such as a chemical mechanical polishing (CMP) process is performed to remove the material layer forming the third gate electrode part 56 until the surface of the silicon nitride layer 46 is exposed, thereby removing the first gate electrode. The formation of the triple gate electrode consisting of the portion 50, the second gate electrode portion 54, and the third gate electrode portion 56 is completed.

7, after selectively removing the silicon nitride layer 46 and the pad oxide layer 44 except for the gate electrode, the gate electrode pattern remaining on the semiconductor substrate 40 may be replaced by an ion implantation mask. As a result, a first ion implantation process is performed with relatively low concentration of impurity ions at a relatively low ion implantation energy to form a first low concentration ion implantation region 60 aligned with the sidewall of the gate electrode pattern. An insulating layer, for example, a silicon oxide layer is formed on the entire surface of the semiconductor substrate 40 and then etched to form an insulating spacer 58 on the sidewall of the gate electrode pattern. Subsequently, the second ion implantation process is performed by using a relatively high concentration of impurity ions with a relatively high ion implantation energy, using the gate electrode pattern and the insulating spacer 58 as an ion implantation mask. A second high concentration ion implantation region 62 is formed in the substrate 40. Thereafter, a conventional semiconductor device manufacturing process such as a salicide process and a metal wiring process is performed to complete the manufacture of the semiconductor device.

Although the embodiments of the present invention have been described in detail above, the present invention is not limited thereto, and various modifications can be made by those skilled in the art within the scope of the present invention. For example, the material of the intermediate material pattern, the thickness of the first gate insulating layer and the second gate insulating layer, and the like can be freely selected and set.

According to the present invention, after the gate electrode pattern is formed, the gate electrode and the source are formed in advance in the process of forming the gate electrode without having to excessively perform the annealing time during the subsequent thermal oxidation process to increase the thickness of the gate insulating layer. Since the thickness of the portion of the overlapping gate insulating layer between the / drain regions can be arbitrarily formed sufficiently thick, it is possible to easily reduce the overlap capacitance.

Claims (12)

A semiconductor substrate having source and drain regions formed on both sides of the channel region; A pair of first gate insulating layers respectively formed near a junction between the channel region and the source region and above a junction between the channel region and the drain region; A second gate insulating layer formed between the pair of first gate insulating layers and having a thickness lower than that of the first gate insulating layer; And And a double gate insulating layer including a gate electrode formed on the pair of first gate insulating layers and the second gate insulating layer. The double gate of claim 1, wherein the second gate insulating layer includes a second protrusion protruding at a predetermined height into the gate electrode at each contact portion of the pair of first gate insulating layers. A semiconductor device having an insulating layer. The method of claim 2, wherein the gate electrode, A pair of first gate electrode portions formed on the pair of first gate insulating layers; A second gate electrode part formed on the second gate insulating layer and separated from the first gate electrode part by the second protrusion; And And a third gate electrode formed on the first gate electrode part and the second gate electrode part to connect the first gate electrode part and the second gate electrode part. device. 4. The semiconductor device according to claim 3, wherein the first gate insulating layer has a first protrusion protruding by a predetermined height along an outer wall of the pair of first gate electrodes. . The semiconductor device according to claim 1, wherein the first gate insulating layer has a thickness of 50 to 100 GPa, and the second gate insulating layer has a thickness of 5 to 30 GPa. The semiconductor device of claim 1, wherein the source region and the drain region have an impurity region having an LDD structure. Forming a medium material pattern exposing a portion where a gate electrode is to be formed on the semiconductor substrate; Forming a first gate insulating layer on the semiconductor substrate exposed by the intermediate material pattern; The first gate electrode layer forming material layer is deposited on the entire surface of the semiconductor substrate on which the first gate insulating layer is formed, and then etched to the entire surface to form a pair of the first gate electrode part forming material layer on each sidewall of the intermediate material pattern. Exposing the semiconductor substrate therebetween while forming a spacer therebetween; Forming a second gate insulating layer on the semiconductor substrate exposed between the pair of spacers; Depositing a second gate electrode part forming material layer on an entire surface of the semiconductor substrate on which the second gate insulating layer is formed; Etching the entire surface of the second gate electrode forming material layer and the second gate insulating layer to expose a portion of the surface of the spacer; And And depositing a third gate electrode part forming material layer on the entire surface of the semiconductor substrate to form a gate electrode in which the first gate electrode part, the second gate electrode part, and the third gate electrode part are electrically connected to each other. A method of manufacturing a semiconductor device having a double gate insulating layer. The method of claim 7, wherein the forming of the gate electrode is performed by etching the third gate electrode forming material layer to planarize the surface until the surface of the intermediate material pattern is exposed. The method of manufacturing a semiconductor device having a double gate insulating layer, further comprising the step of removing the pattern. The method of claim 7, wherein the intermediate material pattern is formed of silicon nitride, and the first and second gate insulating layers are formed of silicon oxide. The method of claim 7, wherein a thickness of the second gate insulating layer is thinner than a thickness of the first gate insulating layer. The method of claim 10, wherein the thickness of the first gate insulating layer is 50 to 100 GPa, and the thickness of the second gate insulating layer is 5 to 30 GPa. . 8. The double gate insulating layer of claim 7, further comprising: forming a spacer of the first gate electrode forming material layer, and performing ion implantation into the semiconductor substrate using the spacer as an ion implantation mask. A method for manufacturing a semiconductor device having a layer.