KR20030016758A - Liquid crystal display device - Google Patents

Abstract

PURPOSE: A liquid crystal display is provided to prevent movement of current between two gate driving circuits for driving a plurality of gate lines. CONSTITUTION: A liquid crystal display includes a display area(111) where a plurality of pixels are arranged in a matrix form on a substrate(112a), a plurality of data lines(DL1,DLn) for supplying pixel data to each pixel column of the display area, and a data driving circuit(113) arranged in the first region surrounding the display area to drive the data lines. The liquid crystal display further includes the first gate lines(GL1,GLm) for supplying a scan pulse to a part of pixels of each pixel row of the display area, the first gate driving circuit(114) arranged in the second region surrounding the display area to drive the first gate lines, the second gate lines(GLm+1,GL2m) for providing the scan pulse to the other pixels of each pixel row of the display area, and the second gate driving circuit(115) arranged in the third region surrounding the display area to drive the second gate lines.

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY DEVICE}

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of improving the driving characteristics of a gate line.

Recently, information processing devices have been rapidly developed to have various forms, various functions, and faster information processing speed. Information processed in such an information processing device has an electrical signal form. In order for the user to visually check the information processed by the information processing apparatus, a display apparatus that serves as an interface is required.

Recently, a liquid crystal display device has a light weight, a small size, a high resolution, a low power, and can be full-colored compared to a typical CRT display device.

The liquid crystal display is largely divided into twisted nematic (TN) and super-twisted nematic (STN) methods, and due to the difference in driving method, an active matrix display method using a switching element and TN liquid crystal and a passive matrix using STN liquid crystal (passive matrix) display method. The active matrix display method uses a TFT as a switch to drive an LCD.

TFT-LCD is divided into a-Si TFT LCD and poly-Si TFT LCD. Poly-Si TFT LCD has low power consumption and low price, but has a disadvantage of complicated TFT manufacturing process compared to a-Si TFT. Thus, poly-Si TFT LCDs are mainly applied to small display devices such as those of IMT-2000 phones. On the other hand, a-Si TFT LCD has large area and high yield, and is mainly applied to large screen display devices such as notebook PCs, LCD monitors, and HDTVs.

In a poly-si TFT LCD, a data driving circuit and a gate driving circuit for driving data lines and gate lines on a substrate are formed by a poly-si TFT process. In general, the gate driving circuit is disposed on the left side of the display area. But. As the size of the liquid crystal display panel increases, the delay time at the gate line becomes longer, resulting in deterioration of the image quality of the liquid crystal display panel.

In order to solve this problem, gate driving circuits are disposed on both sides of the liquid crystal display panel.

1 is a plan view showing a TFT substrate of a conventional poly-si TFT LCD.

Referring to FIG. 1, a data driving circuit for driving a data region 21 and a gate line 22 formed in the display region 20 and the display region 20 by a poly-si TFT process is performed on the TFT substrate 10. The furnace 30, first and second gate driving circuits 41 and 42 are formed.

The display area 20 is connected to a TFT (not shown) formed by a poly-si TFT process, a transparent pixel electrode (not shown) connected to the drain electrode of the TFT, and a data electrode of the TFT, and the display area 20 A plurality of data lines 21 extending in the column direction of the column and a plurality of gate lines 22 connected to the gate electrode of the TFT and extending in the low direction of the display area 20. do.

The plurality of data lines 21 are respectively connected to the data driving circuit 30 formed at one side of the substrate, and both ends of the plurality of gate lines 22 are formed at left and right regions of the substrate 10, respectively. The first gate driving circuit 41 and the second gate driving circuit 42 are connected to each other.

As such, when the first and second gate driving circuits 41 and 42 are disposed in the left and right regions, the gate lines 22 may be connected to the first and second gate driving circuits 41 and 42 provided in the left and right regions. By driving at the same time, the delay time in the gate line 22 is reduced.

However, due to the operational delay and design problems of the first and second gate driving circuits 41 and 42 by connecting the first and second gate driving circuits 41 and 42 to both ends of the gate line 22. Current movement occurs between the first and second gate driving circuits 41 and 42.

Accordingly, it is an object of the present invention to provide a liquid crystal display device capable of preventing current movement between two gate driving circuits for driving a plurality of gate lines provided on both sides of a substrate.

1 is a schematic view showing the structure of a conventional TFT substrate.

2 is a schematic exploded perspective view of a poly-si TFT LCD according to an embodiment of the present invention.

3 is a schematic diagram showing the configuration of the TFT substrate shown in FIG.

FIG. 4 is a detailed block diagram of the gate driving circuit shown in FIG. 3.

FIG. 5 is a circuit diagram illustrating an RC delay circuit of the gate line of FIG. 4.

6 is a schematic diagram showing a configuration of a TFT substrate according to another embodiment of the present invention.

According to an aspect of the present invention, a liquid crystal display device includes: a display area in which a plurality of pixels are formed in a matrix form on a substrate, a plurality of data lines for supplying pixel data to each pixel column of the display area; A data driving circuit disposed around the first area of the display area to drive the plurality of data lines, a plurality of first gate lines to supply scan pulses to some pixels of each pixel row of the display area, and the display A first gate driving circuit disposed around a second periphery of the region for driving the plurality of first gate lines, and a plurality of second gates for supplying the scan pulse to the remaining partial pixels of each pixel row of the display area A second gate driving circuit disposed around a third line of the display area and the display area to drive the plurality of second gate lines Including furnace.

In the present invention, it is preferable that the number of respective pixels shared by the first gate lines in the pixel rows are all the same. In this case, the number of pixels shared by the first and second gate lines in each pixel row may be the same.

In the present invention, in each odd pixel row, the number of pixels shared by the first gate line is greater than the number of pixels shared by the second gate line, and in each of the even pixel rows, the number of pixels shared by the first gate line is increased. It is desirable that the two gate lines share less than the number of pixels they share.

Further, in the present invention, it is preferable that the number of pixels shared by the first gate line and the number of pixels shared by the second gate line are different from each other in the pixel rows.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

2 is a schematic exploded perspective view of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 2, the liquid crystal display device 100 includes a liquid crystal display panel assembly 110, a backlight assembly 120, a chassis 130, and a cover 140.

The liquid crystal display panel 112 of the liquid crystal display panel assembly 110 includes a TFT substrate 112a and a color filter substrate 112b. A display region 111 (shown in FIG. 4) is formed on the TFT substrate 112a by a poly-si TFT process, and a data driving circuit 113 (shown in FIG. 4) is formed at one side of the display area. And gate driving circuits 114 and 115 (shown in FIG. 4) are formed. RGB pixels and transparent common electrodes are formed on the color filter substrate 112b. The TFT substrate 112a and the color filter substrate 112b are opposed to each other and liquid crystal is injected therebetween and then encapsulated.

The backlight assembly 120 is provided below the liquid crystal display panel 112 to provide light to the liquid crystal display panel 112. The backlight assembly 120 includes a lamp assembly 122, a light guide plate 124, optical sheets 126, a reflector plate 128, and a mold frame 129.

Accordingly, the liquid crystal array is controlled by the voltage applied between the transparent pixel electrode 111e and the transparent common electrode to control the amount of light passing through to display the gray scale of each pixel.

3 is a schematic diagram showing the configuration of the TFT substrate shown in FIG.

Referring to FIG. 3, the TFT substrate 112a includes a data driving circuit 113 for driving the display region 111 and the data lines DL1 and DLn formed in the display region 111 by a poly-si TFT process. First and second gate driving circuits 114 and 115 are formed to drive the first and second gate lines GL1 to GL2m formed in the display area 111.

The display area 111 is a TFT 111a (shown in FIG. 4) formed on the TFT substrate 112a by a poly-si TFT process, and a transparent pixel electrode connected to the drain electrode 111d of the TFT 111a. And a plurality of data lines DL1 to DLn extending in the column direction connected to the source electrode 111b of the TFT 111a and the gate electrode 111c of the TFT 111a, and in a row direction. It includes a plurality of extended gate lines (GL1 ~ GL2m).

The plurality of gate lines GL1 to GL2m are cut off from the first gate lines GL1 to GLm and the first gate lines GL1 to GLm formed to extend on one side of the display area 111. The second gate lines GLm + 1 to GL2m are formed to extend on the other side of the display area 111 to be positioned on the same line as the first gate lines GL1 to GLm.

The plurality of data lines DL1 to DLn of the TFT substrate 112a are connected to the data driving circuit 113 formed at one side of the TFT substrate 112a. In addition, one end of the first gate lines GL1 to GLm is connected to the first gate driving circuit 114, and one end of the second gate lines GLm + 1 to GL2m is connected to the second gate driving circuit ( 115).

As shown in FIG. 3, the lengths of the first and second gate lines GL1 to GLm and GLm + 1 to GL2m are the same, so that the first and second gate lines GL1 to GLm and GLm are the same. The part where +1-GL2m) is cut off is located on the 1/2 line of the display area 111. That is, the same number of pixels of the unit pixels connected to the first and second gate lines GL1 to GLm and GLm + 1 to GL2m are formed.

FIG. 4 is a detailed block diagram of the gate driving circuit shown in FIG. 3. However, the liquid crystal display panel shown in FIG. 4 has 8 × 6 resolution.

Referring to FIG. 4, the display cell array circuit 111 includes eight data lines DL1 to DL8 extending in a column direction, six first gate lines GL1 to GL6 extending in a row direction, and a second one. Gate lines GL7 to GL12.

TFTs 111a for performing switching roles are formed at intersections of the data lines DL1 to DL8 and the first and second gate lines GL1 to GL6 and GL7 to GL12. The data line DL1 is connected to the source electrode of the TFT 111a, and the gate line GL1 is connected to the gate electrode. In addition, a transparent pixel electrode 111b is connected to the drain electrode of the TFT 111a.

The data lines DL1 to DL8 are connected to the data driving circuit 113 formed on the TFT substrate 112a. Meanwhile, one end of the first gate lines GL1 to GL6 is connected to the first gate driving circuit 114 formed on the left side of the TFT substrate 112a and one end of the second gate lines GL7 to GL12. Is connected to the second gate driving circuit 115 formed on the right side of the TFT 112a.

The first gate driving circuit 114 includes a shift register 114a having a plurality of stages SRC1 to SRC7. The shift register 114a includes six stages SRC1 to SRC6 and one dummy stage SRC7 corresponding to six first gate lines GL1 to GL6, and each of the stages SRC1 to SRC6. The output of is provided to the first gate lines GL1 to GL6. The clock signal input terminal CK, the first power supply voltage terminal VOFF or VSS, and the second power supply voltage terminal VON or VDD are connected to each stage SRC1 to SRC6.

The second gate driving circuit 115 includes a shift register 115a having a plurality of stages SRC8 to SRC14. The shift register 115a includes six stages SRC8 to SRC13 and one dummy stage SRC14 corresponding to six second gate lines GL7 to GL12, and each of the stages SRC8 to SRC13. The output of is provided to the second gate lines GL7 to GL12. The clock signal input terminal CK, the first power supply voltage terminal VOFF or VSS, and the second power supply voltage terminal VON or VDD are connected to each stage SRC8 to SRC14.

When the start signal ST is provided to the first stages SRC1 and SRC8 of the first and second gate driving circuits 114 and 115, respectively, four TFTs connected to the first first gate line GL1 are driven. Four TFTs connected to the first second gate line GL7 are driven.

Thereafter, the output signals of the first stages SRC1 and SRC8 are provided as control signals of the next stages SRC2 and SRC9 so that the second first and second gate lines GL2, corresponding to the next stages SRC2 and SRC9, are provided. The switching transistor connected to GL8 is driven. In this manner, six first and second gate lines GL1 to GL6 and GL7 to GL12 are driven in one frame.

FIG. 5 is a circuit diagram illustrating an RC delay circuit of the gate line of FIG. 3. 5 illustrates an example in which two pixels are connected to the first and second gate lines, respectively. Here, "R" is the resistance when the TFT of each pixel is turned on, and "C" is the capacitance between the transparent pixel electrode and the transparent common electrode.

Referring to FIG. 5, in the first RC delay circuit 150, a first resistor R1 is connected in series between a first gate driving power supply voltage V1 and a first node N1, and the first node NI is connected to the first node NI. ) And the first capacitance C1 is connected in parallel between the ground and the ground. A second resistor R2 is connected in series between the first node NI and the second node N2, and a second capacitance C2 is connected in parallel between the second node N2 and the ground.

Also, in the second RC delay circuit 160, a third resistor R3 is connected in series between the second gate driving power supply voltage V2 and the third node N3, and between the third node N3 and the ground. The third capacitance C3 is connected in parallel. A fourth resistor R4 is connected in series between the third node N3 and the fourth node N4, and a fourth capacitance C4 is connected in parallel between the fourth node N4 and the ground. In this case, the first and second gate driving power supply voltages V1 and V2 are turn-on voltages of the TFT.

In the first RC delay circuit 150 according to the first gate driving power supply voltage V1, 'τ = (R1 + R2) x (C1 + C2), that is, τ = 4RC'. Further, 'τ = (R3 + R4) × (C3 + C4), i.e., τ = 4RC' in the second RC delay circuit 160 caused by the second gate driving power supply voltage V2.

In this case, since the first RC delay circuit 150 is not connected to the second RC delay circuit 160, the first and second gate driving power supply voltages V1 and V2 may be applied even when the first RC delay circuit 150 is different from the first RC delay circuit 150. And no current movement between the second gate driving power supply voltages V1 and V2 occurs.

6 is a schematic diagram showing a configuration of a TFT substrate according to another embodiment of the present invention. However, in describing FIG. 6, components that perform the same functions as those described in FIG. 3 are given the same reference numerals, and descriptions of the functions are omitted.

Referring to FIG. 6, the plurality of gate lines GL1 to GL2n may extend to one side of the display area 111, and the first gate lines GL1 to GLn and the first gate lines GL1 to GLn. ) And second gate lines GLn + 1 to GL2n formed on the same line as the first gate lines GL1 to GLn and extending to the other side of the display area 111. It consists of.

The plurality of data lines DL1 to DLn of the TFT substrate 112a are connected to the data driving circuit 113 formed at one side of the TFT substrate 112a. In addition, one end of the first gate lines GL1 to GLn is connected to the first gate driving circuit 114, and one end of the second gate lines GLn + 1 to GL2n is connected to the second gate driving circuit ( 115).

As shown in FIG. 6, the cut portions of the plurality of first and second gate lines GL1 to GLn and GLn + 1 to GL2n are alternately formed. That is, more unit pixels are connected to the first first gate line GL1 than the second gate line GLn, and the second gate line GLn + 1 is connected to the first gate line GL2. Fewer unit pixels are connected, and so on.

Although not shown in the drawings, the cut portions of the first and second gate lines are formed at different positions. That is, the number of unit pixels connected to each of the first and second gate lines is different from each other.

As described above, the liquid crystal display according to the present invention includes a plurality of first gate lines and a plurality of first gate lines for supplying scan pulses to some pixels of each pixel row in a display area in which a plurality of pixels are formed in a matrix form on a substrate. And a plurality of second gate lines for supplying scan pulses to the remaining pixels of the pixel row. The first and second gate lines are respectively driven by first and second gate driving circuits disposed around second and third peripheral portions of the display area.

Therefore, even when a gate line driving delay between the first and second gate driving circuits occurs, current movement between the first and second gate driving circuits can be prevented.

Although described with reference to the examples, those skilled in the art can understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention described in the claims below. There will be.

Claims (5)

A display area in which a plurality of pixels are formed in a matrix on a substrate; A plurality of data lines for supplying pixel data to each pixel column of the display area; A data driving circuit disposed around the first area of the display area to drive the plurality of data lines; A plurality of first gate lines for supplying scan pulses to some pixels of each pixel row of the display area; A first gate driving circuit disposed around a second periphery of the display area to drive the plurality of first gate lines; A plurality of second gate lines for supplying the scan pulse to the remaining pixels of each pixel row of the display area; And a second gate driving circuit disposed in a third periphery of the display area to drive the plurality of second gate lines. 2. The liquid crystal display device according to claim 1, wherein the number of pixels each shared by the first gate lines in the pixel rows is the same. 3. The liquid crystal display device according to claim 2, wherein the number of pixels shared by the first and second gate lines in each pixel row is the same. 2. The pixel of claim 1, wherein the number of pixels shared by the first gate line is greater than the number of pixels shared by the second gate line in each odd pixel row, and the pixels shared by the first gate line in each even pixel row. Wherein the number is shared less than the number of pixels shared by the second gate line. The liquid crystal display of claim 1, wherein the number of pixels shared by the first gate line and the number of pixels shared by the second gate line are different from each other in the pixel rows.