KR20030016553A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE: A phase locked loop(PLL) circuit is provided, which reduces a locked time and noise, by reducing a loop band width. CONSTITUTION: According to the PLL circuit, a phase detector(PD)(120) receives an external clock and the first and the second internal clock, and compares the first internal clock with the second internal clock and the external clock with the first internal clock periodically, and generates four up/down signals according to a phase difference of two signals. A phase frequency detector(PFD)(110) receives the external clock and the first internal clock and generates four up/down signals according to a phase difference of the two signals. A multiplexer part(MUX)(130) outputs one of a signal received from the phase detector and a signal received from the phase frequency detector selectively by the first control signal. A charge pump part(140) generates a constant signal according to an output signal from the phase detector or the phase frequency detector received through the multiplexer part, and controls a current source supplied to a circuit by the first control circuit. A locked state part(150) generates the first control signal to the multiplexer part and the charge pump part by counting the external clock. And a voltage controlled oscillator(VCO)(180) receives a signal generated from the charge pump part and generates a signal having a frequency and a phase proportional or inversely proportional to the signal received from the charge pump part.

Description

Face lock loop circuit {PHASE LOCKED LOOP CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a phase locked loop (also referred to as a 'PLL') circuit of a semiconductor memory device, and more particularly to a face lock loop circuit having a reduced locked time and a reduced noise.

In general, a PLL circuit is a device that receives a clock signal input from the outside of the system and generates an internal clock signal required inside the system to be synchronized with the phase of the clock signal input from the outside. In this case, the system includes all of a logic device or a semiconductor device using an external clock signal. For example, PLL circuits can be used in various types of logic devices, as well as in cache memory devices that speed up data processing between the central processing unit and DRAM (DRAM) of a computer, or can be applied to synchro DRAM, Rambus DRAM, and the like.

1 is a block diagram of a conventional PLL circuit.

The conventional PLL circuit is composed of a phase detector 12, a charge pump 14, a loop filter 16, and a voltage regulation generator 18, and operates as a negative feedback loop. The PLL circuit needs to match the output frequency of the voltage regulation generator 19 with the feedback input frequency of the phase detector 12.

The phase detector 18 of the PLL circuit periodically compares the phases of the external clock eCLK coming from the outside and the internal clock iCLK, which is the output of the internal voltage regulation generator 18, to increase the phase according to the phase difference between the two signals. The up and down signals are sent to the charge pump unit 14. The charge pump unit 14 generates a constant output voltage Vd according to the up and down signals and sends it to the loop filter unit 16. The loop filter unit 16 uses a low pass filter to filter the output voltage of the charge pump unit 14 to remove high frequency components and to adjust the DC regulation voltage Vc for adjusting the voltage regulation generator 18. ) Finally, the voltage regulation generator 18 is an oscillator that outputs a frequency proportional to Vc by inputting the output voltage Vc of the loop filter unit 16.

In such a PLL, when a negative feedback operation of a loop is repeated several times, the clock is synchronized when the output of the voltage regulation generator 18 becomes the same as the external clock eCLK input from the outside. At this time, since the external clock eCLK and the internal clock iCLK have a constant phase difference and the frequencies are the same, the phase detector 12 generates a constant continuous pulse. However, even if the frequencies match, if the phase difference between the two input signals is large, the number of pulses of the up and down signals generated by the phase detector 12 do not coincide with each other. As the voltage continues to change, the loop is unlocked again to continue the locking process. In order for the PLL to be fully locked, the two signals must have the same frequency, and the phase difference must be small.

However, the conventional PLL circuit configured as described above can obtain a fast lock time when the loop band width is increased for fast operation, but in this case, the phase jitter of the output signal becomes large. Or there is a lot of noise. In other words, if the loop bandwidth is large, fast operation is performed, but there is a lot of noise. On the contrary, if the loop bandwidth is reduced to reduce the noise, the time for reaching the steady state, that is, the lock time is long.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to increase the loop bandwidth in the initial operation and to reduce the loop bandwidth when the phase difference between the input signal and the reference signal decreases after a predetermined time. In addition, the present invention provides a face lock loop (PLL) circuit that reduces lock time and reduces noise.

1 is a block diagram of a conventional PLL circuit

2 is a block diagram of a face lock loop circuit according to the present invention.

3A and 3B are circuit and operation waveform diagrams of the phase detector 120 shown in FIG. 2.

4A and 4B are circuit and operation waveform diagrams of the phase frequency detector 110 shown in FIG.

5A is a circuit diagram of the voltage regulation generator 180 shown in FIG. 2.

5B is a circuit diagram of the differential delay cells 182 to 188 shown in FIG. 5A.

6 is a circuit diagram of the charge pump unit 140 shown in FIG.

Explanation of symbols on the main parts of the drawings

120: phase detector 130: multiplexer

140: charge pump portion 150: lock state portion

160: loop filter unit 180: voltage regulation generating unit

In order to achieve the above object, the PLL circuit of the present invention receives an external clock and a first internal clock and a second internal clock to periodically perform the first internal clock, the second internal clock, and the external clock and the first internal clock, respectively. The phase detection unit generates four up / down signals according to the phase difference between the two signals, and the phase which receives the external clock and the first internal clock and generates four up / down signals according to the phase difference between the two signals. A multiplexer section for selecting and outputting a frequency detector, a signal received from the phase detector, or a signal received from the phase frequency detector by a first control signal, and the phase detector or phase frequency detector received through the multiplexer section A constant signal is generated according to the output signal from the second control signal and supplied to the circuit by the first control signal. A charge pump unit for adjusting a current source, a lock state unit for generating the first control signal to the multiplexer unit and the charge pump unit when the preset value is reached by countering the external clock, and generated from the charge pump unit And a voltage regulation generator for receiving a signal and generating a signal having a frequency and a phase proportional or inversely proportional to the signal.

A low pass filter unit is additionally provided between the charge pump unit and the voltage regulation generating unit.

The low pass filter unit includes first and second capacitors connected in parallel between a ground voltage and a node connected between the charge pump unit and the voltage regulation generating unit, and a resistor connected to one side of the first capacitor. It features.

The low pass filter part may further include a switching element switched by the first control signal between the charge pump part and the voltage regulation generating part.

The switching element is characterized in that the transfer gate.

The switching device is characterized in that the PMOS transistor.

The switching device is characterized in that the NMOS transistor.

The bandwidth of the signal is changed by adjusting the voltage gain of the voltage regulation generator.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In addition, in all the drawings for demonstrating an embodiment, the thing with the same function uses the same code | symbol, and the repeated description is abbreviate | omitted.

2 is a block diagram of a PLL circuit according to the present invention, in which a phase detector 120, a phase frequency detector 110, a multiplexer 130, a charge pump 140, a loop filter 160, and voltage regulation are generated. The unit 180 and the lock state unit 150 are provided.

The PLL circuit having the above configuration operates as a negative feedback loop, so that the output frequency of the voltage regulation generation unit 180 and the feedback input frequency of the phase detection unit 120 are coincident with each other.

The phase detector (PD) 120 periodically compares the phases of the external clock IN received from the outside with the phases of the internal clocks clk1 and clk3 that are outputs of the voltage regulation generation unit 180. Four up and down signals are generated according to the phase difference of?.

The phase frequency detector (PFD) 110 periodically compares the phases of the external clock IN coming from the outside and the internal clock clk1, which is an output of the voltage regulation generator 180, to compare two signals. Four up and down signals are generated according to the phase difference of?.

The multiplexer unit (MUX) 130 selects the signal received from the phase detector 120 and the signal received from the phase frequency detector 110 based on a signal output from the lock state unit 150 to charge the charge. Output to the pump unit 140.

The charge pump unit 140 generates a constant output signal according to an output signal from the phase detector 120 or the phase frequency detector 110 received through the multiplexer 130, and the lock state unit. By controlling the current source by the output signal of 150 to adjust the size of the loop bandwidth.

The lock state unit 150 counters the external clock IN received from the outside and generates a lock signal to the multiplexer unit 130 and the charge pump unit 140 when a preset value is reached. .

The loop filter unit 160 connected between the charge pump unit 140 and the voltage regulation generating unit 180 filters the output voltage of the charge pump unit 140 by using a low pass filter. The high frequency component is removed and a direct current (DC) control voltage Vc for controlling the voltage regulation generator 180 is output.

The voltage controlled oscillator (VCO) 180 generates a clock signal clk1 and clk3 in proportion to the DC regulated voltage Vc received from the loop filter unit 160.

3A and 3B are circuit and operation waveform diagrams of the phase detector 120 illustrated in FIG. 2.

The phase detection unit 120 receives the clock signals clk1 and clk3 from the voltage regulation generator 180 to generate a down signal DOWN, and the down signal EXNOR and the down signal. Inverter INV1 for receiving (DOWN) and outputting the inverted down bar signal / DOWN, and receiving the clock signal clk1 and the external clock IN from the voltage regulation generator 180. An exclusive OR gate EXOR for generating an up signal UP and an inverter INV2 for receiving the up signal UP and outputting an inverted up bar signal / UP.

When the outputs of the EXNOR gate EXNOR and EXOR gate EXOR of FIG. Becomes At this time, the average voltage of the output pulses of the phase detector 120 is half voltage (Vcc / 2).

4A and 4B are circuit and operation waveform diagrams of the phase frequency detector 110 shown in FIG. 2.

The phase frequency detector 110 converts a power supply voltage Vcc into an input signal D, a clock signal clk1 from the voltage regulation generator 180 into a clock input signal clk, and ups UP. A first synchronous RS flip-flop 112 which receives a signal combining the signal and the DOWN signal as a reset (R) signal and outputs the up signal, and the power supply voltage Vcc. As the input signal D, the external clock IN is used as a clock input signal clk, and a signal obtained by combining a UP signal and a DOWN signal as a reset R signal is received. A second synchronous RS flip flop 114 for outputting a DOWN signal and a combined signal by receiving the UP signal and a DOWN signal and combining the first and second synchronous RS flip flops 112 ( AND gate (AND) output as the reset (R) signal of 114, the inverter (INV3) for receiving the up (UP) signal and outputs the inverted up bar signal / UP, and the down (DOWN) A) can signal And it consists of an inverter (INV4) for outputting the turn-down bar signal (/ DOWN).

Since the phase frequency detector 110 uses an edge trigger method, the phase frequency detector 110 operates regardless of the duty ratio of the signal, and the output of the charge pump is 'high' according to the combination of the UP and DOWN signals. It has three states, 'high impedance' and 'low'. Therefore, the PLL circuit transitions between these three states and goes through a locking process, and when the PLL is locked, it is in a 'high impedance' state, and the phase difference of the two signals becomes zero.

FIG. 5A is a circuit diagram of the voltage regulation generator 180 shown in FIG. 2, and is configured of four stages of differential delay cells 182 to 188.

As shown, the delay cell stage is evenly implemented by connecting the feedback output of the last stage to the first stage in reverse. Since the entire stage of the voltage regulation generator 180 is configured as an even number, the output of the voltage regulation generator 180 obtained in the middle stage is 90 degrees different from the phase of the output of the last stage, so that the multiphase output can be easily performed. You can get it.

FIG. 5B is a circuit diagram of the differential delay cells 182 to 188 shown in FIG. 5A, and a PMOS transistor P1 connected in a diode structure between a power supply voltage Vcc and a node Nd1, and the power supply voltage Vcc. A PMOS transistor P4 connected in a diode structure between the nodes Nd2, a PMOS transistor P2 for transmitting a power supply voltage Vcc to the node Nd1 by a control signal CTL, and the control signal CTL The signal of the node Nd1 is transferred to the node Nd2 by the PMOS transistor P3 for transmitting the power supply voltage Vcc to the node Nd2 and the signal IN received from the charge pump unit 140. Transmitting the signal of the node Nd2 to the node Nd3 by the NMOS transistor N1 transmitted to the Nd3 and the inversion signal / IN of the signal IN received from the charge pump unit 140. NMOS transistor N2 and an NMOS transistor for discharging the signal of node Nd3 to ground voltage Vss by bias signal bias It is configured as an emitter (N3).

FIG. 6 is a circuit diagram of the charge pump 140 shown in FIG. 2, and receives the output signals of the phase detector 120 or the phase frequency detector 110 received through the multiplexer 130, and then receives these signals. A differential amplification unit 142 for generating a differentially amplified signal according to the present invention, and supplying a power supply voltage Vcc to the differential amplifying stage 142 by a first control signal, wherein the differential signal is activated when the first control signal is active. The pull-up bias unit 144 adjusts the amount of the power supply voltage Vcc supplied to the amplifier stage 142 by the second control signal, and the ground voltage Vss is supplied to the differential amplifier stage 142 by the third control signal. A pull-down bias unit 146 for supplying a current flowing from the differential amplifier terminal 142 to the ground voltage terminal Vss by the second control signal when the third control signal is activated and the power supply; Voltage terminal (Vcc) and ground It is constituted by a resistance connected in parallel to the voltage terminal (Vss) to bias control unit 148 for generating the first and the third control signal.

The differential amplifier 142 is connected in series between a node Nd11 and a node Nd12 and is operated by a PMOS transistor and an DOWN signal respectively received from the multiplexer 130. A PMOS transistor P12 connected between a P11 and an NMOS transistor N11 and the node Nd11 and an output terminal out and switched by an up bar signal / UP received from the multiplexer 130. ) And an NMOS transistor N12 connected between the output terminal out and the node Nd12 and switched by a down bar signal / DOWN received from the multiplexer 130.

The pull-up bias unit 144 is connected in series between the power supply voltage terminal Vcc and the node Nd11 of the differential amplifier 142 and is respectively connected by the first control signal and the second control signal lock. A PMOS transistor P14 and a transfer gate G1 to be switched, and a PMOS transistor P5 connected between the power supply voltage terminal Vcc and the node Nd11 and switched by the first control signal.

The pull-down bias unit 146 is connected in series between the node Nd12 of the differential amplifier 142 and the ground voltage terminal Vss and is switched by the second control signal lock and the third control signal, respectively. The transfer gate G2 and the NMOS transistor N15, and the NMOS transistor N16 connected between the node Nd12 and the ground voltage terminal Vss and switched by the third control signal.

The bias control unit 148 includes a resistor R1 connected between the power supply voltage terminal Vcc and the node Nd15 for transmitting the third control signal, the power supply voltage terminal Vcc, and the first control signal. Discharges the signals of the node Nd15 and the node Nd16 to the ground voltage Vss by the signal of the node Nd15 and the PMOS transistor P13 connected in a diode structure between the node Nd16 transmitting the NMOS transistors N13 and N14 having a current mirror structure.

The PLL circuit having the above configuration increases the loop bandwidth in an initial operation and decreases the phase difference between the input signal IN and the reference signal, that is, the clock signal clk1 from the voltage regulation generator 180 after a predetermined time. The smaller loop bandwidth reduces the lock time and reduces the noise.

The loop bandwidth can be expressed as follows.

Bandwidth (Bandwidth: BW) _P = I · R · K _VCO

Where K _VCO and R are constants and I _P is a variable.

Initial PLL operation requires fast lock, so increase I _P to increase K.

Then, the lock state unit 150 counters an input pulse and sends a lock signal to change the size of the current source I of the charge pump unit 140 when the preset value is reached. That is, by turning off the transfer gate G1 of the pull-up bias unit 144 of the charge pump unit 140 by the lock signal generated by the lock state unit 150 through the PMOS transistor P14. It blocks the flow of current. Therefore, the lock state that the power supply voltage Vcc is supplied to the pull-up node of the differential amplifier 140 through the PMOS transistors P14 and P15 of the pull-up bias unit 144 connected in parallel at the beginning of the operation of the PLL circuit. The amount of current flowing to the pull-up node of the differential amplifier 142 may be adjusted by blocking one of two paths by the lock signal generated by the block 150.

Similarly, by turning off the transfer gate G2 of the pull-down bias unit 146 of the charge pump unit 140 by the lock signal generated by the lock state unit 150 through the NMOS transistor N15. It blocks the flow of current. Accordingly, the lock state of supplying the ground voltage Vss to the pull-down node of the differential amplifier 142 through the NMOS transistors N15 and N16 of the pull-down bias unit 146 connected in parallel at the beginning of the operation of the PLL circuit. The amount of current flowing to the pull-down node of the differential amplifier 142 may be adjusted by blocking one of two paths by the lock signal generated by the block 150.

As such, the loop bandwidth can be reduced by half (1/2) by adjusting the amount of current flowing through the pull-up and pull-down nodes of the differential amplifier 142.

Meanwhile, the multiplexer unit 130 transmits the output signal from the phase frequency detector 110 to the charge pump unit 140 by a lock signal generated by the lock state unit 150. The output signal from the phase detector 120 is transferred to the charge pump 140.

In this case, since the phase detector 120 is configured as an EXOR gate as shown in FIG. 3A, the output is restored to the original input signal and output even in the case of code missing of the input signal IN. That is, the clock recovery function. This can also be useful when the horizontal sync signal of an OSD or TV signal is missing.

In addition, the PLL circuit of the present invention controls the band width by controlling K _VCO or controlling R at the gain of the voltage regulation generator 180, that is, the bandwidth BW = I _P · K _VCO · R without controlling the current source. You can change it.

As described above, according to the PLL circuit according to the present invention, the loop bandwidth is increased during initial operation and the loop bandwidth is reduced when the phase difference between the input signal and the reference signal decreases after a predetermined time, thereby reducing the lock time ( locked time) and reduce noise.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.

Claims (20)

In a face lock loop (PLL) circuit of a semiconductor memory device, Receiving an external clock and first and second internal clocks and periodically comparing the first internal clock and the second internal clock and the external clock and the first internal clock, respectively, according to the phase difference of the two signals, A phase detector for generating a down signal, A phase frequency detector for receiving the external clock and the first internal clock and generating four up / down signals according to a phase difference between the two signals; A multiplexer unit which selects and outputs a signal received from the phase detector or a signal received from the phase frequency detector by a first control signal; A charge pump unit which generates a constant signal according to the output signal from the phase detector or the phase frequency detector received through the multiplexer, and regulates a current source supplied to the circuit by the first control signal; A lock state unit for generating the first control signal to the multiplexer unit and the charge pump unit when the external clock is countered and a preset value is reached; And a voltage regulation generator which receives a signal generated from the charge pump unit and generates a signal having a frequency and a phase proportional to or inversely proportional to the signal. The method of claim 1, A low pass filter unit is further provided between the charge pump unit and the voltage regulation generating unit. The method of claim 2, wherein the low pass filter, And a first and second capacitors connected in parallel between a node connected between the charge pump unit and the voltage regulation generating unit and a ground voltage, and a resistor connected to one side of the first capacitor. Loop (PLL) circuit. The method of claim 3, wherein the low pass filter, And a switching element that is switched by the first control signal between the charge pump section and the voltage regulation generation section. The method of claim 4, wherein And the switching element is a transfer gate. The method of claim 4, wherein And the switching element is a PMOS transistor. The method of claim 4, wherein The switching element is a phase lock loop (PLL) circuit, characterized in that the NMOS transistor. The method of claim 1, wherein the phase detection unit, An exclusive NOR gate receiving the first and second internal clocks and generating a down signal DOWN; A first inverter receiving the down signal DOWN and outputting an inverted down bar signal / DOWN; An exclusive OR gate configured to receive the first internal clock and the external clock and generate an up signal UP; And a second inverter configured to receive the up signal (UP) and output an inverted up bar signal (/ UP). The method of claim 1, wherein the phase frequency detector, Generating a UP signal by receiving a power supply voltage as an input signal, receiving the first internal clock as a clock input signal, and a signal combining a UP signal and a DOWN signal as a reset signal; 1 synchronous flip flop, Generating a DOWN signal by receiving the power voltage as an input signal, the external clock as a clock input signal, and receiving a combination signal of the UP signal and the DOWN signal as a reset signal; A second synchronous flip flop, An AND gate receiving the UP signal and the DOWN signal and generating a combined signal as a reset signal of the first and second synchronous flip-flops; A first inverter receiving the up signal and outputting an inverted up bar signal / UP; And a second inverter configured to receive the down signal and output an inverted down bar signal (/ DOWN). The method of claim 1, And the voltage regulation generator comprises four stages of differential delay cells. The method of claim 10, And the differential delay cell comprises a differential amplifier for receiving a signal received from the charge pump unit and an inverted signal of the signal and outputting a differentially amplified signal. The method of claim 1, wherein the charge pump unit, A differential amplifier which receives an output signal of the phase detector or the phase frequency detector received through the multiplexer and generates differentially amplified signals according to these signals; A pull-up bias unit which supplies a power supply voltage to the differential amplifier by a second control signal and adjusts the amount of the power supply voltage supplied to the differential amplifier by the first control signal when the second control signal is activated; A pull-down bias supplying a ground voltage to the differential amplifier by a third control signal and adjusting the amount of current flowing from the differential amplifier to the ground voltage terminal by the first control signal when the third control signal is active; Wealth, And a bias controller configured to generate the second and third control signals by a resistor connected in parallel between the power supply voltage terminal and the ground voltage terminal. The method of claim 12, wherein the differential amplifier, A first PMOS transistor and a first NMOS transistor connected in series between a pull-up node and a pull-down node and operated by an UP signal and a DOWN signal received from the multiplexer, A second PMOS transistor connected between the node and an output terminal and switched by an up bar signal received from the multiplexer unit; And a second NMOS transistor coupled between the output terminal and the pull-down node and switched by a down bar signal (/ DOWN) received from the multiplexer section. The method of claim 13, wherein the pull-up bias unit, A third PMOS transistor and a first switching element connected in series between the power supply voltage terminal and the pull-up node and switched by the second control signal and the first control signal, respectively; And a fourth PMOS transistor connected between the power supply voltage terminal and the pull-up node and switched by the second control signal. The method of claim 14, And said first switching element comprises a transfer gate. The method of claim 14, wherein the pull-down bias unit, A second switching element and a third NMOS transistor connected in series between the pull-down node and a ground voltage terminal and respectively switched by the first control signal and a third control signal; And a fourth NMOS transistor connected between the pull-down node and a ground voltage terminal and switched by the third control signal. The method of claim 16, And said second switching element comprises a transfer gate. The method of claim 16, wherein the bias control unit, A first resistor connected between the power supply voltage terminal and a first node for transmitting the third control signal; A second resistor connected between the power supply voltage terminal and a second node for transmitting the second control signal; And a fifth and sixth NMOS transistors having current mirror structures that discharge the signals of the first node and the second node to ground voltages by the signal of the first node. The method of claim 18, And the second resistor is a PMOS transistor having a diode structure. The method of claim 1, And controlling the voltage gain of the voltage regulation generator to change the bandwidth of the signal.