KR20030002813A - High voltage generation circuit of semiconductor memory device - Google Patents

Abstract

PURPOSE: A high voltage generation circuit of a semiconductor memory device is provided to reduce current consumption during a refresh operation by driving each of n number of Vpp pumping circuits and to implement a stable operation by separably driving the Vpp pumping circuits. CONSTITUTION: A high voltage generation circuit of a semiconductor memory device includes a high voltage control block for outputting a pump enable signal(b) and an enable signal of an oscillation block by comparing a high voltage and a reference voltage level, the oscillation block for oscillating n number of constant pulses by inputting the enable signal of the oscillation block, a delay circuit block for outputting Vpp pump driving signal by inputting the pump enable signal(b) and a refresh enable signal(c) and n umber of Vpp pump circuit blocks for generating a high voltage level by inputting the constant pulse signal of the oscillation block and the Vpp pump driving signal.

Description

HIGH VOLTAGE GENERATION CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE}

The present invention relates to a high voltage generation circuit of a semiconductor memory device. More particularly, the operation speed is enhanced by reinforcing high voltage (Vpp) consumed when a word line of a bank is activated by an internal RAS signal of an activated bank. The present invention relates to a high voltage generation circuit of a semiconductor memory device that can reduce noise and current consumption of cell data.

In general, in order to write or read data in a cell, a signal applied to a gate of a cell transistor, that is, a voltage level of a word line, that is, a cell transistor, due to an NMOS characteristic, which is higher than the 'high' data level written to the cell + a threshold voltage of the cell transistor. Should be For this reason, a high voltage Vpp is internally generated and used, and is used in word lines and related parts thereof.

1 is a block diagram of a high voltage generation circuit of a conventional semiconductor memory device.

As shown, the high voltage generation circuit includes the Vpp control section 1, an oscillator section 2 for inputting the output signal of the Vpp control section 1, an output signal of the oscillator section 2, and a Vpp control section ( It consists of n Vpp pump circuit parts 3 which take the output signal of 1) as an input.

The operation of this is as follows.

The Vpp control unit 1 inputs a Vpp_ref signal generated at a reference voltage (not shown) and a feedback signal of a Vpp voltage level, which is an output signal from the pump circuit unit 3, at a predetermined level. At this time, when the fed back Vpp voltage level is lower than the Vpp_ref signal, a b signal, which is a pump enable signal of the Vpp control unit 1, and an enable signal a of the oscillator unit 2 are generated. The oscillator unit 2 mainly uses a ring oscillator. When the a signal is input, the oscillator unit 2 generates n osc0 to oscn signals, which are pulse signals of a predetermined period.

The Vpp pump circuit unit 3 that receives the output signal of the oscillator unit 2 and the b signal that is the pump enable signal as an input outputs a Vpp voltage level by pumping through a capacitor. At this time, when reaching a predetermined level or more of the Vpp voltage level, the Vpp control unit 1 detects this and controls the oscillation and pumping by disabling the a signal.

However, since a high voltage line that transfers the Vpp voltage level is disposed throughout the chip, and the main point of use is a word line enable time, the Vpp control unit 1 and the oscillator unit ( 2) and the Vpp pump circuit section 3, etc. must all operate. As a result, the compensation of the Vpp voltage level has to be delayed and power consumption is large.

In particular, the reduction of current consumption and peak current for the operation of the high voltage generating circuit in the self-refresh mode are the main characteristics of low voltage products.

Accordingly, an object of the present invention is to generate a high voltage of a semiconductor memory device capable of reducing current consumption and power noise of a Vpp pump circuit part by delaying each pump enable signal input to the Vpp pump circuit part in a self refresh mode. To provide a circuit.

1 is a block diagram of a high voltage generation circuit of a conventional semiconductor memory device.

2 is a block diagram of a high voltage generation circuit of the semiconductor memory device of the present invention.

3 is a circuit diagram of a delay circuit of FIG. 2.

4 is an operation timing diagram of FIG. 3.

Explanation of symbols on the main parts of the drawings

10: Vpp control part 20: oscillator part

30: delay circuit 31: delay unit

32: first inverter 33: first NAND gate

34: second NAND gate 35: second inverter

40: Vpp pump circuit part

The high voltage generation circuit of the semiconductor memory device of the present invention for achieving the above object is a high voltage control unit for outputting the pump enable signal and the oscillator unit enable signal by comparing the high voltage and the reference voltage level, and the enable signal of the oscillator unit An oscillator section for generating n constant pulses as an input, a delay circuit section for outputting a Vpp pump driving signal with the pump enable signal and a refresh enable signal as inputs, and a constant pulse signal and the Vpp pump driving section of the oscillator section And n Vpp pump circuit parts generating a high voltage (Vpp) level as a signal.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

2 is a block diagram of a high voltage generation circuit of the semiconductor memory device of the present invention, FIG. 3 is a circuit diagram of the delay circuit shown in FIG. 2, and FIG. 4 is an operation timing diagram of FIG.

As shown in FIG. 2, the high voltage generation circuit 10 compares the high voltage Vpp and the reference voltage level Vpp_ref to output a pump enable signal b and an oscillator enable signal a. ), An oscillator unit 20 for oscillating n constant pulses <osc0: oscn> by inputting the enable signal a of the oscillator unit, a pump enable signal b, and a self-refresh enable signal c. By inputting the constant pulse signal of the delay circuit unit 30 and the oscillator unit 20 for outputting the Vpp pump driving signal <en 0: en n> and the pump driving signal <en 0: en n>, respectively, N number of Vpp pump circuits 40 for generating a high voltage (Vpp) level.

In this case, as shown in FIG. 3, the delay circuit unit 30 includes a delay unit 31 for delaying the pump enable signal b for a predetermined time and a first inverter for inverting the output signal of the delay unit 31. And a first NAND gate 33 for inputting the first inverter 32 and the refresh enable signal c.

In addition, a second inverter for inverting the output signal of the second NAND gate 34 and the second NAND gate 34 which inputs the output signal of the pump enable signal b and the first NAND gate 33. It comprises 35.

An operation of the high voltage generation circuit of the semiconductor memory device of the present invention having such a configuration will be described with reference to FIG. 4.

The Vpp control unit 10 receives a Vpp_ref signal generated by a reference voltage (not shown) and a feedback signal of a Vpp voltage level, which is an output signal from the pump circuit unit 40, at a predetermined level. At this time, when the feedback Vpp voltage level is lower than the Vpp_ref signal, the pump enable signal b of the Vpp control unit 10 and the enable signal a of the oscillator unit 20 are generated.

Here, when the semiconductor memory device is in a normal operation, the refresh enable signal c is disabled so that a 'low' level is input to the delay circuit unit 30. Then, the node n1 level is always maintained at a 'high' level such that the pump driving signal <en 0: en n>, which is the output signal of the delay circuit unit 30, becomes the same signal as the pump enable signal b. .

In addition, when the oscillator 20 enable signal a is input to the oscillator 20, n output signals <osc0: oscn>, which are pulse signals of a predetermined period, are output.

The n output signals <osc0: oscn> and the output signals <en 0: en n> of the delay circuit unit 30, which are the same signals as the pump enable signal b, are input to the Vpp pump circuit unit 40 to provide a high voltage ( Vpp).

On the other hand, when the semiconductor memory device is in the refresh mode, the refresh enable signal c becomes 'high' level, so the node n1 level is delayed by t0 to tn step by the delay unit 31 to enable Vpp. Generate the pump drive signal <en 0: en n>.

That is, each of the delay units 31 provided in the n delay circuit units 30 delays the pump enable signal b by t0 to tn, respectively, and the Vpp pump driving signal en i (0 to n) is gradually increased. Causes)).

Therefore, in the refresh mode, the Vpp pump driving signal is delayed to generate a delayed signal to drive the Vpp pump circuit part 40, respectively, thereby reducing the current consumption of the Vpp pump circuit part 40 during the refresh operation. By dividing 40, power noise can be reduced to perform stable operation.

According to the high voltage generation circuit of the semiconductor memory device of the present invention described above, in the normal operation, a plurality of Vpp pump circuit parts 40 are simultaneously driven in the same manner as the conventional method, and in the refresh operation, the Vpp pump driving signal is applied. By delaying each of the n Vpp pump circuit units 40, the current consumption can be reduced during the refresh operation, and the Vpp pump circuit unit 40 can be divided and operated to reduce power noise to perform stable operation. .

Claims (3)

In a high voltage generation circuit of a semiconductor memory device, A high voltage control unit for comparing the high voltage and the reference voltage level to output a pump enable signal and an oscillator enable signal; An oscillator unit configured to generate n constant pulses by inputting an enable signal of the oscillator unit; A delay circuit unit configured to output a Vpp pump driving signal by inputting the pump enable signal and the refresh enable signal; And n Vpp pump circuit parts generating a high voltage (Vpp) level by inputting a constant pulse signal and the Vpp pump driving signal as input signals of the oscillator part. The method of claim 1, The n delay circuits output the same signal as the pump enable signal during a normal operation of the semiconductor memory device. And delaying the pump enable signals and outputting the pump enable signals to the n Vpp pump circuits, respectively, in the refresh operation. The method of claim 2, The delay circuit unit, A delay unit configured to delay the pump enable signal for a predetermined time; A first inverter for inverting the output signal of the delay unit; A first NAND gate configured to receive the first inverter and the refresh enable signal; A second NAND gate inputting the pump enable signal and an output signal of the first NAND gate; And a second inverter for inverting the output signal of the second NAND gate.