KR20030002639A - A system for processing serial data - Google Patents

Abstract

PURPOSE: A system for processing serial data is provided to reduce an electric power consumption and apply to all audio devices. CONSTITUTION: In a system for processing serial data, a processor comprises a plurality of processing blocks. An electric power management unit(101) controls an electric power of the processor. The processing block of the processor has a hardware structure specified in a data processing, and the electric power management unit(101) operates only one processing block related to the current data processing out of the processing blocks. The processing blocks includes a bit stream processing block(115) which analyzes a compressed bit stream being inputted to a data processing system and converts the bit stream into a data format for the next process, and a digital signal processing block(117) which performs a general digital signal process with respect to output data of the bit stream processing block(115). In addition, a direct memory controller(DMA) of a low-power structure which performs an interface between a memory of the data processing system and the processing blocks is provided.

Description

System for serial data processing {A SYSTEM FOR PROCESSING SERIAL DATA}

The present invention relates to a system for serial data processing, and more particularly, to a system for reducing power consumption by processing audio data using a plurality of separately controllable processing blocks.

A general signal processing system has a structure in which an application program is ported to a general digital signal processor. The structure of the current audio processing apparatus is the same.

However, in such a structure, since all the flows of the program, that is, even hardware that is not required to be driven in the data processing process, must be driven, power consumption is large. In complex programs, especially high performance (high frequency) requires more power consumption. In addition, there is a problem that a hardware interface must be provided separately according to the audio device.

Accordingly, an object of the present invention is to provide a data processing system with reduced power consumption.

It is another object of the present invention to provide an audio data processing system applicable to all audio devices.

1 is a block diagram of a low power audio processing apparatus according to an embodiment of the present invention.

Fig. 2 is a diagram showing a power control mode in the present invention.

3 is a block diagram of a clock control unit in the present invention.

4 is a diagram showing the structure of a memory system in the present invention;

5 is a block diagram of a device interface in the present invention.

In order to achieve the object as described above, the present invention provides a system for serial data processing, comprising a processor consisting of a plurality of processing blocks, and a power control unit for controlling the power of the processor, the processing block of the processor It has a hardware structure specific to the processing process, the power control unit is characterized in that to drive only the processing block associated with the current data processing process of the plurality of processing blocks.

The processor typically analyzes a compressed bit stream input to the data processing system through the plurality of processing blocks, and converts the bit stream processing block into a data format for subsequent processing, and output data of the bit stream processing unit. And a digital signal processing block for performing digital signal processing.

It is preferable that a direct memory controller (DMA) of a low power structure that functions as an interface between the memory of the data processing system and the plurality of processing blocks is further provided. Data transfer of the processing block is performed directly through the memory controller.

The serial data is audio data, and the digital signal processing block performs a general audio algorithm, a phase locked loop for generating an audio clock, and in the digital signal processing block. It is preferable to further include a post processing block for outputting the processed audio data in synchronization with the audio clock.

The plurality of processing blocks sequentially process data, and each of the processing blocks notifies another processing block of the start or end of data processing by itself through a request signal or an acknowledgment signal. The power control unit determines the power control mode using the request signal or the approval signal as an input. It is preferable to further include a clock control block for separating and outputting clocks for the plurality of processing blocks according to the power control mode.

The power mode includes a standby mode, a run mode, and a power off mode. The standby mode is activated after a reset or when a standby command is input in the execution mode or a powerdown pin is deactivated in the power-off mode. In the standby mode, the processing block is static. state. The run mode is activated when a run command is input in the standby mode, and in the run mode, the power controller monitors a state of the processing blocks to mask a clock for the processing blocks. The power off mode is activated when a power down pin is activated in the standby mode, and no clock is supplied to the processing blocks in the power off mode.

It is preferable to further include a device interface part for configuring a clock and data timing according to the format of the data to be processed.

In addition, the present invention provides a system for processing audio data, in which a bit stream processing block for analyzing an input compressed audio bit stream and converting it into a data format for subsequent processing, and output data of the bit stream processing unit are conventional. A digital signal processing block for performing an audio algorithm, a post processing block for outputting audio data processed in the digital signal processing block in synchronization with an audio clock, and controlling the power of the processing blocks. The power control unit has a hardware structure specific to a data processing process, and the power control unit drives only a processing block related to a current data processing process among the plurality of processing blocks.

In the present invention, a bit stream processor (hereinafter referred to as "BSP"), a digital signal processor (hereinafter referred to as "DSP") and a post signal for signal processing of serial data, particularly audio data. A processor such as a post signal processor (hereinafter, referred to as a "PSP") is provided to operate only one processor according to a signal flow, that is, a data processing process, through a power management unit. Each processor has a hardware structure specific to the signal flow, which can significantly reduce power consumption. In addition, the input stream is delivered to the bit stream processor directly through a memory controller (DAM) without any processor involvement. Processors operate only during the decoding process, reducing power consumption. In addition, clock and data timing can be configured without the need to redesign hardware for a variety of audio formats, making it suitable for a wide variety of audio systems.

1 is a block diagram of a low power audio processing apparatus according to an embodiment of the present invention. As shown in FIG. 1, the low power audio processing apparatus according to the present embodiment includes a plurality of processor modules such as a bit stream processor 115, a digital signal processor 117, and a post processor 119 including an equalizer. have. 1, 101 is a power management unit, 103 is a reset generator for generating an internal reset signal, 105 is a phase locked loop circuit, 107 is a parallel host interface / I2C protocol implementation, 109 is a configuration register, 111 is a clock controller for dividing or masking the clock signal, 113 is an input buffer controller Reference numeral 121 denotes a direct memory controller and 123 denotes an audio device interface. 125 is the input buffer, 127 is the BSP data RAM, 129 is the BSP micro code, and 131 is the BSP-DSP interface buffer. 133 denotes a DSP data RAM, 135 denotes a DSP microcode, 137 denotes an output buffer, and 139 denotes an equalizer coefficient RAM.

The BSP 115 is dedicated to bit processing for the audio stream. The compressed data is analyzed and converted into a format for DSP processing. The DSP 117 performs general audio algorithm processing and outputs real-time audio pulse code modulation data from the post processor 119. Between the BSP 115, the DSP 117, the DSP 117, and the post processor 119 so that signal processing for audio may be sequentially performed in the order of the BSP 115, the DSP 117, and the post processor 119. The request and acknowledge signals indicate the start and end of processing. Each processor is in an idle state outside of the time needed for processing, so it can disconnect the clock input. The power control mode is defined by inputting request and acknowledgment signals of the processors, and the prescribed power control mode is supplied to the clock controller 111. The clock control unit 111 separates and outputs a clock input for each processor according to the power control mode. Here, the memory interface of each processor is made through the DMA 121. This is to eliminate memory access by the processor and to reduce power consumption through the DMA 121 of the low power structure. In addition, since the audio device interface 123 can support a data format applicable to any audio system, the system cost can be reduced.

2 is a diagram illustrating a power control mode in the present invention. As shown in FIG. 2, the power control mode in the present invention has three modes, a standby mode 201, a power off mode 203, and an execution mode 205. In the present invention, not only the standby mode 201 but also the power off mode 203 is provided to further reduce power consumption.

The standby mode 201 is set to default after reset. In standby mode 201, only the clock-related portion and the host interface block operate with a programmable clock (1, 1/2, 1/4, 1/8 of the source clock), and the processing block remains in a static state. do. The phase locked loop 105 is powered down according to the configuration of the clock source.

The execute mode 205 is a mode that is activated from the standby mode 201 when issuing an execute command in the host interface block. The host performs parameter setup before issuing a run command. The default clock keeps 1/2 of the source clock and is divided into 1/1, 1/2, and 1/4 depending on the mode. The states of the BSP 115, the DSP 117, and the post block 119 are monitored and clock masking is performed. Transition to the standby mode 201 by the standby command.

The power off mode 203 is activated by activating a powerdown pin in the standby mode 201. In power off mode 203 the clock source is made direct current. When the oscillator is disabled, a problem may occur in the transition to the standby mode 201, so that the PMU 101 and the reset logic 103 are supplied with a clock.

3 is a block diagram of a clock control unit in the present invention. As shown in FIG. 3, a divider 303 for dividing a source clock and a divider 319 for dividing an output signal clko of the PLL circuit portion 315 and the PLL circuit portion 315 are provided. Doing. In FIG. 3, 301, 305, 307, 309, 311, 313, and 317 are multiplexers that select and output an input signal according to a predetermined control signal. For example, the multiplexer 301 is a multiplexer that outputs a direct current in a power down mode and outputs a source clock in a standby mode or a run mode. In addition, source clock is a clock signal input to the clock control unit 111, Sys clk is the processor main clock, BSP clk is the BSP block clock, DSP clk is the DSP engine clock, POST clk is a post block The clock, EQ clk refers to the equalizer clock, mem clk refers to the memory clock.

In accordance with the prescribed power control mode, the clock control unit 111 shown in Fig. 3 supplies the clocks of the processors 115, 117, and 119 separately. The source clock is input and the clock input is cut off in the power-off mode, and the input clock is divided and supplied according to the processing mode. The clocks thus supplied are used to view the idle states of the processors 115, 117, and 119, and provide the clocks separated by the BSP 115, the DSP 117, and the post 119. In addition, the output data processed by the post processor 119 is synchronized with an audio clock Audio clk generated by the PLL circuit 315 and then output as audio data.

Fig. 4 is a diagram showing the structure of the memory system in the present invention. Data transfer of each processor is performed through the DMA 121 as described above. Each channel of the DMA 121 stores a source and a destination area and transfers data from the source to the destination upon initiation. The processors are then idle. As shown in Fig. 4, the memory system in the present invention shows a structure shared with each other. DMA can be in any area.

5 is a block diagram of an audio device interface in the present invention. As shown in FIG. 5, a configuration register 501, a clock controller 503, an audio output buffer 505, a data timing controller 507, and an audio interface generator 509 are provided. The configuration register 501 is a register that stores a configuration for clock division ratio, start / stop control, and data format, and supplies configuration information to the clock control unit 503 and the audio interface generating unit 509. The clock control unit 503 divides the source clock in accordance with the configuration information output from the configuration register 501. The audio output buffer 505 buffers the decoded parallel data. The data timing controller 507 converts the parallel data according to the configuration information into serial data and transmits the serial data. The audio interface generator 509 processes data in accordance with the configuration information from the configuration register 501. This configuration automatically creates an interface structure that can be applied to audio devices with various formats.

The present invention is a structure designed for the purpose of a low power decoder and can be applied to all systems for serial data processing such as an audio system. The configuration related to the above embodiment is only intended to embody the present invention and is not intended to limit the scope of the present invention. Therefore, those skilled in the art should note that various modifications or changes to the configuration related to the above embodiments are possible within the scope of the present invention. The scope of the invention is defined in principle by the claims that follow.

When using a general DSP, compared to a conventional audio processor that operates almost all of the hardware of the DSP, the BSP, DSP, and post processor separated by functions allow for sequential audio signal processing, thereby enabling 1/2 to 1 / The same application program can be processed with three driving frequencies. In addition, in the case of the separated processor, since the driving area is reduced to about 1/2 to 1/5, the overall power consumption is reduced by about 1/4 to 1/15. Compared with a typical audio processor, the driving frequency has a ratio of 10 MHz / 25 MHz and a ratio of 100,000 / 30,000 in area. DMA also reduces the I / O performance of each processor and reduces power consumption by one third compared to memory access. The area to be increased may be an area of four channel DMA. In addition, since a configuration audio format interface can be implemented, it can be applied to various audio devices, thereby making it easier to implement a system.

Claims (11)

In a system for serial data processing, A processor composed of a plurality of processing blocks, A power control unit controlling power of the processor Equipped, The processing block of the processor has a hardware structure specific to a data processing process, and the power control unit drives only a processing block related to a current data processing process among the plurality of processing blocks. The method of claim 1, The processor is to the plurality of processing blocks A bit stream processing block for analyzing the compressed bit stream input to the data processing system and converting the compressed bit stream into a data format for subsequent processing; A digital signal processing block for performing normal digital signal processing on the output data of the bit stream processing unit A data processing system comprising: a. The method of claim 2, And a low power structure direct memory controller (DMA) that functions as an interface between the memory of the data processing system and the plurality of processing blocks. And the input stream is delivered to the bit stream processing block by the direct memory controller without the processing blocks being involved. The method of claim 3, And data transfer of the processing block is performed through the direct memory controller. The method of claim 2, The serial data is audio data, The digital signal processing block performs a general audio algorithm, A phase locked loop that generates an audio clock, And a post processing block for outputting the audio data processed by the digital signal processing block in synchronization with the audio clock. The method of claim 1, And said plurality of processing blocks sequentially process data, each of said processing blocks notifying another processing block of the start or end of data processing by itself through a request signal or an acknowledgment signal. The method of claim 6, And the power control unit determines the power control mode using the request signal or the approval signal as an input. The method of claim 7, wherein And a clock control block for separating and outputting clocks for the plurality of processing blocks according to the power control mode. The method of claim 7, wherein The power mode includes a standby mode, a run mode and a power off mode, The standby mode is activated after a reset or when a standby command is input in the execution mode or a powerdown pin is deactivated in the power-off mode. In the standby mode, the processing block is static. state) The run mode is activated when a run command is input in the standby mode, and in the run mode, the power controller monitors a state of the processing blocks to mask a clock for the processing blocks, The power off mode is activated when a power down pin is activated in the standby mode, and a clock is not supplied to the processing blocks in the power off mode. The method of claim 1, And a device interface part for configuring a clock and data timing according to the format of the data to be processed. In the system for processing audio data, A bit stream processing block for analyzing the input compressed audio bit stream and converting it into a data format for subsequent processing; A digital signal processing block for performing a conventional audio algorithm on the output data of the bit stream processor; A post processing block for outputting audio data processed by the digital signal processing block in synchronization with an audio clock; A power control unit controlling power of the processing blocks Equipped, The processing blocks have a hardware structure specific to a data processing process, and the power control unit drives only a processing block related to a current data processing process among the plurality of processing blocks.