KR20030001584A - An improving method of gap-fill characteristic using surface catalysts - Google Patents

An improving method of gap-fill characteristic using surface catalysts Download PDF

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KR20030001584A
KR20030001584A KR1020010036361A KR20010036361A KR20030001584A KR 20030001584 A KR20030001584 A KR 20030001584A KR 1020010036361 A KR1020010036361 A KR 1020010036361A KR 20010036361 A KR20010036361 A KR 20010036361A KR 20030001584 A KR20030001584 A KR 20030001584A
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metal layer
surface catalyst
gap
catalyst
compound
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KR1020010036361A
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Korean (ko)
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황의성
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주식회사 하이닉스반도체
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Publication of KR20030001584A publication Critical patent/KR20030001584A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances

Abstract

PURPOSE: A method for improving a gap-fill characteristic by using surface catalyst is provided to ultimately increase yield by using a compound including a halogen element as the surface catalyst in forming a metal layer. CONSTITUTION: After an interlayer dielectric(3) is formed on a substrate(1) having the first metal layer(2), the interlayer dielectric is selectively etched to expose the surface of the metal layer. A surface catalyst compound is induced to make the surface catalyst(5) absorbed to the surface of the exposed first metal layer. The second metal layer(6) is formed on the resultant structure to be exchanged for the surface catalyst so that the second metal layer comes in contact with the first metal layer.

Description

표면 촉매를 이용한 갭-필 특성 개선 방법{An improving method of gap-fill characteristic using surface catalysts}An improving method of gap-fill characteristic using surface catalysts

본 발명은 반도체 소자의 제조 방법에 관한 것으로 특히, 갭-필 특성 개선 방법에 관한 것으로, 더욱 상세하게는 표면 촉매를 이용한 갭-필 특성 개선 방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method for improving gap-fill characteristics, and more particularly, to a method for improving gap-fill characteristics using a surface catalyst.

반도체 소자 제조 공정은 빠른 속도로 고집적화됨에 따라 요구되는 최소 선폭은 더욱 초미세화 되고 있다.As the semiconductor device manufacturing process is rapidly and highly integrated, the minimum line width required is further miniaturized.

이에 따라 금속화(Metallization) 등의 공정 개발에 대한 중요성이 증가하고 있다. 초기의 금속화 공정은 모두 물리기상 증착(Physical Vapor Deposition; 이하 PVD라 함)법을 이용하여 금속선을 형성하였으나, 서브 마이크론(Sub-micron) 이하의 선폭을 요구하는 제조 공정에서부터 화학기상 증착(Chemical Vapor Deposition; 이하 CVD라 함)법이 도입되어 사용되어 왔다. 즉, 콘택홀(Contact hole) 또는 비아홀(Via hole)의 종횡비(Aspect ratio)가 증가하면서 PVD보다 갭필, 즉 홀 채움 특성이 우수한 CVD의 특성 때문에 CVD에 의한 금속화 공정이 반도체 소자 제조 공정에 필수적으로 적용되고 있다.Accordingly, the importance of process development such as metallization is increasing. In the early metallization process, all of the metal lines were formed using physical vapor deposition (PVD), but chemical vapor deposition (Chemical) was started from the manufacturing process requiring a sub-micron line width. Vapor Deposition (hereinafter referred to as CVD) method has been introduced and used. That is, the metallization process by CVD is essential for the semiconductor device manufacturing process because of the increase in the aspect ratio of the contact hole or via hole and the characteristics of CVD with better gap fill, that is, hole filling characteristics, than PVD. Is being applied.

그러나, 서브-0.1㎛ 이하의 최소 선폭이 요구되는 공정에서는 일반 CVD법도 한계를 갖게 된다. 즉, 기가 스케일(Giga scale) 이상으로 집적화되면서 필요한 콘택홀의 종횡비가 10 이상으로 증가하게 되어, CVD법에 의해 홀을 완전히 채우지 못하고 홀 내부에 빈 공간을 형성하거나 주름살 모양의 균열(Seam) 등을 형성하게 된다. 그 결과 집적도가 증가할 수록 금속 접촉 저항은 기하급수적으로 증가하게 되며, 이에 따라 종횡비가 큰 콘택홀을 완전히 채울 수 있는 새로운 방법들이 요구되고 있다.However, general CVD methods also have limitations in processes requiring a minimum line width of sub-0.1 μm or less. In other words, the integration ratio of the required contact hole is increased to 10 or more as it is integrated above the giga scale, so that the hole is not completely filled by the CVD method and an empty space is formed inside the hole, To form. As a result, as contact density increases, metal contact resistance increases exponentially, and new methods are needed to completely fill contact holes with high aspect ratios.

한편, 이러한 요구 사항에 대한 대안으로 원자층 증착(Atomic Layer Deposition; 이하 ALD라 함)법이 사용되고 있으나, 단원자층 형성을 반복적으로 수행하는 특성 상 증착 속도가 매우 느리다는 단점이 있으며, 이 역시 홀 내부를 모두 채우는 데는 한계가 있다.On the other hand, the atomic layer deposition (ALD) method is used as an alternative to this requirement, but it has a disadvantage that the deposition rate is very slow due to the property of repeatedly forming the monoatomic layer, which is also a hole There is a limit to filling the interior.

상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 본 발명은, 금속에서만 선택적으로 화학흡착 반응을 하는 특성을 갖고 있으며, 동시에 화학기상 증착 반응에 대한 촉매 역할을 하여 반응속도를 향상시키는 특성을 갖는 표면 촉매제를 선도입하여 금속 박막을 금속 표면에서만 낮은 온도에서 빠른 속도로 증착시킨 후, CVD 금속화 공정을 진행함으로써 홀의 바닥에서부터 금속이 성장하여 빈공간이나 주름살 모양의 균열없이 홀 내부를 완벽하게 채울 수 있는 표면 촉매를 이용한 갭-필 특성 개선 방법을 제공하는데 그 목적이 있다.The present invention proposed to solve the problems of the prior art as described above, has a characteristic of selectively chemisorption reaction only in the metal, and at the same time has a characteristic of improving the reaction rate by acting as a catalyst for chemical vapor deposition reaction Leading surface catalyst is used to rapidly deposit metal thin films at low temperatures only on metal surfaces, and then proceed with the CVD metallization process to grow metal from the bottom of the hole to fill the hole perfectly without voids or creases. It is an object of the present invention to provide a method for improving gap-fill characteristics using a surface catalyst.

도 1a 내지 도 1c는 본 발명의 일실시예에 따른 표면 촉매를 이용한 금속배선 공정을 도시한 단면도,1A to 1C are cross-sectional views illustrating a metal wiring process using a surface catalyst according to an embodiment of the present invention;

도 2는 금속 표면에서 할로겐 원소의 흡착 유무가 MOCVD-Cu의 증착속도에 미치는 영향을 기판 온도에 따라 도시한 그래프.2 is a graph showing the effect of the adsorption of halogen on the metal surface on the deposition rate of MOCVD-Cu according to the substrate temperature.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

1 : 기판1: substrate

2 : 제1금속층2: first metal layer

3 : 층간절연막3: interlayer insulating film

4 : 콘택홀4: contact hole

5 : 표면 흡착제5: surface adsorbent

6 : 제2금속층6: second metal layer

상기와 같은 문제점을 해결하기 위해 본 발명은, 제1 금속층이 형성된 기판 상에 층간 절연막을 형성한 후, 상기 층간 절연막을 선택적으로 식각하여 상기 금속층 표면을 노출시키는 단계; 표면 촉매 화합물을 유입하여 상기 노출된 제1금속층 표면에 표면 촉매제를 선흡착시키는 단계; 상기 결과물 상에 제2 금속층을 형성하되, 상기 표면 촉매제와 자리 바꿈하여 상기 제1금속층에 콘택되도록 하는 단계를 포함하여 이루어지는 표면 촉매를 이용한 갭-필 특성 개선 방법을 제공한다.In order to solve the above problems, the present invention, after forming an interlayer insulating film on the substrate on which the first metal layer is formed, selectively etching the interlayer insulating film to expose the surface of the metal layer; Introducing a surface catalyst compound to adsorb a surface catalyst on the exposed surface of the first metal layer; Forming a second metal layer on the resultant, and replacing with the surface catalyst provides a method for improving the gap-fill characteristics using a surface catalyst comprising the step of contacting the first metal layer.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 첨부한 도면을 참조하여 상세하게 설명한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can more easily implement the present invention.

도 1a 내지 도 1c는 본 발명의 일실시예에 따른 표면 촉매를 이용한 금속배선 공정을 도시한 단면도이다.1A to 1C are cross-sectional views illustrating a metal wiring process using a surface catalyst according to an embodiment of the present invention.

먼저 도 1a에 도시된 바와 같이, 반도체 소자를 이루기 위한 여러 요소가 형성된 기판(1) 상에 소정의 금속층(2)을 형성한 다음, 그 상부에 층간절연막(3)을 형성한다. 이어서, 층간절연막(3)을 선택적으로 식각하여 금속층(2) 표면을 노출시킴으로써, 금속배선 등을 위한 콘택홀(4)을 형성한다. 여기서, 콘택홀(4)은 다중 금속 배선일 경우에는 비아홀로 적용 가능하며, 본 발명의 실시예에서는 콘택홀을 일예로 하였으며, 금속층(2)은, Cu, Al, W, Pt, Co, Ir, Ti, Ta, Zr, Hf 또는 이들의 산화물을 포함한다.First, as shown in FIG. 1A, a predetermined metal layer 2 is formed on a substrate 1 on which various elements for forming a semiconductor element are formed, and then an interlayer insulating film 3 is formed thereon. Subsequently, the interlayer insulating film 3 is selectively etched to expose the surface of the metal layer 2, thereby forming a contact hole 4 for metal wiring or the like. Here, the contact hole 4 may be applied as a via hole in the case of multiple metal wires, and in the embodiment of the present invention, the contact hole is an example, and the metal layer 2 includes Cu, Al, W, Pt, Co, Ir, Ti, Ta, Zr, Hf or oxides thereof.

다음으로 도 1b에 도시된 바와 같이, 노출된 금속층(2) 표면에만 표면 촉매제(5)를 화학흡착시킨다.Next, as shown in FIG. 1B, the surface catalyst 5 is chemisorbed only on the exposed metal layer 2 surface.

구체적으로, 기판(1)을 금속 증착 반응기에 넣은 후, 반응기 내부에 표면 촉매 화합물을 유입하여 노출된 금속층(2) 표면에만 화학흡착시킨다.Specifically, after the substrate 1 is placed in the metal deposition reactor, the surface catalyst compound is introduced into the reactor to be chemisorbed only on the exposed metal layer 2 surface.

다음으로 도 1c에 도시된 바와 같이, 화학흡착이 완료된 후, 반응기 내에 잔류하는 화합물을 제거하는 바, He, Ne, Ar 또는 Xe 등의 비활성 기체 또는 N2, H2기체를 이용하여 퍼지(Purge) 및 펌핑(Pimping)을 한 다음, 금속 화학 증착을 위한 전구체(Precursor)를 반응기 내에 유입하여 표면 촉매제(5)가 흡착된 영역에서만 금속층(6)이 성장하도록 반응시킨다. 이 때, 표면 촉매제(5)는 증착하는 금속 원자와 빠르게 자리바꿈하여 항상 표면에만 흡착되는 성질을 가져야 한다.Next, as shown in Figure 1c, after the chemical adsorption is completed, to remove the compound remaining in the reactor, purge using an inert gas such as He, Ne, Ar or Xe or N 2 , H 2 gas And pumping, a precursor for metal chemical deposition is introduced into the reactor to react the metal layer 6 to grow only in the region where the surface catalyst 5 is adsorbed. At this time, the surface catalyst 5 should be quickly replaced with the metal atom to be deposited, and always have the property to be adsorbed only on the surface.

예컨대, 금속유기 화학기상 증착(Metal Organic Chemical Vapor Deposition; 이하 MOCVD라 함)법에 의한 Cu 금속층(6) 형성 시, F, Cl, Br 또는 I와 같은 할로겐 물질을 표면 촉매제(5)로 사용하는 바, 이러한 표면 촉매제(5)로 사용할 수 있는 화합물은 R-Ix와 R-Brx이다.For example, in the formation of the Cu metal layer 6 by the Metal Organic Chemical Vapor Deposition (MOCVD) method, a halogen material such as F, Cl, Br or I is used as the surface catalyst 5. The compounds which can be used as the surface catalyst (5) are R-Ix and R-Brx.

여기서, R은 수소, 알킬, 카르복실, 에테르 또는 수소 대신 불소나 염소가 탄소에 치환된 알킬화합물이며, x는 1 ∼ 3이다. 이러한 화합물은 일정 온도 이상에서 금속 표면과의 상호 반응에 의해 R 치환기는 기상으로 배출되고 할로겐 원소 만이 금속 표면에 흡착하게 된다.R is an alkyl compound in which fluorine or chlorine is substituted for carbon in place of hydrogen, alkyl, carboxyl, ether or hydrogen, and x is 1-3. These compounds react with the metal surface above a certain temperature so that the R substituent is released into the gas phase and only the halogen element is adsorbed on the metal surface.

도 2는 금속 표면에서 할로겐 원소의 흡착 유무가 MOCVD-Cu의 증착속도에 미치는 영향을 기판 온도에 따라 도시한 그래프이다.2 is a graph showing the effect of the adsorption of halogen on the metal surface on the deposition rate of MOCVD-Cu according to the substrate temperature.

도 2를 참조하면, 기판 온도가 100℃일 때 할로겐 원소가 없는 기판에서는 10Å/min 이하의 증착 속도를 보이지만, 할로겐 원소가 흡착된 기판에서는 1000Å/min 까지 증착 속도가 증가하여 100배 이상 빨라짐을 알 수 있다.Referring to FIG. 2, when the substrate temperature is 100 ° C., a deposition rate of 10 μs / min or less is shown on a substrate without a halogen element, but a deposition rate is increased to 1000 μs / min by a halogen element adsorbed substrate, which is 100 times faster. Able to know.

또한, 기판 온도가 50℃일 때는 할로게 원소가 없는 경우 Cu의 증착이 거의 이루어지지 않는 반면 할로겐 원소가 흡착된 표면에서는 250Å/min 까지 증착 속도가 나타남을 알 수 있다.In addition, when the substrate temperature is 50 ℃ it can be seen that the deposition of Cu almost does not occur when there is no halogen element, while the deposition rate appears up to 250 Å / min on the surface where the halogen element is adsorbed.

따라서, 상기한 바와 같은 본 발명은 콘택홀 또는 비아홀 등의 저면에만 할로겐 원소가 흡착되며, 이 후에 낮은 온도에서 Cu 등의 금속층을 성장시키면 홀의 저면에서 부터 Cu가 성장하여 빈 공간이나 주름살 모양의 균열 없이 거의 완벽하게 갭-필할 수 있으며, 표면 촉매제의 일부가 계면 활성제로서도 작용하는 특성을 갖고 있기 때문에 표면이 매끈한 박막을 형성할 수 있어 후속의 노광 및 식각 공정에 대한 마진을 높일 수 있음을 실시예를 통해 알아 보았다.Therefore, in the present invention as described above, the halogen element is adsorbed only on the bottom of the contact hole or the via hole, and when the metal layer such as Cu is grown at a low temperature, Cu is grown from the bottom of the hole to form an empty space or wrinkled crack. It can be almost completely gap-free without, and because some of the surface catalysts also have a property of acting as a surfactant, it is possible to form a thin film with a smooth surface to increase the margin for subsequent exposure and etching processes. Learned through.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

전술한 본 발명은, 금속층 형성시 할로겐 원소를 포함하는 화합물을 표면 촉매제로 이용함으로써, 갭-필 특성을 향상시키며, 후속 공정 마진을 향상시킴으로써, 궁극적으로 소자 수율을 향상시킬 수 있는 탁월한 효과를 기대할 수 있다.The present invention described above, by using a compound containing a halogen element as a surface catalyst in the formation of a metal layer, it is expected that the excellent effect that can improve the gap-fill characteristics, improve the subsequent process margin, ultimately improve the device yield Can be.

Claims (6)

반도체 소자 제조 방법에 있어서,In the semiconductor device manufacturing method, 제1 금속층이 형성된 기판 상에 층간 절연막을 형성한 후, 상기 층간 절연막을 선택적으로 식각하여 상기 금속층 표면을 노출시키는 단계;Forming an interlayer insulating film on the substrate on which the first metal layer is formed, and then selectively etching the interlayer insulating film to expose a surface of the metal layer; 표면 촉매 화합물을 유입하여 상기 노출된 제1금속층 표면에 표면 촉매제를 선흡착시키는 단계;Introducing a surface catalyst compound to adsorb a surface catalyst on the exposed surface of the first metal layer; 상기 결과물 상에 제2 금속층을 형성하되, 상기 표면 촉매제와 자리 바꿈하여 상기 제1금속층에 콘택되도록 하는 단계Forming a second metal layer on the resultant, inverting the surface catalyst to make contact with the first metal layer; 를 포함하여 이루어지는 표면 촉매를 이용한 갭-필 특성 개선 방법.Method for improving the gap-fill characteristics using a surface catalyst comprising a. 제 1 항에 있어서,The method of claim 1, 상기 표면 촉매제는, Cl, Br 또는 I 중 어느 하나인 것을 특징으로 하는 표면 촉매를 이용한 갭-필 특성 개선 방법.The surface catalyst is a method of improving the gap-fill characteristics using a surface catalyst, characterized in that any one of Cl, Br or I. 제 1 항에 있어서,The method of claim 1, 상기 표면 촉매 화합물은, R-Ix(R은 수소, 알킬, 카르복실, 에테르 또는 수소 대신 불소나 염소가 탄소에 치환된 알킬화합물, x는 1 내지 3) 또는 R-Brx 중어느 하나인 것을 특징으로 하는 표면 촉매를 이용한 갭-필 특성 개선 방법.The surface catalyst compound is R-Ix (R is hydrogen, alkyl, carboxyl, ether, or an alkyl compound in which fluorine or chlorine is substituted for carbon instead of hydrogen, x is 1 to 3) or R-Brx any one of Method for improving the gap-fill characteristics using a surface catalyst. 제 1 항에 있어서,The method of claim 1, 상기 표면 촉매제 선흡착 후, He, Ne, Ar, Xe, N2또는 H2중 어느 하나를 이용한 퍼지 및 펌핑을 실시하여 잔류하는 화합물을 제거하는 단계를 더 포함하는 것을 특징으로 하는 표면 촉매를 이용한 갭-필 특성 개선 방법.After the surface catalyst pre-adsorption, the step of purging and pumping using any one of He, Ne, Ar, Xe, N 2 or H 2 to remove the remaining compound using a surface catalyst, characterized in that How to improve gap-fill properties. 제 1 항에 있어서,The method of claim 1, 상기 제1, 2금속층은, Cu, Al, W, Pt, Co, Ir, Ti, Ta, Zr, Hf 또는 이들의 산화물 중 어느 하나인 것을 특징으로 하는 표면 촉매를 이용한 갭-필 특성 개선 방법.The first and the second metal layer is Cu, Al, W, Pt, Co, Ir, Ti, Ta, Zr, Hf or any one of these oxides, gap-fill characteristics improvement method using a surface catalyst. 제 1 항에 있어서,The method of claim 1, 상기 제2 금속층의 형성은, 금속유기 화학기상 증착법 또는 화학기상 증착법 중 어느 하나를 이용하는 것을 특징으로 하는 표면 촉매를 이용한 갭-필 특성 개선 방법.The second metal layer may be formed using a metal organic chemical vapor deposition method or a chemical vapor deposition method.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101008002B1 (en) * 2010-09-14 2011-01-14 시너스 테크놀리지, 인코포레이티드 Method of forming substrate structure and method of manufacturing device comprising the same
KR101060560B1 (en) * 2003-12-10 2011-08-31 매그나칩 반도체 유한회사 Metal wiring formation method of semiconductor device
US8263502B2 (en) 2008-08-13 2012-09-11 Synos Technology, Inc. Forming substrate structure by filling recesses with deposition material

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101060560B1 (en) * 2003-12-10 2011-08-31 매그나칩 반도체 유한회사 Metal wiring formation method of semiconductor device
US8263502B2 (en) 2008-08-13 2012-09-11 Synos Technology, Inc. Forming substrate structure by filling recesses with deposition material
KR101008002B1 (en) * 2010-09-14 2011-01-14 시너스 테크놀리지, 인코포레이티드 Method of forming substrate structure and method of manufacturing device comprising the same

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