KR20030001074A - Method for forming a via by dual damascence process - Google Patents
Method for forming a via by dual damascence process Download PDFInfo
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- KR20030001074A KR20030001074A KR1020010037404A KR20010037404A KR20030001074A KR 20030001074 A KR20030001074 A KR 20030001074A KR 1020010037404 A KR1020010037404 A KR 1020010037404A KR 20010037404 A KR20010037404 A KR 20010037404A KR 20030001074 A KR20030001074 A KR 20030001074A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 듀얼다마신 공정(Dual damascene process)에 의한 비아의 형성 방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming vias by a dual damascene process.
반도체 소자 제조에 있어 칩의 디멘션이 작아질수록 RC 지연, 교류전력, 누화에 영향을 미치는 배선 캐패시턴스를 줄이기 위해 금속간절연막(Inter Metal Dielectric; IMD)으로 저유전상수(low-k)를 갖는 절연막을 적용하는 다마신 공정이 개발되고 있다.In semiconductor device manufacturing, as the chip dimension decreases, an insulating film having a low dielectric constant (low-k) is used as an inter metal dielectric (IMD) in order to reduce wiring capacitance affecting RC delay, AC power, and crosstalk. An application damascene process is being developed.
일반적으로 다마신 공정은 절연막을 식각하여 트렌치를 형성하고, 트렌치에 배선막을 매립시키는 공정으로, 트렌치 하부에 비아(Via)가 정렬되는 자기정렬 듀얼 다마신 공정(Self-aligned dual damascene etching)이 주로 이용되고 있다.In general, the damascene process forms a trench by etching an insulating film and fills a wiring film in the trench, and a self-aligned dual damascene etching process in which vias are aligned under the trench is mainly used. It is used.
자기정렬 듀얼 다마신 공정은 절연막을 사진 및 식각으로 식각하여 트렌치(Trench)를 형성하고, 이 트렌치에 텅스텐(W), 알루미늄, 구리 등의 도전 물질을 채워 넣고 필요한 배선 이외의 도전 물질은 에치백(Etchback)이나 화학적기계적연마(Chemical Mechanical Polishing; CMP) 등의 기술을 이용하여 제거하므로써 처음에 형성한 트렌치 모양으로 배선을 형성하는 기술이다.In the self-aligned dual damascene process, the insulating film is etched by photo and etching to form a trench, and the trench is filled with a conductive material such as tungsten (W), aluminum, or copper, and the conductive material other than the necessary wiring is etched back. It is a technique for forming wiring in the trench shape first formed by removing using techniques such as etching or chemical mechanical polishing (CMP).
이러한 자기정렬 듀얼 다마신 기술은 주로 DRAM 등의 비트 라인(bit line) 또는 워드라인(Wordline), 금속배선 형성에 이용되며, 특히 다층 금속배선에서 상층 금속배선과 하층 금속배선을 접속시키기 위한 비아홀을 동시에 형성할 수 있을뿐만 아니라, 금속배선에 의해 발생하는 단차를 제거할 수 있으므로 후속 공정을 용이하게 하는 장점이 있다.The self-aligned dual damascene technology is mainly used for forming bit lines, word lines, and metal interconnections such as DRAMs. In particular, via holes for connecting upper metal interconnections and lower metal interconnections in multilayer metal interconnections are provided. Not only can it be formed at the same time, it is possible to eliminate the step caused by the metal wiring has the advantage of facilitating subsequent processes.
도 1a 내지 도 1d는 종래기술에 따른 듀얼다마신 공정에 의한 알루미늄배선의 형성 방법을 도시한 공정 단면도이다.1A to 1D are cross-sectional views illustrating a method of forming an aluminum wiring by the dual damascene process according to the prior art.
도 1a에 도시된 바와 같이, 반도체기판(11)내에 소스/드레인(12)을 형성한 후, 반도체기판(11)상에 층간절연막(13)을 형성하고, 층간절연막(13)을 선택적으로 식각하여 소스/드레인(12)의 소정 표면을 노출시키는 콘택홀을 형성한다.As shown in FIG. 1A, after the source / drain 12 is formed in the semiconductor substrate 11, the interlayer insulating layer 13 is formed on the semiconductor substrate 11, and the interlayer insulating layer 13 is selectively etched. To form a contact hole exposing a predetermined surface of the source / drain 12.
계속해서, 콘택홀에 매립되는 금속콘택(14)을 형성한 후, 층간절연막(13)상에 알루미늄(15a)과 반사방지막(15b)의 적층막을 형성하고, 반사방지막(15b) 및 알루미늄(15a)을 순차적으로 식각하여 제1 알루미늄배선을 형성한다.Subsequently, after forming the metal contact 14 buried in the contact hole, a laminated film of aluminum 15a and an antireflection film 15b is formed on the interlayer insulating film 13, and the antireflection film 15b and the aluminum 15a are formed. ) Is sequentially etched to form a first aluminum wiring.
도 1b에 도시된 바와 같이, 제1 알루미늄배선을 포함한 전면에 제1 금속간절연막(16), 식각정지막(17), 제2 금속간절연막(18)을 순차적으로 형성한 후, 제2 금속간절연막상에 감광막을 도포하고 노광 및 현상으로 패터닝하여 비아홀 마스크(도시 생략)를 형성한다.As shown in FIG. 1B, the first intermetallic insulating film 16, the etch stop film 17, and the second intermetallic insulating film 18 are sequentially formed on the entire surface including the first aluminum wiring, and then the second metal is formed. A photoresist film is applied on the interlayer insulating film and patterned by exposure and development to form a via hole mask (not shown).
계속해서, 비아홀 마스크를 이용하여 제2 금속간절연막, 식각정지막, 제1 금속간절연막을 식각하므로써 제 1 알루미늄배선의 표면을 노출시키는 비아홀(19)을 형성한다.Subsequently, a via hole 19 exposing the surface of the first aluminum wiring is formed by etching the second intermetallic insulating film, the etch stop film, and the first intermetallic insulating film using a via hole mask.
도 1c에 도시된 바와 같이, 비아홀 마스크를 제거한 후, 전면에 감광막을 다시 도포하고 노광 및 현상으로 패터닝하여 비아홀 마스크보다 큰 선폭을 갖는 트렌치 마스크(20)를 형성한다.As shown in FIG. 1C, after the via hole mask is removed, the photoresist film is coated on the entire surface and patterned by exposure and development to form a trench mask 20 having a line width larger than that of the via hole mask.
계속해서, 식각정지막(17)에서 식각이 멈추도록 트렌치 마스크를 이용하여 제2 금속간절연막을 식각하므로써 비아홀(19) 상부에 트렌치(21)를 형성한다.Subsequently, the trench 21 is formed in the upper portion of the via hole 19 by etching the second intermetallic insulating layer using a trench mask to stop the etching in the etch stop layer 17.
도 1d에 도시된 바와 같이, 트렌치(21)가 형성된 제2 금속간절연막(18)상에 알루미늄을 증착한 후, 화학적기계적연마하여 비아홀에 매립되는 비아(22a)와 트렌치(21)에 매립되는 제2 알루미늄배선(22b)을 동시에 형성한다.As shown in FIG. 1D, aluminum is deposited on the second intermetallic insulating film 18 on which the trench 21 is formed, and then, chemically polished by a mechanical mechanical polishing and embedded in the via 22a and the trench 21. The second aluminum wiring 22b is formed at the same time.
여기서, 제1,2 금속간절연막(16,18)은 산화막을 이용하며, 식각정지막(17)은 질화막을 이용한다.Here, the first and second intermetallic insulating layers 16 and 18 use an oxide film, and the etch stop layer 17 uses a nitride film.
상술한 종래기술에서는 듀얼다마신 공정을 알루미늄 배선 형성에 적용하므로써 공정을 단순화시키고 비용을 절감하는 효과가 있다.In the above-described prior art, the dual damascene process is applied to the aluminum wiring to simplify the process and reduce the cost.
그러나, 종래기술은 제1 알루미늄배선상에 비아홀(19)를 형성하기 위해 플루오린계 가스(Fluorine base gas)로 제1 금속간절연막(16)인 산화막을 식각하는데, 이럴 경우 제1 알루미늄배선상에 비휘발성 금속폴리머(도 1b의 'A')인 알루미늄플로라이드(Al fluorides)가 형성되고, 이러한 금속폴리머는 산소(oxygen) 또는 오존(ozon) 가스를 이용한 애싱(ashing) 공정후 제거되지 않고 잔류하므로써 비아의 저항을 증가시키는 문제점이 있다.However, the prior art etches the oxide film, which is the first intermetallic insulating film 16, with a fluorine base gas to form the via holes 19 on the first aluminum wiring, in which case the first aluminum wiring is etched on the first aluminum wiring. Aluminum fluoride (Al fluorides), which is a nonvolatile metal polymer ('A' in FIG. 1B), is formed, and the metal polymer remains unremoved after an ashing process using oxygen or ozone gas. This increases the resistance of the vias.
본 발명은 상기한 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 비아홀 형성을 위한 산화막 식각시 생성되는 금속성 폴리머로 인한 비아의 저항 증가를 억제하는데 적합한 듀얼다마신 공정에 의한 비아의 형성 방법을 제공하는데 그목적이 있다.The present invention has been made to solve the above-mentioned problems of the prior art, and provides a method of forming vias by a dual damascene process suitable for suppressing an increase in resistance of vias due to a metallic polymer produced during oxide etching for forming via holes. The purpose is to.
도 1a 내지 도 1d는 종래기술에 따른 듀얼다마신 공정에 의한 비아의 형성 방법을 도시한 공정 단면도,1A to 1D are cross-sectional views illustrating a method of forming a via by a dual damascene process according to the prior art;
도 2는 본 발명의 일실시예에 따른 듀얼다마신 공정에 의한 비아의 형성 방법을 도시한 공정 흐름도,2 is a process flow diagram illustrating a method of forming vias by the dual damascene process according to one embodiment of the present invention;
도 3a 내지 도 3b는 도 2에 따른 비아의 형성 방법을 도시한 공정 단면도,3A to 3B are cross-sectional views illustrating a method of forming a via according to FIG. 2;
도 4는 본 발명의 다른 실시예에 따른 듀얼다마신 공정에 의한 비아 형성 방법을 도시한 공정 흐름도.4 is a process flow diagram illustrating a via formation method by a dual damascene process in accordance with another embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
31 : 반도체기판 33 : 층간절연막31 semiconductor substrate 33 interlayer insulating film
34 : 금속콘택 35a : 알루미늄34: metal contact 35a: aluminum
35b : 반사방지막 36 : 제 1 금속간절연막35b: antireflection film 36: first intermetallic insulating film
37 : 식각정지막 38 : 제 2 금속간절연막37: etch stop film 38: second intermetallic insulating film
39a : 비아 39b : 제 2 알루미늄배선39a: via 39b: second aluminum wiring
상기의 목적을 달성하기 위한 본 발명의 듀얼다마신 공정에 의한 비아의 형성 방법은 반도체기판상에 제 1 배선층을 형성하는 단계, 상기 제 1 배선층상에 층간절연막, 식각정지막을 차례로 형성하는 단계, 상기 식각정지막 및 상기 층간절연막을 선택적으로 식각하여 상기 제1배선층의 표면을 노출시키는 비아홀을 형성하는 단계, 질산용액으로 상기 비아홀 형성후 발생된 폴리머를 제거하는 단계; 및 상기 비아홀상부에 트렌치를 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.A method of forming a via by a dual damascene process of the present invention for achieving the above object comprises the steps of forming a first wiring layer on a semiconductor substrate, sequentially forming an interlayer insulating film, an etch stop film on the first wiring layer, Selectively etching the etch stop layer and the interlayer insulating layer to form a via hole exposing the surface of the first wiring layer, and removing the polymer generated after the via hole is formed with nitric acid solution; And forming a trench on the via hole.
바람직하게, 상기 질산용액은 희석된 질산이나 기화된 질산 중 어느 하나를 선택함을 특징으로 한다.Preferably, the nitric acid solution is characterized in that it is selected from dilute nitric acid or vaporized nitric acid.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 2는 본 발명의 일실시예에 따른 듀얼다마신 공정에 의한 비아의 형성 방법을 도시한 공정 흐름도이고, 도 3a 내지 도 3b는 도 2에 따른 희석된 질산을 이용한 금속성 폴리머의 제거 과정을 도시한 도면이다.2 is a process flow diagram illustrating a method of forming vias by the dual damascene process according to one embodiment of the present invention, and FIGS. 3A to 3B illustrate a process of removing a metallic polymer using diluted nitric acid according to FIG. 2. One drawing.
도 2 및 도 3a 내지 도 3b를 참조하면, 반도체기판(31)에 소스/드레인(32)을 형성한 후, 반도체기판(31)상에 층간절연막(33)을 형성하고, 층간절연막(33)을 선택적으로 식각하여 소스/드레인(32)의 소정 표면을 노출시키는 콘택홀을 형성한다.2 and 3A to 3B, after the source / drain 32 is formed on the semiconductor substrate 31, the interlayer insulating layer 33 is formed on the semiconductor substrate 31, and the interlayer insulating layer 33 is formed. Is selectively etched to form contact holes exposing predetermined surfaces of the source / drain 32.
계속해서, 콘택홀에 매립되는 금속콘택(34)을 형성한 후, 층간절연막(33)상에 알루미늄(35a)과 반사방지막(35b)의 적층막을 형성하고, 반사방지막(35b) 및 알루미늄(35a)을 순차적으로 식각하여 제1 알루미늄배선을 형성한다(100). 여기서, 반사방지막(35b)은 알루미늄의 어택을 방지하기 위한 막으로서, TiN, Ti, TiAlN, TiSiN, TiW 또는 TaW 중 어느 하나를 이용하며, 알루미늄(35a) 식각은 반응성이온식각법(Reactive Ion Etching; RIE)으로 이루어진다.Subsequently, after forming the metal contact 34 embedded in the contact hole, a laminated film of aluminum 35a and the antireflection film 35b is formed on the interlayer insulating film 33, and the antireflection film 35b and the aluminum 35a are formed. ) Is sequentially etched to form a first aluminum wiring (100). Here, the anti-reflection film 35b is a film for preventing the attack of aluminum, using any one of TiN, Ti, TiAlN, TiSiN, TiW or TaW, the aluminum 35a etching is reactive ion etching (Reactive Ion Etching) ; RIE).
계속해서, 제 1 알루미늄배선을 포함한 전면에 제 1 금속간절연막(36), 식각정지막(37), 제 2 금속간절연막(38)을 순차적으로 형성한 후, 제 2 금속간절연막 (38), 식각정지막(37), 제 1 금속간절연막(36)을 선택적으로 식각하여 제1 알루미늄배선의 표면을 노출시키는 비아홀을 형성한다(101). 여기서, 비아홀을 형성하기 위한 공정은 먼저 제2 금속간절연막(38)상에 감광막을 도포하고 노광 및 현상으로 패터닝하여 비아홀 마스크를 형성한 후, 비아홀 마스크를 이용하여 제2 금속간절연막(38), 식각정지막(37), 제1 금속간절연막(36)을 식각하므로써 이루어지며, 비아홀 마스크는 비아홀 형성후 제거된다.Subsequently, the first intermetallic insulating film 36, the etch stop film 37, and the second intermetallic insulating film 38 are sequentially formed on the entire surface including the first aluminum wiring, and then the second intermetallic insulating film 38 is formed. The etching stop layer 37 and the first intermetallic insulating layer 36 are selectively etched to form via holes exposing the surface of the first aluminum interconnection (101). Here, in the process for forming the via hole, first, a photoresist film is applied on the second intermetallic insulating film 38 and patterned by exposure and development to form a via hole mask, and then the second intermetallic insulating film 38 using the via hole mask. The etching stop film 37 and the first intermetallic insulating film 36 are etched, and the via hole mask is removed after the via hole is formed.
상술한 비아홀 형성시, 반사방지막(35b)과의 선택비를 확보하기 위하여 ICP 식각장치에서 50W∼200W의 바이어스 파워와 20mtorr∼100mtorr의 압력하에서 C4F8/Ar/O2계 가스로 식각하고, 이로써 TiN 대 산화막의 선택비를 15;1 이상 확보한다. 이 때, C4F8대 O2의 가스비를 2:1∼1:1로 하며, 후속 플루오르카본계 폴리머를 용이하게 제거하기 위해 비아홀 형성시 온도를 20℃∼100℃로 한다.When forming the above-mentioned via hole, in order to secure the selectivity with the anti-reflection film 35b, the ICP etching apparatus is etched with C 4 F 8 / Ar / O 2 based gas under a bias power of 50 W to 200 W and a pressure of 20 mtorr to 100 mtorr. This ensures a selectivity of TiN to oxide film of 15: 1 or more. At this time, the gas ratio of C 4 F 8 to O 2 is 2: 1 to 1: 1, and the temperature at the time of via hole formation is 20 ° C. to 100 ° C. in order to easily remove the subsequent fluorocarbon polymer.
또한, ICP 식각장치에서 50W∼700W의 바이어스 파워와 20mtorr∼100mtorr의 압력하에서 Ar 가스 단독으로 이루어지되, ICP 식각장치의 전극의 온도를 40℃∼100℃로 유지한다.In the ICP etching apparatus, Ar gas alone is used under a bias power of 50 W to 700 W and a pressure of 20 mtorr to 100 mtorr, but the temperature of the electrode of the ICP etching apparatus is maintained at 40 ° C to 100 ° C.
다음으로, 비아홀 형성후 발생된 금속성 폴리머(B)를 제거하기 위한 세정을 실시하는데, 세정 용액으로 희석된 질산(Diluted nitric acid)을 이용한다(102).Next, the cleaning is performed to remove the metallic polymer (B) generated after the via hole formation, using dilute nitric acid diluted with the cleaning solution (102).
이와 같이 플루오르카본계 금속성 폴리머를 제거하기 위해 희석된 질산을 이용하면, 희석된 질산과 금속성 폴리머의 반응으로 인해 CO, CO2, COF 등의 휘발성 부산물이 생성되므로써 폴리머를 제거할 수 있다.As such, when dilute nitric acid is used to remove the fluorocarbon-based metallic polymer, the reaction of the diluted nitric acid with the metallic polymer generates volatile by-products such as CO, CO 2 , and COF, thereby removing the polymer.
이어서, 후속 공정으로 종래와 동일하게, 트렌치를 형성한 후(103), 트렌치 및 비아홀에 매립되는 제2 알루미늄배선(39b)과 비아(39a)를 형성한다(104).Subsequently, after the trench is formed 103 in the subsequent process, the second aluminum wiring 39b and the via 39a, which are embedded in the trench and the via hole, are formed 104.
여기서, 트렌치를 형성하는 공정은, 폴리머 제거후, 전면에 감광막을 도포하고 노광 및 현상으로 패터닝하여 비아홀 마스크보다 큰 선폭을 갖는 트렌치 마스크를 형성하고, 식각정지막(37)에서 식각이 멈추도록 트렌치 마스크를 이용하여 제2 금속간절연막(38)을 식각하므로써 비아홀 상부에 트렌치를 형성한다.Here, in the process of forming the trench, after removing the polymer, a photoresist film is applied to the entire surface and patterned by exposure and development to form a trench mask having a line width larger than that of the via hole mask, and the etching stops at the etch stop layer 37. A trench is formed on the via hole by etching the second intermetallic insulating layer 38 using a mask.
그리고, 제2 알루미늄배선과 비아 형성 방법은 트렌치가 형성된 제2 금속간절연막(38)상에 알루미늄을 증착한 후, 화학적기계적연마하므로써 이루어진다.The second aluminum wiring and via formation method is performed by depositing aluminum on the second intermetallic insulating film 38 having trenches, followed by chemical mechanical polishing.
한편, 제1,2 금속간절연막(36, 38)은 산화막을 이용하며, 식각정지막(37)은 질화막을 이용한다.Meanwhile, the first and second intermetallic insulating layers 36 and 38 use oxide films, and the etch stop film 37 uses nitride films.
본 발명의 일실시예에서는 희석된 질산을 이용하였으나, 기화된 질산을 이용할 수 있으며, 이 경우 기화된 질산을 운반하기 위한 운반가스로 H2O, He, Ne 를 사용한다.In one embodiment of the present invention, diluted nitric acid is used, but vaporized nitric acid may be used. In this case, H 2 O, He, Ne is used as a carrier gas for transporting vaporized nitric acid.
도 4는 본 발명의 다른 실시예에 따른 듀얼다마신 공정에 의한 비아 형성 방법을 도시한 공정 흐름도로서, 도 3에 도시된 일실시예와 제1 알루미늄배선 형성(110), 비아홀 형성(111), 트렌치 형성(113), 제2 알루미늄배선 형성(114)은 동일하다.FIG. 4 is a process flow diagram illustrating a via formation method using a dual damascene process according to another embodiment of the present invention. The embodiment shown in FIG. 3 and the first aluminum wiring formation 110 and the via hole formation 111 are shown in FIG. The trench formation 113 and the second aluminum wiring formation 114 are the same.
다만, 비아홀 형성후 생성된 금속성 폴리머를 제거하기 위한 세정(112)은 산화막 에처(Oxide ethcer)에서 후식각처리(Post Etch Treatment; PET)를 실시하되, 20mtorr∼100mtorr의 압력에서 Ar, Ar/O2또는 Ar/NH3가스를 이용하여 후식각처리를 실시한다.However, the cleaning 112 for removing the metallic polymer formed after the via hole formation is performed by post etching treatment (PET) in an oxide ethcer, but Ar, Ar / O at a pressure of 20 mtorr to 100 mtorr. Post etching is performed using 2 or Ar / NH 3 gas.
본 발명은 제1알루미늄배선을 반응성이온식각한 후, 제2알루미늄배선과 비아를 듀얼다마신공정에 의해 형성하였으나, 다른 방법으로 제1알루미늄배선을 싱글다마신공정(single damascene process)에 의해 형성한 후, 제2알루미늄배선과 비아를 듀얼다마신공정에 의해 형성할 수 있다.In the present invention, the first aluminum wiring is formed by the dual ion damascene process after the reactive ion etching, and the second aluminum wiring and the via are formed by the dual damascene process, but after the first aluminum wiring is formed by the single damascene process. The second aluminum wirings and vias can be formed by a dual damascene process.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명은 희석된 질산이나 기화된 질산을 이용하여 비아홀 형성후 생성된 폴리머를 효과적으로 제거하므로써 비아의 저항을 감소시킬 수 있는 효과가 있으며, 듀얼다마신 공정을 이용함에 따라 공정 단순화 및 비용 절감차원에서 매우 유용한 알루미늄 듀얼다마신 공정을 안정적으로 구현가능한 효과가 있다.As described above, the present invention has the effect of effectively reducing the resistance of vias by effectively removing the polymer formed after via hole formation using dilute nitric acid or vaporized nitric acid, and simplifying the process by using the dual damascene process. It is possible to stably implement the aluminum dual damascene process, which is very useful for cost reduction.
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