KR20030000672A - Method for forming a metal wiring - Google Patents

Method for forming a metal wiring Download PDF

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Publication number
KR20030000672A
KR20030000672A KR1020010036736A KR20010036736A KR20030000672A KR 20030000672 A KR20030000672 A KR 20030000672A KR 1020010036736 A KR1020010036736 A KR 1020010036736A KR 20010036736 A KR20010036736 A KR 20010036736A KR 20030000672 A KR20030000672 A KR 20030000672A
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South Korea
Prior art keywords
layer
polishing
diffusion barrier
metal layer
contact hole
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KR1020010036736A
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Korean (ko)
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권병호
이세영
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주식회사 하이닉스반도체
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Priority to KR1020010036736A priority Critical patent/KR20030000672A/en
Publication of KR20030000672A publication Critical patent/KR20030000672A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

PURPOSE: A method for fabricating a metal interconnection is provided to obtain good polishing uniformity by twice performing a chemical mechanical polishing(CMP) process on a metal layer, and to improve the characteristic of the metal interconnection by minimizing the loss of a tungsten plug and an oxide layer. CONSTITUTION: An insulation layer having a contact hole(210) is formed on a semiconductor substrate. A diffusion barrier layer(220) is formed on the insulation layer including the contact hole. The first metal layer(230) is formed on the diffusion barrier layer to completely fill the inside of the contact hole. The first metal layer is firstly polished to expose the diffusion barrier layer at a high polishing pressure by using slurry including abrasive. The remaining metal layer and the exposed diffusion barrier layer are eliminated by using H2O2 so that the resultant structure becomes the same plane as the insulation layer. The second metal layer(240) is formed on the resultant structure.

Description

금속 배선 형성 방법{Method for forming a metal wiring}Method for forming a metal wiring

본 발명은 금속 배선 형성 방법에 관한 것으로, 특히 0.35um 기술 미만의 반도체 소자의 금속 배선을 형성할 때 콘택 플러그의 CMP 공정에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings, and more particularly, to a CMP process for contact plugs when forming metal wirings for semiconductor devices of less than 0.35 um technology.

반도체 집적 회로의 집적도가 증가함에 따라 금속 배선의 폭이 줄어들고 콘택홀에서는 아스펙트비(aspect ratio)가 계속 증가하고 있다. 이에 따라, 현재 금속 배선의 재료로 사용되고 있는 알루미늄 합금과 같은 금속막은 콘택홀 내에서의 단차 도포성(step coverage)이 불량하거나 보이드(void)와 같은 결함이 발생하게 된다. 그 결과, 금속 배선들 간의 단선 등이 유발되어 집적 회로의 신뢰성이 저하된다.As the degree of integration of semiconductor integrated circuits increases, the width of metal wires decreases, and the aspect ratio of contact holes continues to increase. Accordingly, a metal film such as an aluminum alloy, which is currently used as a material for metal wiring, may have poor step coverage in the contact hole or defects such as voids. As a result, disconnection or the like between the metal wires is caused, thereby lowering the reliability of the integrated circuit.

그러므로, 반도체 소자에서는 금속 배선과 하부 실리콘 기판의 접합 영역을 전기적으로 연결시키기 위하여 콘택 플러그를 형성한 후 그 상부에 금속 배선을 형성한다.Therefore, in the semiconductor device, a contact plug is formed to electrically connect the junction region of the metal wiring and the lower silicon substrate, and then the metal wiring is formed thereon.

종래의 금속 배선 형성 방식을 도 1a 내지 1b를 참조로 간단히 설명한다. 먼저 도 1a를 참조하면, 반도체 기판의 콘택홀(110)을 포함하는 절연막(100) 상부에 확산 방지막(120)을 형성한다. 그 후에 콘택홀(110) 내부를 완전히 채우도록 제1 금속층(130)을 형성한다. 그런 다음, 도 1b에 도시된 바와 같이 이 금속층(130)을 CMP 공정으로 평탄화시킨 후 제2 금속층을 형성한다. 도 1b에서 볼 수 있는 바와 같이, 종래의 방식을 이용한 제1 금속층의 CMP 공정후에는 산화막 손상(도 1b의 "A") 또는 플러그 리세스(도 1b의 "B")와 같은 결함이 발생할 수 있다.A conventional metal wiring formation method will be briefly described with reference to FIGS. 1A to 1B. First, referring to FIG. 1A, a diffusion barrier layer 120 is formed on an insulating layer 100 including a contact hole 110 of a semiconductor substrate. Thereafter, the first metal layer 130 is formed to completely fill the inside of the contact hole 110. Next, as shown in FIG. 1B, the metal layer 130 is planarized by a CMP process to form a second metal layer. As can be seen in FIG. 1B, defects such as oxide damage (“A” in FIG. 1B) or plug recesses (“B” in FIG. 1B) may occur after the CMP process of the first metal layer using a conventional method. have.

이와 같이 종래의 금속 배선 CMP 공정시에는, 금속 배선층의 균일성, 텅스텐 플러그의 리세스(recess)와 산화막 손실(loss), 스크래치(scratch)등이 발생할 수 있다. 이중, 금속 배선층의 균일성은 장비의 문제와 직결되며, 일반적으로 연마 압력을 높이면 연마 속도가 올라가고 연마 균일도도 좋아지는 특성이 있다. 그러나, 이처럼 연마 압력을 높이면 텅스텐 플러그의 리세스, 산화막 손실 및 스크래치 등의 문제가 유발된다. 예를 들어 7psi의 연마 압력으로 연마할 때 웨이퍼의 균일성이 좋더라도 실제 디바이스를 연마할 때에는 연마 초기부터 끝까지 5psi 정도의 연마 압력을 적용하여 CMP를 진행하는 경우가 대부분이다. 또한, 균일성, 텅스텐 플러그 리세스, 산화막 손실 및 스크래치 등의 문제는 연마 압력 등의 연마 조건에 의해서도 크게 좌우되지만, 사용하는 슬러리에 의해서도 좌우된다. 특히 슬러리에 포함된 연마재(abrasive)에 따라 그 특성이 크게 달라진다. 또한, 연마 후에 텅스텐 잔류물이 남게 되는 경우에는 후속 공정에서 배선층을 형성할 때 브리지(bridge) 소스가 되는 문제가 발생한다. 그러므로 콘택 플러그를 형성할 때 CMP의 정도를 적당하게 조정하는 것이 양호한 금속 배선을 형성하는 데에 매우 중요하다.As described above, in the conventional metal wiring CMP process, uniformity of the metal wiring layer, recesses of the tungsten plug, loss of oxide film, scratches, and the like may occur. Of these, the uniformity of the metal wiring layer is directly connected to the problem of equipment, and in general, the higher the polishing pressure, the higher the polishing rate and the better the polishing uniformity. However, such an increase in polishing pressure causes problems such as tungsten plug recess, oxide film loss and scratching. For example, even if the wafer uniformity is good when polishing at a polishing pressure of 7 psi, in most cases, CMP is performed by applying a polishing pressure of about 5 psi from the beginning to the end when polishing the actual device. In addition, problems such as uniformity, tungsten plug recess, oxide film loss, and scratches also depend greatly on polishing conditions such as polishing pressure, but also on the slurry used. In particular, the properties vary greatly depending on the abrasive contained in the slurry. In addition, when tungsten residues remain after polishing, there is a problem of becoming a bridge source when forming a wiring layer in a subsequent process. Therefore, appropriately adjusting the degree of CMP when forming a contact plug is very important for forming good metal wiring.

상기의 문제점을 극복하기 위하여, 본 발명의 목적은, 반도체 소자의 금속 배선을 형성할 때, 2단계의 CMP 공정을 사용하여 텅스텐 플러그의 손실을 최소화하고 후속 금속 배선층 형성을 위한 금속 물질의 증착을 용이하게 하는 데 있다.In order to overcome the above problems, it is an object of the present invention to minimize the loss of tungsten plugs and to deposit metal materials for subsequent metallization layer formation using a two-step CMP process when forming metallization of semiconductor devices. To facilitate it.

도 1a 내지 1b는 종래의 금속 배선 형성 방법에서 금속층의 CMP 공정을 순차적으로 나타낸 단면도.1A to 1B are cross-sectional views sequentially illustrating a CMP process of a metal layer in a conventional metal wiring forming method.

도 2a 내지 2c는 본 발명의 금속 배선 형성 방법에서 금속층의 CMP 공정을 순차적으로 나타낸 단면도.2a to 2c are cross-sectional views sequentially showing the CMP process of the metal layer in the metal wiring forming method of the present invention.

도 3은 모터 전류 방식의 EPD 시스템에서 검출되는 신호도.3 is a signal diagram detected in an EPD system of a motor current method.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

100, 200: 산화막110, 210: 콘택홀100, 200: oxide film 110, 210: contact hole

120, 220: 확산 방지막130, 230: 제1 금속층120, 220: diffusion barrier 130, 230: first metal layer

240: 제2 금속층240: second metal layer

상기의 목적을 달성하기 위하여, 본 발명의 금속 배선 형성 방법은, 반도체 기판상에 콘택홀을 갖는 절연막을 형성하는 단계; 상기 콘택홀을 포함하여 상기 절연막 상에 확산 방지막을 형성하는 단계; 상기 콘택홀의 내부를 완전히 채우도록 상기 확산 방지막상에 제1 금속층을 형성하는 단계; 연마재가 포함된 슬러리를 사용하여 높은 연마 압력하에서 상기 확산 방지막을 노출시키도록 상기 금속층을 1단계 연마하는 단계; H2O2를 사용하여 잔여 제1 금속층과 상기 노출된 확산 방지층을 제거하여 상기 절연막과 동일 평면이 되도록 2단계 연마하는 단계; 및 상기 전체 구조 상부에 제2 금속층을 형성하는 단계를 포함하여 이루어진다.In order to achieve the above object, the metal wiring forming method of the present invention comprises the steps of forming an insulating film having a contact hole on the semiconductor substrate; Forming a diffusion barrier on the insulating layer including the contact hole; Forming a first metal layer on the diffusion barrier to completely fill the inside of the contact hole; Polishing the metal layer in one step using a slurry containing an abrasive to expose the diffusion barrier under high polishing pressure; Removing the remaining first metal layer and the exposed diffusion barrier layer using H 2 O 2 and performing two-step polishing to be coplanar with the insulating film; And forming a second metal layer on the entire structure.

이제 도 2a 내지 2c를 참조로 본 발명의 일실시예를 상세히 설명한다.An embodiment of the present invention will now be described in detail with reference to FIGS. 2A-2C.

먼저 도 2a를 참조하면, 반도체 기판상에 콘택홀(210)을 갖는 절연막(200)이 형성된다. 콘택홀(210)을 포함하여 절연막(200) 상부에 확산 방지막(220)을 형성한다. 이 확산 방지막(220)은 바람직하게는 Ti/TiN막을 사용한다. 확산 방지막(220) 상에 콘택홀을 완전히 채우도록 제1 금속층(230)을 형성한다. 제1 금속층으로는 텅스텐층을 사용하는 것이 바람직하다.First, referring to FIG. 2A, an insulating film 200 having contact holes 210 is formed on a semiconductor substrate. The diffusion barrier layer 220 is formed on the insulating layer 200 including the contact hole 210. The diffusion barrier film 220 preferably uses a Ti / TiN film. The first metal layer 230 is formed on the diffusion barrier layer 220 to completely fill the contact hole. It is preferable to use a tungsten layer as the first metal layer.

도 2b를 참조하면, 높은 연마 압력에서 연마재를 포함한 슬러리를 사용하여 1단계 연마를 수행한다. 높은 연마 압력에서 연마를 진행하는 경우, 웨이퍼 레벨에서 매우 균일한 연마를 진행할 수 있다. 1단계 연마를 멈추는 시점은 텅스텐이다 연마되고 확산 방지막이 연마되기 시작하는 시점이다. 이러한 시점은 EPD(EndPoint Detection) 시스템을 사용하여 알 수 있다(도 3에 도시되어 있음). 이러한 EDP 시스템은 모터 전류 방식과 레이저 방식의 2가지 방식을 사용한다. 이 2가지 방식에 따라 신호의 모양은 다르지만, 모든 방식에서 텅스텐 제거 시기, 확산 방지막의 제거 시기 등이 구분될 수 있다. 이처럼 EPD 시스템을 사용하여 확산 방지막이 드러나는 시점을 알 수 있으며, 이 시점에서 1단계 연마를 멈추고 2단계 연마를 시작한다. 즉 이렇게 1단계 연마가 끝난 시점에서 웨이퍼의 표면은 일부 확산 방지막이 드러나고 일부에는 텅스텐이 남아 있는 상태가 된다.Referring to FIG. 2B, one-step polishing is performed using a slurry including an abrasive at a high polishing pressure. When polishing is performed at high polishing pressures, very uniform polishing can be performed at the wafer level. The stop point of the first stage polishing is tungsten. The polishing stops and the diffusion barrier starts to polish. This time point can be known using an Endpoint Detection (EPD) system (shown in FIG. 3). The EDP system uses two methods, a motor current method and a laser method. Although the shape of the signal is different according to the two methods, the tungsten removal time and the diffusion barrier film removal time can be distinguished in all methods. The EPD system can be used to know when the diffusion barrier is exposed, at which point the first step stops polishing and the second step starts polishing. In other words, at the end of the one-step polishing, some of the diffusion barrier layer is exposed on the surface of the wafer and some of the tungsten remains.

도 2c를 참조하면, H2O2를 사용하여 2단계 연마를 진행하여 잔여 텅스텐을 제거하고 표면을 평탄화시킨다. H2O2를 사용하면 연마 속도가 약 1000Å/min으로 비교적 낮지만, 연마재가 없기 때문에 연마재에 의한 플러그 리세스, 산화물 손실 및 스크래치 등을 최소화시킬 수 있다.Referring to FIG. 2C, two-step polishing is performed using H 2 O 2 to remove residual tungsten and planarize the surface. When H 2 O 2 is used, the polishing rate is relatively low at about 1000 mW / min, but since there is no abrasive, plug recess, oxide loss and scratches caused by the abrasive can be minimized.

도 2d를 참조하면, 2단계의 연마를 진행한 후 텅스텐 플러그가 형성된 전체 구조 상부에 금속층(240)을 형성한다.Referring to FIG. 2D, the metal layer 240 is formed on the entire structure of the tungsten plug after the two-step polishing is performed.

상기 설명한 바와 같이, 본 발명에 따르면, 금속 배선 형성시에 금속층을 CMP 할 때 2단계의 CMP를 사용하여 양호한 연마 균일도를 얻을 수 있고, 텅스텐 플러그 및 산화막의 손실을 최소화함으로써, 후속 금속 배선의 특성을 향상시킬 수있다. 또한, 상대적으로 저렴한 H2O2를 연마재로 사용함으로써 공정 단가를 감소시킬 수 있다는 이점이 있다.As described above, according to the present invention, when polishing the metal layer at the time of forming the metal wiring, it is possible to obtain good polishing uniformity by using two-step CMP, and to minimize the loss of the tungsten plug and the oxide film, thereby the characteristics of the subsequent metal wiring Can improve. In addition, there is an advantage that the process cost can be reduced by using relatively inexpensive H 2 O 2 as the abrasive.

Claims (7)

반도체 기판상에 콘택홀을 갖는 절연막을 형성하는 단계;Forming an insulating film having a contact hole on the semiconductor substrate; 상기 콘택홀을 포함하여 상기 절연막 상에 확산 방지막을 형성하는 단계;Forming a diffusion barrier on the insulating layer including the contact hole; 상기 콘택홀의 내부를 완전히 채우도록 상기 확산 방지막상에 제1 금속층을 형성하는 단계;Forming a first metal layer on the diffusion barrier to completely fill the inside of the contact hole; 연마재가 포함된 슬러리를 사용하여 높은 연마 압력하에서 상기 확산 방지막을 노출시키도록 상기 금속층을 1단계 연마하는 단계;Polishing the metal layer in one step using a slurry containing an abrasive to expose the diffusion barrier under high polishing pressure; H2O2를 사용하여 잔여 금속층과 상기 노출된 확산 방지층을 제거하여 상기 절연막과 동일 평면이 되도록 2단계 연마하는 단계; 및Removing the residual metal layer and the exposed diffusion barrier layer using H 2 O 2 and performing two-step polishing to be coplanar with the insulating film; And 상기 전체 구조 상부에 제2 금속층을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 금속 배선 형성 방법.And forming a second metal layer over the entire structure. 제1항에 있어서, 상기 1단계 연마시에 5psi 내지 8psi의 압력을 사용하여 상기 금속층의 연마를 진행하는 것을 특징으로 하는 금속 배선 형성 방법.The method of claim 1, wherein the polishing of the metal layer is performed using a pressure of 5 psi to 8 psi during the first stage polishing. 제1항에 있어서, 상기 2단계 연마시에 2psi 내지 4psi의 압력에서 H2O2를 사용하여 연마재 없이 연마를 진행하는 것을 특징으로 하는 금속 배선 형성 방법.The method of claim 1, wherein the polishing is performed without abrasive using H 2 O 2 at a pressure of 2 psi to 4 psi during the two-step polishing. 제1항에 있어서, 상기 제1 금속층으로 텅스텐층을 사용하는 것을 특징으로 하는 금속 배선 형성 방법.The method of claim 1, wherein a tungsten layer is used as the first metal layer. 제1항에 있어서, 상기 확산 방지층으로 Ti/TiN 층을 사용하는 것을 특징으로 하는 금속 배선 형성 방법.2. The method of claim 1, wherein a Ti / TiN layer is used as the diffusion barrier layer. 제1항에 있어서, 상기 1단계 연마를 멈추는 시점은 EPD 시스템을 사용하여 산출하는 것을 특징으로 하는 금속 배선 형성 방법.2. The method of claim 1, wherein the time point at which the first step of polishing is stopped is calculated using an EPD system. 제1항에 있어서, 상기 H2O2를 사용하는 2단계 연마는 1000Å/min의 속도로 진행되는 것을 특징으로 하는 금속 배선 형성 방법.The method of claim 1, wherein the two-step polishing using H 2 O 2 is performed at a speed of 1000 kW / min.
KR1020010036736A 2001-06-26 2001-06-26 Method for forming a metal wiring KR20030000672A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100703509B1 (en) * 2005-01-11 2007-04-03 삼성전자주식회사 Sliding type portable telephone with game function
KR100708607B1 (en) * 2006-01-03 2007-04-18 삼성전자주식회사 Mobile communication terminal having both keypad
KR100733262B1 (en) * 2005-12-29 2007-06-27 동부일렉트로닉스 주식회사 Method for manufacturing conductive plugs
KR100843971B1 (en) * 2007-08-08 2008-07-03 주식회사 동부하이텍 Method of manufacturing metal line

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100703509B1 (en) * 2005-01-11 2007-04-03 삼성전자주식회사 Sliding type portable telephone with game function
KR100733262B1 (en) * 2005-12-29 2007-06-27 동부일렉트로닉스 주식회사 Method for manufacturing conductive plugs
KR100708607B1 (en) * 2006-01-03 2007-04-18 삼성전자주식회사 Mobile communication terminal having both keypad
KR100843971B1 (en) * 2007-08-08 2008-07-03 주식회사 동부하이텍 Method of manufacturing metal line

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