KR20030000126A - High voltage generator of semiconductor memory device - Google Patents

Abstract

PURPOSE: An apparatus for generating a high voltage in a semiconductor memory device is provided to improve driving capacity of a pump circuit by operating selectively a dual mode pump in a standby/active mode. CONSTITUTION: A voltage level detection portion(110) is formed with a standby mode voltage level detector(112) and an active mode voltage level detector(114) which are arranged on a center region of a chip. An oscillator portion(120) is formed with the first active mode oscillator(122) arranged on an upper region of the chip and a standby mode oscillator(124) and the second active mode oscillator(126) arranged on the center region of the chip, and the third active mode oscillator(128) arranged on a lower region of the chip. A pump circuit portion(140) is formed with an active mode pump circuit(142) arranged on the upper region of the chip, a dual mode pump circuit(144) arranged on the center region of the chip, and an active mode pump circuit(146) arranged on the lower region of the chip.

Description

High voltage generator of semiconductor memory device

The present invention relates to a high voltage generator of a semiconductor memory device, and more particularly, to a high voltage generator of a semiconductor memory device configured to simplify the high voltage generator using a dual mode pump circuit.

As the density of DRAMs improves and the capacity of cells mounted on one chip increases, current consumption also increases. In order to cope with this, the driving capability of the high voltage generator must be gradually increased, which increases the area of the chip peripheral circuit because it increases the pump capacitor area. This reduces net die and lowers productivity.

Currently, there are two types of DRAM high voltage (Vpp) generators. One is a standby high voltage generator used for initial power-up and precharge, and the other is a word line active. Active high voltage generator).

FIG. 1 is a block diagram showing a high voltage generator of a conventional semiconductor memory device, and includes a voltage level detector 10, an oscillator 20, and a pump circuit 30.

Here, the voltage level detecting unit 10 includes one standby mode voltage level detector 14 and three active mode voltage level detectors 12, 16, and 18, and the oscillator unit 20 includes one standby mode oscillator ( 24) and three active mode oscillators 22, 26, and 28, and the pump circuit unit 30 includes one standby mode pump circuit 34 and three active mode pump circuits 32, 36, and 38. do.

Usually, in order to smoothly supply high voltage (Vpp) to the entire chip, the active mode pump circuits 32 and 38 are arranged at the top and the bottom of the chip, respectively, and the standby mode pump circuit 34 is arranged in the center region. And one active mode pump circuit 36 are arranged, respectively. The number and placement of these pump circuits may vary depending on the characteristics of the chip.

Here, assuming that the area of each active / standby mode pump circuit is 1, the total area occupied by the active mode pump circuits 32, 36, and 38 is three. The standby mode pump circuit 34 usually has a value smaller than the area 1 because the current consumption is smaller than that of the active mode pump circuits 32, 36, 38. However, it is assumed here that 1 is the same as active.

Therefore, when the standby mode and the active mode work together in the actual active operation, the standby mode pump circuit affects only about 1/4, that is, about 25% of the total driving capability.

Further, assuming that the period of the standby mode pump circuit 34 is β times longer than the active mode pump circuits 32, 36, 38, the influence is reduced to 1 / β. Therefore, the standby mode pump circuit 34 does not significantly affect the driving capability in the active mode for the above reason.

Accordingly, an object of the present invention for solving such a problem is to improve the driving capability of the pump circuit by selectively operating the dual mode pump circuit in the standby / active mode.

Still another object of the present invention is to reduce the area of the peripheral circuit by simplifying the circuit of the high voltage generator using the dual mode pump circuit.

1 is a block diagram of a high voltage generator of a conventional semiconductor memory device.

2 is a block diagram of a high voltage generator of a semiconductor memory device according to a preferred embodiment of the present invention.

3 is a circuit diagram of the pump control unit of FIG.

4 is a circuit diagram of the dual mode pump circuit of FIG.

5 is a timing diagram of main signals of the dual mode pump circuit of FIG. 4;

A dual mode voltage level detecting device according to the present invention for achieving the above object comprises: a voltage level detecting unit for detecting and outputting a level of a voltage to be detected; An oscillator unit for receiving an output signal of the voltage level detector and generating a standby oscillation signal and an active oscillation signal; A pump controller configured to selectively output the standby oscillation signal and the active generation signal in response to an active signal; And a pump circuit unit which switches to an active mode only during an active operation in response to an output signal of the pump control unit.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 2 is a block diagram of a high voltage generator according to a preferred embodiment of the present invention, and includes a voltage level detecting unit 110, an oscillator unit 120, a pump control unit 130, and a pump circuit unit 140.

Here, the voltage level detector 110 includes one standby mode voltage level detector 112 and one active mode voltage level detector 114 disposed only in the center region of the chip.

The oscillator unit 120 has one active mode oscillator 122 disposed in the upper region of the chip, one standby mode oscillator 124 and one active mode oscillator 126 disposed in the center region of the chip as in the related art. ) And one active mode oscillator 128 disposed in the lower region of the chip.

Next, the pump circuit unit 140 includes one active mode pump circuit 142 disposed in the upper region of the chip, the dual mode pump circuit 144 disposed in the central region of the chip, and one single region disposed in the lower region of the chip. It consists of an active mode pump circuit 146.

Here, the dual mode pump circuit 144 integrates the pump circuits used differently in the standby mode and the active mode into one to implement both the standby and active modes.

The pump capacitor size of the dual mode pump circuit is the same as a conventional standby mode pump circuit. In the present invention, it is assumed that the pump capacitor size of the dual mode pump circuit is equal to the pump capacitor size of the active mode pump circuit.

The operation of the high voltage generator shown in FIG. 2 will be briefly described below.

First, in the standby operation, the standby mode voltage level detector 112 operates, and the standby oscillation signal STN_OSC having a period β times longer than the pulse period of the active mode generated by the standby mode oscillator 124 receives the pump control unit 130. ) To operate the dual mode pump circuit 144.

Next, during the active operation, the active mode voltage level detector 114 operates, and an active oscillation signal ACT_OSC having one cycle generated by the active mode oscillator 126 is input to the pump control unit 130, thereby providing a dual mode pump. The circuit 144 is operated.

FIG. 3 is a circuit diagram of the pump controller 130. The transfer gate T1 receives and transmits a standby oscillation signal STN_OSC, an active signal ACT, and an output signal of an inverter I1 inverting the active signal ACT. ) And a transfer gate T2 that receives and transmits an active oscillation signal STN_OSC, an active signal ACT, and an output signal of the inverter I1 that inverts the active signal ACT.

The pump controller 130 bypasses the standby oscillation signal STN_OSC output from the standby mode oscillator 124 when the active signal ACT is at a low level, and the active mode oscillator when the active signal ACT is at a high level. Bypass the active oscillation signal (ACT_OSC) output at (126).

That is, when the high level active signal ACT is input to the active mode voltage level detector 114, the active oscillation signal ACT_OSC having one cycle generated by the active mode oscillator 126 is input to the pump controller 130. do. At this time, since the active signal ACT is at a high level, the standby oscillation signal STN_OSC output from the standby mode oscillator 124 is blocked. Accordingly, since only the active oscillation signal ACT_OSC having one cycle is input to the dual mode pump circuit 144, the number of operations of the dual mode pump circuit 144 increases, thereby increasing the standby mode pump having the actual β cycle. The driving capability is improved over the circuit.

In summary, the dual mode pump circuit 144 according to the present invention operates in the normal operation in the standby operation in response to the output signal of the pump control unit 130, and in the active operation is switched to the active mode to operate the drive capability Will be improved.

4 is a circuit diagram of the dual mode pump circuit 144, and FIG. 5 is a timing diagram of main signals P1, P2, G1, and G2 of the dual mode pump circuit 144. As shown in FIG.

The dual mode pump circuit 144 is connected to a node P1BOOT and receives an NMOS capacitor C1 receiving a pump control signal P1, and an NMOS capacitor C2 connected to a node P2BOOT and receiving a pump control signal P2. NMOS capacitor C3 connected to node G1BOOT to receive pump control signal G1, NMOS capacitor C4 connected to node G2BOOT to receive pump control signal G2, and the source and bulk have high voltage (Vpp). PMOS transistor P1 connected to the node P2BOOT, the source and the bulk connected to the high voltage Vpp, the PMOS transistor P2 connected to the node P1BOOT, and the node P1BOOT connected to the node P2BOOT, and the power supply voltage Vdd. NMOS transistor N1 connected between node G1BOOT and a gate connected to node G1BOOT, NMOS transistor N2 connected between node P2BOOT and power supply voltage Vdd and gate connected to node G2BOOT, and node G1BOOT and power supply voltage. (Vdd) is connected between the gate The NMOS transistor N3 connected to the source voltage Vdd, the NMOS transistor N4 connected between the node G2BOOT and the power supply voltage Vdd, and the gate connected to the power supply voltage Vdd, and the node G1BOOT and the power supply voltage. NMOS transistor N5 connected between Vdd and a gate connected to power supply voltage Vdd, and an NMOS transistor N6 connected between a node G2BOOT and power supply voltage Vdd and connected to a power supply voltage Vdd. It is composed of

The dual mode pump circuit 144 configured as described above operates to generate the high voltage Vpp by receiving the pump signals P1 and P2 and the precharge signals G1 and G2 output from the pump controller 130. .

Hereinafter, the operation of the pump circuit will be described in more detail.

First, when the pump signal P1 is enabled at the high level, the node P1BOOT is charged up by the NMOS capacitor C1 and rises from the power supply voltage Vdd to twice the power supply voltage 2Vdd.

At this time, since the pump signal P2 is low level and the precharge signal G2 is high level, the NMOS transistor N2 is turned on by the node G2BOOT to precharge the node P2BOOT to the power supply voltage Vdd level. do.

Since the node P2BOOT precharged with the power supply voltage Vdd is connected to the gate of the PMOS transistor P1, the node P2BOOT is different from the node P1BOOT having twice the power supply voltage 2Vdd by more than the threshold voltage Vt. Therefore, the PMOS transistor P1 is completely turned on to transfer twice the charge of the power supply voltage Vdd to the node of the high voltage Vpp.

Next, when the pump signal P1 becomes low level and the pump signal P2 becomes high level, the opposite phenomenon occurs, and the charge of the node P2BOOT having twice the power supply voltage 2Vdd becomes the high voltage Vpp. Will be passed to the node.

Here, the NMOS transistors N3 and N4 prevent the node G1BOOT and the node G2BOOT from rising to levels above Vdd + Vth.

The NMOS transistors N5 and N6 prevent the node G1BOOT and the node G2BOOT from falling below Vdd-Vth.

Therefore, by controlling the node G1BOOT and the node G2BOOT at a level between Vdd-Vth and Vdd + Vth at all times, the dual mode pump circuit 144 stably transitions and is insensitive to noise.

As described above, the present invention can simplify the circuit of the high voltage generator by using a dual mode pump circuit that operates as a standby mode pump circuit in the standby mode and as an active mode pump circuit in the active mode, As a result, the area of the ferry circuit can be reduced.

In addition, it is possible to improve the driving capability of the high voltage generator by using a dual mode pump circuit that operates in the normal operation during the standby operation and switches to the active mode during the active operation.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the scope of the claims You will have to look.

Claims (4)

A voltage level detector for detecting and outputting a level of a voltage to be detected; An oscillator unit for receiving an output signal of the voltage level detector and generating a standby oscillation signal and an active oscillation signal; A pump controller configured to selectively output the standby oscillation signal and the active generation signal in response to an active signal; And And a pump circuit unit which is switched to an active mode only during an active operation in response to an output signal of the pump control unit. The method of claim 1, The pump control unit, A first transfer gate configured to receive and transmit the active signal, the standby oscillation signal, and an inverted signal of the standby oscillation signal; And And a second transfer gate configured to receive and transmit the active signal, the active oscillation signal, and an inverted signal of the active oscillation signal. The method of claim 1, And the pump circuit unit has a dual mode pump circuit in a central region of a chip. The method of claim 3, wherein And the dual mode pump circuit is switched to an active mode only during an active operation in response to an output signal of the pump controller.