KR20020093962A - S-parameter microscopy for semiconductor devices - Google Patents

Abstract

Method of using bias-dependent S-parameter measurements in the form of microscopy (FIG. 5). Microscopy can be used to determine details of the internal charge and electric field structure of semiconductor devices. Like other forms of microscopy, S-parameter microscopy focuses on the pseudo "image" and provides contrast in the "image". In essence, the images are gathered in raw form as S-parameter measurements and extracted as small signal models. Through an alternative method similar to focusing, this model is used to form the charge control map 32. Focusing is provided by an algorithm for the unique determination of small signal parameters with contrast provided using the measured bias dependent activity, to determine the boundary between the electrical charge and the electric field.

Description

S-PARAMETER MICROSCOPY FOR SEMICONDUCTOR DEVICES

The ability to accurately predict the product yield of semiconductor devices, such as microwave monolithic integrated circuits (MMICs), is a valuable asset in manufacturing. Yield forecasts include better allocation of limited manufacturing resources; Identification of yield problems; And reduced manufacturing costs. In GaAs MMIC manufacturing, the drive to produce products for new markets under reduced design costs and reduced time for market cycles has increased the potential for RF performance yield issues. This risk is even worse when the limits of semiconductor device technology are reached in accordance with the current trend in which RF performance specifications are much more competitive.

Explaining the cause of poor MMIC RF yield may be an insidious problem in that this may not be clear. In particular, RF yield problems can arise as a result of unrealized defects distributed throughout the entire manufacturing process. The main mechanism that contributes to the yield loss in the MMIC manufacturing process is illustrated in FIG. 1. As shown, four from seven possible mechanisms are strongly related to RF yield loss. Unrealistic performance specifications; Design for poor manufacturing; And factors, such as process variability, reduce RF yield individually or cumulatively, increasing cycle time from design to manufacturing as well as long-term manufacturing costs.

Various methods are used for RF yield prediction. For example, statistical and experimental modeling methods are known. Statistical modeling uses device model and circuit simulation while experimental approach uses measured data. Such statistical modeling includes Monte Carlo statistical motels, correlation statistical models, boundary models, and database models. The Monte Carlo statistical model allows device model parameters to change independently of each other by Gaussian statistics, while the correlation statistical model is known to represent more realistic statistics, where the transformation is limited to correlations between model parameters. Long-term model databases are typically created for process control monitoring, but also for example M. "A product Engineering Exercise in 6-Sigma Manufacturability: Redesign of pHEMT Wideband LNA" by M. King et al. ( 1999 GaAs MANTECH Technical Digest , Pages 91-94, April 1999).

The boundary model is a set of models representing "process corner performance". Boundary models are known to be ideal for quickly evaluating the robustness of new designs against predicted process changes. To some manufacturers, such as al. As described in "GaAs Fabs Approachto Design-for-Manufacturability" by R. Garcia et al. (1999 GaAs MANTECH Technical Digest, pages 99-102, April 1999) Likewise, it is known to develop a method for directly evaluating toughness through a "process corner experiment". However, the boundary method cannot be used to determine the RF performance distribution that is fundamental to yield calculation. As such, this method is inadequate for RF yield prediction.

The long term model database is a powerful tool for MMIC process control monitoring and typically consists of a large sample of small signal equivalent circuit model extraction for a single consistent device structure, measured under a standard set of bias conditions. The database model clearly captures pure process changes through uniform sampling. Unfortunately, this model is limited to applications based on proximity around the first measurement. For example, it is problematic to precisely extend the database model to represent devices with different bias conditions and layouts. This decision is labor intensive, as described generally in "Product Engineering Practices in Six-Sigma Productivity: Redesigning pHEMT Broadband LNAs". In other circumstances, it is virtually impossible or not recommended to apply database results, for example to predict low noise or low signal results from small signal models.

Monte Carlo statistics are simple to implement RF yield simulations. However, the predictions produced by this method are relatively inaccurate and are usually used for yield analysis if they are worse. In particular, examples of inaccurate yield prediction provided by Monte Carlo and correlation statistical models are shown in FIGS. 2A and 2B, which illustrate simulated noise versus actual noise and gain statistics for 22 to 26 GHz GaAs pHEMT LNAs. . As illustrated, squares and circles represent data points simulated by correlation statistics and Monte Carlo statistical models, respectively, and ruled lines represent measured data points.

The correlation statistical model provides a better method than the Monte Carlo method, but the results from this method may also be inaccurate. Another disadvantage of the correlation statistical model is that a substantial model database is also needed to derive the correlation that relates the method to the constraints that typically require a long term model database.

As mentioned above, empirical prediction is also known to be used to predict RF yield. In this empirical prediction method, the long term RF yield of one circuit is predicted by the known process dependent RF yield characteristics of the other circuit. This method can be thought of as a yield mapping using a linear mapping transformation between critical RF performance parameters and measured device process control monitor (PCM) data. This transformation is known to be used to map PCM data into circuit performance space. Any distribution of PCM parameters is converted to a distribution of RF performance. An example of such a transformation is shown in FIG. 3 illustrating the transformation of the device PCM into the MMIC RF performance space. In order to apply a yield map design to another circuit, an offset is included to account for the differences associated with the design. Such an empirical model is known to provide accurate prediction of noise characteristics and small signal gain performance if there is power. An exemplary comparison of predicted noise shape performance and measured noise shape performance for a 35 GHz GaAs pHEMT LNA is shown in FIG. 4, where the predicted data is shown as lines and the measured data is shown as squares.

One disadvantage of yield mapping is that it cannot be used to accurately predict RF performance before the design is created. Instead, its prediction should be refined as the design dependent offset is determined through feedback from the pre-production run.

Unfortunately, in order to accurately model the characteristics of the semiconductor device, the length of the linear conductive region; The magnitude of the saturated electric field; Phenomena associated with the internal structure of the device, such as the effective pass distance for the saturated carrier, need to be obtained. Finite element device simulation has been known to be used to calculate the internal charge / field structure of the device. Unfortunately, this device simulation is generally inaccurate and gives significantly different results than the measured device statistics. As such, there is a lack of analytical technology capable of analyzing and measuring electrical characteristics associated with internal structures of semiconductor devices in order to accurately model semiconductor devices.

Cross-References to Related Applications

This application is a continuing application of US Patent Application No. 60 / 200,307, filed April 28, 2000, which claims priority.

The present application discloses a METHOD FOR UNIQUE DETERMINATION OF FET EQUIVALENT CIRCUIT MODEL PARAMETERS, a serial number filed Oct. 5, 2000 by Roger Tsai. 09 / 680,339), co-owned co-pending patent application. The present application also discloses the following co-owned co-pending patent applications, all filed on April 28, 2000: EMBEDDING PARASITIC MODEL FOR PIFET LAYOUTS { Serial number 60 / 200,810 (agent management number 12-1116); Semi-Physical Modeling of HEMT DC-TO HIGH FREQUENCY ELECTROTHERMAL CHARACTERISTICS (serial number 60 / 200,648) number)}; SEMI-PHYSICAL MODELING OF HEMT HIGH FREQUENCY NOISE EQUIVALENT CIRCUITMODELS {Serial No. 60 / 200,290 (Attorney Management No. 12-1119)} by Roger Difference; SEMI-PHYSICAL MODELING OF HEMT HIGH FREQUENCY SMALL SIGNAL EQUIVALENT CIRCUIT MODELS (Serial Number 60 / 200,666) (Representative No. 12-1120) }; HYBRID SEMI-PHYSICAL AND DATA FITTING HEMT MODELING APPROACH FOR LARGE SIGNAL by Roger Difference and Yao Chung for Large Signal and Non-Linear Microwave / Millimeter Wave Circuit CAD AND NON-LINEAR MICROWAVE / MILLIMETER WAVE CIRCUIT CAD) (serial number 60 / 200,622 (agent representative number 12-1127)); And process variation (PM ² : PROCESS PERTURBATION TO MEASURED MODELED METHOD FOR SEMICONDUCTOR DEVICE TECHNOLOGY MODELING) (serial number 60 / 200,302) by Roger Difference. 12-1128).

Technical Field of the Invention

The present invention relates to a method of modeling semiconductor device technology, and more particularly, to a method of modeling semiconductor device technology, such as a field effect transistor (FET), in which a high electron mobility transistor (HEMT) is one type. Modeling semiconductor device technology includes fully characterizing how the device operates internally. This particular method includes using S-parameters to determine the electrical characteristics corresponding to the internal structure of the semiconductor device, such as the magnitude, state and position of the electric charge and the electric field, which allows the performance of the device to be observed. The semiconductor device technology model allows the electrical performance of any device manufactured with a particular technology to be projected only based on physically-related parameters. This capability allows the performance of circuits constructed using such devices to be predicted.

1 is a time flow diagram of a known MMIC yield loss mechanism in a manufacturing process.

2A and 2B show noise for a 26 GHz MMIC using Monte Carlo and correlation statistical device models, where measured data is shown in squares, Monte Carlo statistical data is shown in circles, and correlation statistical data is shown in ruled lines, respectively. Plot showing simulated loss versus cumulative yield for factor and gain.

3 is an exemplary representative diagram illustrating a known mapping MMIC RF yield prediction method.

4 is a diagram illustrating measured noise factor versus mapped noise factor for a 35 GHz GaAs pHEMT LNA using the method illustrated in FIG. 3.

5 illustrates an exemplary S-parameter microscope in accordance with the present invention.

6 illustrates interior and exterior regions of an exemplary HEMT device.

FIG. 7 is a view similar to FIG. 5 but illustrating an approximate location of model elements in the HEMT FET device illustrated in FIG. 5.

8 is a schematic diagram of a source common FET equivalent circuit model.

FIG. 9 illustrates a particular application of the S-parameter microscope illustrated in FIG. 5. FIG.

FIG. 10 is a view similar to FIG. 5 illustrating that a known system cannot accurately predict the internal charge and electric field structure of a semiconductor device.

11 is a top view of a four-finger, 200 μm GaAs HEMT device.

FIG. 12 illustrates an example of drain-to-source current Ids measured as a function of drain-to-source voltage Vds for the sample FET device illustrated in FIG.

FIG. 13 is an exemplary diagram illustrating drain-to-source current Ids and transconductance Gm as a function of gate-to-source voltage Vgs of the sample FET device illustrated in FIG.

FIG. 14 is a Smith chart illustrating S11, S12 and S22 parameters measured from a frequency of 0.05 to 40.05 GHz for the FET device illustrated in FIG. 11.

FIG. 15 illustrates magnitude as a function of angle with respect to the S21 S-parameter for a frequency of 0.05-40 GHz for the example FET illustrated in FIG.

FIG. 16 illustrates a charge control map of charge and electric field distribution in an on mesa source access region as Rs as a function of bias in accordance with the present invention.

FIG. 17 illustrates a charge control map of charge and electric field distribution in the on-mesa drain access region shown as Rd as a function of bias in accordance with the present invention.

18 illustrates a charge control map for non-quasi-static multi-carrier transfers, shown as Ri as a function of bias, in accordance with the present invention.

19 illustrates a charge control map for gate modulated charge and distribution under the gate, shown as Cgs and Cgt as a function of bias in accordance with the present invention.

20 is a top view of an exemplary π-FET with two gate fingers.

Fig. 21 is a plan view of a? -FET with four gate fingers.

22 is an illustration of a π-FET parasitic model according to the present invention.

Figure 23 illustrates an off-mesa parasitic model for π-FETs in accordance with the present invention.

FIG. 24 is an illustration of an interconnect and boundary parasitic model according to the present invention for a π-FET with four gate fingers as illustrated in FIG.

25 illustrates an inter-electrode parasitic model in accordance with the present invention.

FIG. 26 is a schematic diagram of the inter-electrode parasitic model illustrated in FIG. 25.

Figure 27 is an illustration of an on-mesa parasitic model in accordance with the present invention.

FIG. 28 is a schematic diagram of the on-mesa parasitic model illustrated in FIG. 27.

29 illustrates an eigenmodel according to the present invention.

30 is a schematic representation of the eigenmodel illustrated in FIG. 29.

FIG. 31A is an exemplary device layout view of a π-FET with four gate fingers. FIG.

FIG. 31B shows an equivalent circuit model for the π-FET illustrated in FIG. 31A.

32 illustrates a single finger unit device cell unique model in accordance with the present invention.

FIG. 33 is similar to FIG. 32 and illustrates a first level of embedding in accordance with the present invention.

Figure 34 is a view similar to Figure 33 and illustrating a second level of embedding in accordance with the present invention.

FIG. 35 shows an equivalent circuit model of the π-FET illustrated in FIG. 31A in accordance with the present invention. FIG.

36 is a view similar to FIG. 34 and illustrating a third level of embedding in accordance with the present invention.

FIG. 37 is similar to FIG. 34 and illustrates a fourth level of embedding in accordance with the present invention.

FIG. 38 is similar to FIG. 34 and illustrates a fifth level of embedding in accordance with the present invention.

39A and 39B are time flow diagrams of parameter extraction modeling algorithms forming part of the present invention.

40 and 41 illustrate an error metric in accordance with the present invention.

42A is a Smith chart illustrating measured values versus initial model solution for S11, S12, and S22 S-parameters from a frequency of 0.05 to 40.05 GHz.

42B is an illustration of angle versus magnitude for S-parameter S21 initially modeled from a frequency of 0.05-40.0 GHz.

FIG. 43A is a Smith chart illustrating measured S-parameters S11, S12 and S22 versus simulated S-parameters S11, S12 and S22 for a frequency of 0.05-40.05 GHz for a first extraction optimization cycle. FIG.

FIG. 43B illustrates the magnitude as a function of the measured value for the frequency of 0.05-40 GHz for the first optimization cycle and the angle for the first optimization model S21 parameter.

FIG. 44A illustrates the magnitude as a function of the final model solution for S-parameters S11, S12 and S22 for frequencies between 0.05 and 40.05 GHz for the final solution.

44B illustrates the magnitude as a function of angle for S-parameter S21 for the final model solution from a frequency of 0.05-40.0 GHz.

In summary, the present invention relates to a method of using bias-dependent S-parameter measurements in the form of microscopy. Microscopy can be used to determine details of the internal charge and electric field structure of semiconductor devices. Like other forms of microscopy, S-parameter microscopy focuses on the pseudo "image" and provides contrast in the "image". In essence, the images are collected as raw form with S-parameter measurements and extracted as small signal models. This model is used to form a charge control map through an optional method similar to focusing. Focusing is provided by an algorithm for unique determination of small signal parameters with contrast provided using measured bias dependent activity, to distinguish the boundary between the electrical charge and the electric field. As such, the system can provide a model that accurately describes the internal electrical structure of a semiconductor device.

These and other advantages of the present invention will be readily understood with reference to the following description and attached drawings.

The present invention relates to S-parameter microscopy (SPM), which enables qualitative studies of the magnitude and location and electric field distribution of electric charges in semiconductor device structures. The method uses bias dependent S-parameter measurements in the form of microscopy to provide a qualitative analysis of the internal charge and electric field structure of semiconductor devices that are not known until now. Pseudo images are collected in the form of S-parameter measurements extracted with small signal models to form a charge control map. Finite element device simulations have been used to calculate the internal charge / field of semiconductor devices so far, but this method is known to be relatively inaccurate. In accordance with the present invention, S-parameter microscopy provides a relatively accurate method for determining the internal charge and electric field in a semiconductor device. Given the accurate modeling of the internal charge and the electric field, all of the external electrical characteristics of the semiconductor device can be modeled relatively accurately, including the high frequency performance of the device. Thus, the system is suitable for creating device technology models that enable the prediction and design of high frequency MMIC yield analysis for manufacturing analysis.

S-parameter microscopy is similar to other microscopy techniques in that the SPM uses measurements of the energy reflected from the sample and energy from the sample to derive information. More specifically, the SPM is based on the transmitted and reflected microwave and millimeter wave electromagnetic power, or S-parameters. As such, S-parameter microscopy is similar to the combined operation of scanning and transmission electron microscopy (SEM and TEM). The scattered RF energy is similar to the reflectance and transmittance of the electron beam in SEM and TEM. However, instead of using an electronic detector as in SEM and TEM, a reflectometer in the network analyzer is used in the S-parameter microscopy to measure the signal. S-parameter microscopy both use a measurement of scattering phenomena as data and include a mechanism for focusing the measurement for better resolution, and as detailed in Table 1 below It is similar to other microscopy techniques in that it includes a mechanism for contrasting the measured parts.

Common microscope S-parameter microscope Measurement of scattering energy Measurement of S-parameters Mechanism for " focus " Focuses by Extracting Unique Equivalent Circuit Models Mechanism for " contrast " Contrast using bias dependencies to finely distinguish the characteristics and location of charge / field

result : "Image" of the internal charge and electric field structure of the device

In conjunction with S-parameter microscopy, the image as discussed herein is not related to the actual image, but is used to provide insight and qualitative details about the internal operation of the device. More specifically, S-parameter microscopy does not provide a visual image, as is the case with traditional forms of microscopy. Rather, the S-parameter microscopy image is more similar to a map calculated based on a non-intuitive set of measurements.

5 shows a conceptual representation of an S-parameter microscope according to the invention, generally identified by reference numeral 20. The S-parameter microscope 20 is similar to a microscope that combines the principles of SEM and TEM. The SEM measures the reflectance and the TEM measures the transmittance, while the two-port S-parameter microscope 20 measures both the reflected power and the transmitted power. As a result, the data derived from the two-port S-parameter microscope includes information about the intrinsic and extrinsic charge structures of the device. More specifically, as is known in the art, SEM provides a relatively detailed image of the sample plane through reflective electrons, while TEM provides an image of the internal structure through transmitted electrons. Reflected signals are used to form external details of the sample, while transmitted electrons provide information about the internal structure of the device. In accordance with an important aspect of the present invention, S-parameter microscopy uses a process to measure reflected and transmitted signals to provide a similar “image” of the charge structure of a semiconductor device. As used herein, the internal and external electrical structures of the semiconductor device are commonly referred to as intrinsic device regions 22 and exogenous parasitic access regions 24, as shown in FIG. Also contributing to the external electrical structure of the device are the parasitic components associated with the electrodes and their interconnections which are not shown. These are the so-called "layout parasitics".

Referring to Figure 5, ports 26 and 28 are emulated with S-parameter measurements. S-parameter measurements are generally processed in accordance with the present invention to provide a charge control map shown in a circle 32 similar to an image in other microscopy techniques for a particular semiconductor device identified generally by the reference numeral 30. As discussed in more detail below, these charge control maps 32 are represented in the form of equivalent circuit models. As shown in FIG. 7, linear circuit elements may be used in the model to represent the state and magnitude of the charge / field in semiconductor device 30 or its so-called internal charge structure. The location of the circuit elements in the model topology is approximately close to the physical location in the device structure, so that the charge control map shows a diagram of the internal electrical structure of the device.

The interpretation of the exact position of the charge / field measured within the semiconductor device is ambiguous because, for example, an equivalent circuit model with separate linear elements is used to represent the charge / field distribution structure, as shown in FIG. 8. It is known. Although no precise method exists for separating physical boundaries between measured quantities, bias dependencies are used to clarify how S-parameters should be distinguished, separated, and collated. In particular, changing the bias condition is known to change the magnitude and movement boundary between the charge and the electric field in the device. The change is normally predictable and qualitatively well known in most techniques. As such, the charge control map can be readily used as a map showing the characterization of the physical changes in the magnitude, position, and separation of the electric charge and the electric field.

Similar to other forms of microscopy, the S-parameter microscope 20 according to the present invention emulates a lens identified by reference numeral 40 (FIG. 5). Lens 40 is simulated by a method for the extraction of a unique equivalent circuit model that also accurately simulates the measured S-parameters. More specifically, parameter extraction methods for equivalent circuit models simulating S-parameters are relatively well known. However, when its sole purpose is to accurately fit the S-parameters it measures, an infinite number of solutions exist for possible equivalent circuit parameter values. Thus, in accordance with an important aspect of the present invention, only one unique solution is extracted that accurately describes the physical charge control map of the device. The present method for unique extraction of equivalent circuit model parameters serves as a lens to focus the charge control map solution. As discussed and illustrated herein, lens 40 is subsequently simulated by a filter based on a clear layout parasitic embedding model. As discussed below, the layout parasitic embedding model consists of linear elements that simulate the effects of the electrodes and interconnections of the device on the external electrical properties of the device. PiFET embedding model 42 is described below. This model acts as a filter to effectively remove the electrical structure of exogenous parasitic access contributions to the preliminary charge control map solution. The resulting filtered charge control map solution shows a sharper "image" showing only the electrical structure of the native device. This enhanced image is required to achieve the view of the internal charge / field as accurately as possible. Unlike conventional extraction techniques as shown in FIG. 10 which only extracts a non-unique equivalent circuit model and does not extract a unique charge control map, the S-parameter microscope 20 according to the present invention is a semiconductor device. The internal charge / field structure within can be modeled with relative accuracy.

Exemplary applications of S-parameter microscopes are shown in detail below. In this example, an exemplary GaAs HEMT device with four gate fingers and a total gate periphery of 200 μm formed in a PiFET layout as shown generally in FIG. 11 and identified by reference numeral 43 is used. . GaAS HEMT 43 is adapted to be embedded in a coplanar test structure with a 100 μm pitch to facilitate on-wafer S-parameter measurements.

Initially, as shown in FIGS. 12 and 13, the I-V characteristics for the device are measured. In particular, the drain source current Ids is shown as a function of drain to source voltage Vds at various gate voltages Vgs as shown in FIG. 12. FIG. 13 shows drain to source current Ids as a function of gate voltage Vgs and transconductance Gm (ie, derivative of Ids over Vgs) at different drain voltages Vds. These I-V characteristics represent HEMT devices and most semiconductor devices, which are one type of semiconductor device technology with three terminals.

Table 2 shows the bias conditions under which the S-parameters were measured. S-parameters were measured at 0.05-40 GHz under each bias condition. FIG. 14 shows a Smith chart showing S-parameters S11, S12, and S22 measured for frequencies between 0.05 and 40.0 GHz. 15 graphically shows magnitude as a function of angle for S-parameter S21 measured for frequencies of 0.05-40.0 GHz.

Measured S-Parameter Bias Conditions bias Vds = 0V Vds = 0.5V Vds = 1.0V Vds = 2.0V Vds = 4.0V Vds = 5.0V Vgs -1.6V Yes Yes Yes Yes Yes Yes -1.4V Yes Yes Yes Yes Yes Yes -1.2V Yes Yes Yes Yes Yes Yes -1 V Yes Yes Yes Yes Yes Yes -0.8V Yes Yes Yes Yes Yes Yes -0.6V Yes Yes Yes Yes Yes Yes -0.4V Yes Yes Yes Yes Yes Yes -0.2V Yes Yes Yes Yes Yes Yes 0 V Yes Yes Yes Yes Yes Yes 0.2V Yes Yes Yes Yes Yes Yes 0.4 V Yes Yes Yes Yes Yes Yes 0.6 V Yes Yes Yes Yes Yes Yes

Using the small signal model shown in FIG. 8, the extracted small signal equivalent circuit values are obtained as shown in Table 3 for each S-parameter under each bias condition, using the extraction method discussed below.

The values in Table 3 represent solutions close to the charge control map and represent physically meaningful solutions of the electrical structure of the FETs. However, the values shown in Table 3 include the effects of external layout parasitics, subtracted using a model for embedding parasitics to obtain the most accurate charge control mapping to intrinsic device characteristics, in accordance with an important aspect of the present invention. . In particular, the embedding model is applied to filter the extracted equivalent circuit model values and to obtain values that better represent the unique device. In particular, in an exemplary embodiment, the PiFET embedding parasitic model is used to subtract capacitive contributions due to the interelectrode and off-mesa layout parasitic effects. This filter essentially subtracts a known amount formed of different parameters (Cgs, Cgd, and Cds) depending on the device layout involved. In this example, embedding of inductive parameters is not necessary because these amounts are exogenous and do not contribute to the charge control map of the inherent device.

As discussed above, a lens with a filter is used to generate a unique charge control map. In particular, FIGS. 15-18 show bias dependent charge control maps for parameters RS, RD, RI, CGS, and CGD as a function of bias. More specifically, FIG. 15 shows the charge control map and electric field distribution of charge in the on-mesa source access region shown by the source resistance Rs as a function of bias. FIG. 16 shows the charge control map and electric field distribution of charge in the on-mesa drain access region shown by drain resistance Rd as a bias function. FIG. 17 shows charge control maps for non-quasi static multi-carrier transfers shown by the intrinsic device charge resistance Ri as a function of gate bias for different drain bias points. 18 shows a charge control map for the gate modulated charge and distribution under the gate shown as gate capacitances CGS and CGD as a function of bias.

filter

As mentioned above, the S-parameter microscope 20 uses a filter to provide a clearer charge control map that models the internal charge / field of the semiconductor device. Although the filter is shown in conjunction with a? FET with multiple gate fingers as shown in Figs. 20 and 21, the principles of the present invention are applicable to other semiconductor devices.

As shown in FIG. 20, the PiFET is a device in which the edge and gate finger of the active region are similar to the Greek letter π, as shown. This PiFET layout facilitates the construction of a multi fingered large periphery device cell, for example, as shown in FIG. According to an important aspect of the present invention, semiconductor devices of multiple fingers are modeled as a combination of device cells of a single finger. The device cells of each single finger are represented by a hierarchy of four models, which are in turn assembled with each other using the model to interconnect to represent any multi-fingered device cells shown in FIG. 22. The four models are the same as the off mesa or boundary parasitic model, the mutual electrode parasitic model, the on-mesa parasitic model, and the eigen model.

The off-mesa parasitic model is shown in FIG. 23. This model represents the parasitics present outside the active FET region for each gate finger. In this model, the fringing capacitance of each gate finger of the active device region as well as off mesa gate finger resistance is modeled.

The mutual electrode parasitic model and its equivalent circuit are shown in FIGS. 24 to 26. This model represents parasitics between metal electrodes along each gate finger. The following fringe capacitance parasitics, as shown generally in FIG. 25, are gate to source air bridge, drain to source air bridge, and gate to source ohms. It is modeled for ohmic, gate to drain ohmic resistance, and source to drain ohmic resistance.

Onmesa parasitic models and their equivalent circuits are shown in FIGS. 27 and 28. This model represents the parasitics around the active FET region along each gate finger, which includes several capacitance fringe parasitics and resistive parasitics. In particular, gate-to-source side recesses, gate-drain-side recesses, gate source access charges / doped caps, and gate-drain access charges / doped cap capacitance fringing parasitics are modeled. Moreover, gate metallization and ohmic contact resistance parasitics are modeled.

The intrinsic model and its equivalent circuit are shown in FIGS. 29 and 30. Inherent models represent the physical characteristics that predominantly determine FET performance. In particular, the DC and current voltage responses are described in " NONLINEAR CHARGE CONTROL IN in AlGaAs modulation-doped FETs, for example, by Hughes et al. AlGaAs MODULATION-DOPED FETs ", IEEE Bulletin, Electronic Devices (Vol. ED-34, No. 8), based on physical properties of the location and magnitude of intrinsic charges generally known in the art. Can be determined by analytical equations. Small signal model performance is modeled by taking the derivative of the appropriate charge or current control equation to derive various conditions such as RI, RJ, RDS, RGS, RGD, GM, TAU, CGS, CDS, and CGD. Such control equations are generally known in the art and are described in detail in the aforementioned Hughes et al., Which are incorporated herein by reference. Noise performance is described in "Noise Characteristics of Gallium Arsenide Field-Effect Transistors," by H. Statz et al., 1974, September . Vol. ED-21, No. 9, and by A. Van Der Ziel, March 1963, "Gate Noise in Field Effect Transistors at significantly higher frequencies. Moderately High Frequencies ”, ( PROC.IEEE , Vol. 51).

Examples of parasitic models for use with the S-parameter microscopy discussed above are shown in FIGS. 31A-38. Although certain embodiments of semiconductor devices are shown and described, the principles of the present invention are applicable to various semiconductor devices. Referring to FIG. 31A, a PiFET is shown. As shown, the PiFET has four gate fingers. A four-fingered PiFET is modeled in FIG. 31B. In particular, FIG. 31B shows an equivalent circuit model for the PiFET shown in FIG. 31A, as implemented by a known CAD program of LIBRA 6.1, for example as manufactured by Age Technologies. As shown, the equivalent circuit model does not depict all of the network connections or equivalent circuit elements associated with implementing the parasitic embedding model, but rather illustrates the final product. FIG. 31B is shown in a symbolic diagram to illustrate the similarity to FIG. 3. Actual technical information regarding the configuration of the network and its equivalent circuit elements is typically provided in a schematic drawing.

32-38 illustrate the application of parasitic models for use with S-parameter microscopy. An important aspect of the present invention relates to modeling a device with multiple gate fingers as a single gate finger device. As used herein, a single unit device cell refers to a device associated with a single gate finger. For example, as shown in FIG. 31A, a four-finger PiFET is modeled as four unit device cells.

Initially, the four fingered PiFETs shown in FIG. 31A are modeled as a single finger unit device cell 100 with a unique model 102, as shown in FIGS. 32 and 33. In particular, the PiFET native FET model 104 is replaced with block 102 defining the first embedding level. As shown in FIG. 33, the parameter values for the PiFET eigen model are added together with the parameter values for the unit device cell eigen model with a single finger. The unique device model 104 may be developed by S-parameter microscopy, as discussed above. Next, as shown in FIG. 34, the interconnect layout parasitic element is equivalent by simply adding a model term to the value of the appropriate circuit element to form a single unit device cell defining the second embedding level. Is added to the model. Once a single unit device cell has been formulated, the device is used to construct a model for multiple fingered devices. In this case, a PiFET with four gate fingers is modeled as four single finger device unit cells as shown in FIG. The off mesa layout parasitic element is then connected to a plurality of fingered layouts that define the third embedding level, as shown in FIG. 36. These off-mesa layout parasitic elements, generally identified 108 and 110, are implemented as new circuit elements connected to major external nodes of the equivalent circuit structure. Thereafter, the fourth embedding level is implemented as generally shown in FIG. 40. In particular, the inductor model is connected to each source of the various unit device cells to represent a metal bridge interconnect, as generally shown in FIG. 37. Finally, as shown in FIG. 39, the fifth embedding level in which the feed electrode models 114 and 116 are modeled as distributed linear elements (ie microstrip lines and junctions) as well as lumped linear elements (capacitors, inductors). This is implemented to form the gate feed and drain connections shown in FIG. As shown, the distributed element is a distributed model for microstrip elements, as implemented in LIBRA 6.1.

Extraction Method for Unique Determination of FET Equivalent Circuit Model

As discussed above, a method of determining FET equivalent circuit parameters is shown in FIGS. 39-44. The method is based on an equivalent circuit model, such as the source common FET equivalent circuit model shown in FIG. Referring to FIG. 39A, a model is initially generated at step 122. The model shown in FIG. 8 is used as a small signal model for the FET. According to an important aspect of this algorithm, the equivalent circuit parameters are based on the measured FET S-parameters. Measurement of S-parameters of semiconductor devices is well known in the art. 42A is a Smith chart showing S-parameters S11, S12, and S22 measured by example for frequencies between 0.05 and 40.05 GHz. FIG. 42B shows a magnitude angle chart for S-parameter S21 measured from a frequency of 0.05-40.0 GHz. As disclosed in step 124 (FIG. 39A), after the S-parameter is measured, it is confirmed whether the measurement is suitable for step 126. This is done by manually checking the test results for anomalies or by either algorithm that verifies the test set. If the measurement is suitable, the S-parameter measurement is stored at step 128.

For example, as shown in Table 4, the space of the experimental starting feedback impedance point value is selected. At this point, a direct model attraction algorithm, known as the Minasian algorithm, is used to generate a preliminary value for the equivalent circuit model parameter for each value of the starting feedback impedance. This extraction algorithm, e.g., 1980, July, Kerberos (M. Berroth), "FET small crystal of broadband small-signal equivalent circuit (Broadband Determination of the FET Small Small Signal Equivalent Circuit)" due to, (IEEE- As disclosed in MTT , Vol. 38, No. 7), it is well known in the art. Model parameter values are determined for each of the starting impedance point values shown in Table 4. In particular, referring to FIG. 39A, each impedance point in Table 4 is processed by blocks 130, 132, etc. to develop model parameter values for each impedance point in order to develop an error metric. The metrics are in turn used to develop a unique small signal device model, as discussed below. The processing at each block 130, 132 is similar. Thus, only a single block 130 is discussed for the example impedance points shown in Table 4. In this example, an impedance point 17 is used that correlates the source resistance Rs of 1.7 Ω and the source inductance Ls of 0.0045 pH.

Test start feedback, impedance space point value Impedance point Resistance (Rs) Inductance (Ls) One 0.1Ω 0.0045pH 2 0.2Ω 0.0045pH 3 0.3 Ω 0.0045pH 4 0.4 Ω 0.0045pH 5 0.5 Ω 0.0045pH 6 0.6 Ω 0.0045pH 7 0.7Ω 0.0045pH 8 0.8 Ω 0.0045pH 9 0.9 Ω 0.0045pH 10 1.0Ω 0.0045pH 11 1.1Ω 0.0045pH 12 1.2Ω 0.0045pH 13 1.3Ω 0.0045pH 14 1.4Ω 0.0045pH 15 1.5 Ω 0.0045pH 16 1.6 Ω 0.0045pH 17 1.7 Ω 0.0045pH 18 1.8Ω 0.0045pH 19 1.9Ω 0.0045pH 20 2.0Ω 0.0045pH 21 2.1Ω 0.0045pH 22 2.2 Ω 0.0045pH 23 2.3 Ω 0.0045pH 24 2.4 Ω 0.0045pH 25 2.5 Ω 0.0045pH 26 2.6 Ω 0.0045pH 27 2.7 Ω 0.0045pH 28 2.8Ω 0.0045pH 29 2.9 Ω 0.0045pH 30 3.0Ω 0.0045pH

For the selected value Rs = 1.7 Ω, the initial intrinsic equivalent circuit parameters and the initial parasitic equivalent circuit parameters are determined, for example, by the Minasian algorithm mentioned above, as disclosed in steps 134 and 136, as shown in Table 5 and It is shown in Table 6. In step 138, the simulated circuit parameters are compared with the measured S-parameters, as shown, for example, in FIGS. 43A and 43B. Each of the processing blocks 130, 132, etc., passes through six completion cycles. As such, the system determines in step 140 whether six cycles have been completed.

Initial "Unique" Equivalent Circuit Parameters Intrinsic equivalent circuit parameter Initial solution Cgs 0.23595 pF Rgs 91826Ω Cgd 0.0177 pF Rgd 100000Ω CDs 0.04045 pF Rds 142.66Ω Gm 142.1025mS Tau 0.1 pS

Initial "parasitic" equivalent circuit parameters Intrinsic equivalent circuit parameter Initial solution Rg 3.0Ω Lg 0.014nH Rs 1.7 Ω Ls 0.0045nH Rd 2.5 Ω Ld 0.024nH

Each cycle of processing block 130 consists of a direct extraction followed by optimization with a certain number of optimization iterations, eg, 60 optimization iterations. By fixing the number of extraction optimization cycles according to the number of optimization iterations, the fixed "distance" or calculation time, from which the model solution should be derived, is defined. As such, the algorithm achieves the lowest fitting error over a fixed computational time so that the "race" criterion is implemented, thereby constructing an environment in which each experimental model solution competes with each other to determine the overall error metric. Implement the convergence rate requirement, where the "convergence rate" is implicitly calculated for each processing block 130, 132, and so on.

After the system determines whether racing has completed in step 140, the system proceeds to block 142 and optimizes the model parameters. Several commercial software programs are also available. Commercially available LIBRA 3.5 software, such as, for example, manufactured by HP-eesof, can be used both for circuit simulation as well as for optimizing functions. In addition to fixing the feedback resistor Rs to a fixed value, optimization is performed in accordance with the constraints described in Table 7.

Environment used for competitive solution strategy, as implemented in this example Implementation parameters Circuit Simulators and Optimizers Libra 3.5 Optimal algorithm Gradient Optimal error metrics Sizes and angles of S11, S21, S12 and S22 from 4 to 40 GHz Number of iterations 60 Number of extraction / optimization cycles 6

By fixing the value for Rs, this segment of the algorithm was limited to creating a test model solution only for the test feedback impedance point at which the test model solution begins. Table 8 shows the intrinsic equivalent parameter values optimized using commercially available software, such as LIBRA 3.5. These values along with the optimized parasitic values, illustrated in Table 9, form the first optimized model solution for the first extraction-optimization cycle (ie, one of six). The optimized model parameters are then fed back to function blocks 134 and 136 (FIG. 39A) and used for the new initial model solution. These values are compared with the measured S-parameter values as shown in FIGS. 43A and 43B. The system repeats this cycle for six cycles in a similar manner as mentioned above. After six extraction-optimization cycles, the final test model solution for the test impedance point 17 is completed with the final fitting error for the measured data to form a new error metric 144. According to an important aspect, the extraction-optimization algorithm allows the final optimization fitting error for each point to have information about the measured error versus model fitting error and convergence rate. This algorithm does so by a fixed optimization time constraint that constitutes a competitive race between several test model solutions.

Optimized "Unique" Equivalent Circuit Parameters Intrinsic equivalent circuit parameter Initial solution Cgs 0.227785 pF Rgs 65247 yen Cgd 0.017016pF Rgd 130820Ω CDs 0.047521pF Rds 160.18 yen Gm 135.74mS Tau 0.446 pS

Optimized "parasitic" equivalent circuit parameters Intrinsic equivalent circuit parameter Initial solution Rg 4.715Ω Lg 0.02903 nH Rs ^* 1.7 Ω Ls 0.002102nH Rd 3.2893 yen Ld 0.0317nH

The implementation of the extraction optimization cycle allows the best and fastest solution to be represented by the overall minimum value for the final fitting error at step 146 of both test impedance points as generally shown in FIGS. 40 and 41. More specifically, referring to FIG. 40, the overall minimum solution using the new error metric is found around Rs = 1.7Ω. Tables 10 and 11 list the final model equivalent circuit parameters for this overall solution, including the eigen and parasitic parameters, as disclosed in step 148 (FIG. 39B).

Universal solution for "unique" equivalent circuit parameters Intrinsic equivalent circuit parameter Initial solution Cgs 0.227745 pF Rgs 64242Ω Cgd 0.017019 pF Rgd 133450 yen CDs 0.047544pF Rds 160.1791Ω Gm 135.7568mS Tau 0.443867 pS

Universal solution of "parasitic" equivalent circuit parameters Exogenous equivalent circuit parameters Initial solution Rg 4.711895Ω Lg 0.029314nH Rs 1.7 Ω Ls 0.002104nH Rd 3.309899Ω Ld 0.031671nH

To test the accuracy of this solution, the final model for the solution is compared with the measured S-parameter values as shown in FIGS. 44A and 44B. As shown, there is a good correlation between the simulated model values and the measured S-parameter values, thus verifying that the simulated model values are relatively accurate and represent a unique small signal device model.

Obviously, many modifications and variations of the present invention will be possible from the above description. Accordingly, within the scope of the appended claims, the invention may be practiced otherwise than as specifically described above.

Claims to be made by the patent literature are as follows.

As mentioned above, the present invention is applicable to a method of modeling semiconductor device technology, and more particularly, to a method of modeling a semiconductor device, such as a field effect transistor, in which a high electron mobility transistor is one type.

Claims (10)

A method of determining an internal charge and an electric field in a semiconductor device, Measuring S-parameters of the semiconductor device; And Developing a charge control map of the semiconductor device. The semiconductor device of claim 1, wherein the semiconductor device is a field effect transistor (FET), and the measuring of the S-parameter includes drain-source current Ids as a function of drain-source voltage Vds at various gate voltages Vgs. Measuring the internal charge and electric field. 3. The method of claim 2, wherein measuring the S-parameters includes measuring the S-parameters over a predetermined frequency range for each gate voltage. 4. The method of claim 3, wherein developing the charge control map comprises extracting a small signal equivalent circuit value for each S-parameter at each gate voltage. 5. The method of claim 4, further comprising developing an embedded model. 6. The method of claim 5, wherein the embedded model is used in an extracted filter to obtain the charge control map. 7. The method of claim 6, wherein the embedded model is a PiFET model. 8. The method of claim 7, wherein the PiFET model is used to subtract a predetermined capacitive contribution. 10. The method of claim 8, wherein the PiFET model is used to subtract capacitive contributions due to mutual electrode parasitic effects. 10. The method of claim 9, wherein the PiFET model is used to subtract capacitive contributions due to off-mesa parasitic effects.