KR20020093958A - Semi-physical modeling of hemt dc-to-high frequency electrothermal characteristics - Google Patents

Abstract

The present invention provides a semi-physical device model in which an analytical thermal resistance model is combined to self-consistently solve the channel temperature and internal charge / field structure of a semiconductor device. A semiconductor modeling method using 45) is provided.

Description

SEM-PHYSICAL MODELING OF HEMT DC-TO-HIGH FREQUENCY ELECTROTHERMAL CHARACTERISTICS}

HEMT technology provides RF components with high performance characteristics that are unparalleled at high frequencies (from microwave to millimeter waves) and at high power levels. As such, HEMTs are known to be used in many RF applications. Unfortunately, high power level applications also require a high level of DC power dissipation that raises the HEMT component to a high temperature level. At present, there are two main methods for modeling the electrothermal and thermal properties of HEMT devices: finite element thermal simulation and physical device simulation.

Finite element thermal simulation is used to simulate the layout-dependent thermal conduction characteristics of semiconductor devices. Such a simulation involves simulating a two-dimensional cross section of a device layout and then performing so-called quasi-three-dimensional modeling that assumes semi-infinite thermal conditions in an orthogonal direction or fully simulating a three-dimensional device layout. It can be achieved by any one of. Because full three-dimensional approaches require much more computational power and sophisticated software, quasi-three-dimensional approaches are known to be more commonly used. A typical example of this approach is shown in FIG. 1, which shows a finite element mesh for the HEMT device layout. This device layout is representative of all HEMT devices.

Finite element thermal simulation is known to provide an accurate estimate of the thermal conduction of devices. However, a major drawback of this approach is that it is not possible to reconnect the calculated channel temperature of the device back to electrical simulation to adjust the electrical characteristics of the device. In addition, this approach assumes DC power as the heat source, typically dissipate in intrinsic devices that remain constant. In practice, however, DC power dissipation also varies with temperature. Therefore, for accurate electrothermal simulation, the so-called self heating effect should be considered.

As mentioned above, the overall heat transfer characteristics can be simulated from a so-called physical device simulator. Physical device simulators are known to use comprehensive knowledge of material properties and basic device physical properties to simulate physical behavior within the device's structure. Although finite element approaches are commonly used in electrothermal simulations that also incorporate thermal conductors, the simulator is based on the finite element or Monte Carlo approach. Because these tools use physical structures to simulate performance, the correspondence between the simulated heat transfer performance and the physical characteristics of the device is relatively strong. However, the device simulator's ability to accurately model the measured high frequency electrical properties is relatively inaccurate. In general, such simulation tools can achieve quite useful modeling for DC characteristics, but cannot be used for accurate high frequency simulation. Thus, there is a need for electrothermal semiconductor device models that provide relatively accurate results at high frequencies.

Cross Reference to Related Application

This application is filed U.S. Patent Application on April 28, 2000. It is a partial application of the patent application (No. 60 / 200,648), the U.S. Claim a patent application with priority.

This application is a unique application of FET equivalent circuit model parameters, as filed on October 5, 2000, by the following commonly owned co-pending patent application Ser. Nos. 09/680, 339, that is, Roger Tsai. METHOD FOR UNIQUE DETERMINATION OF FET EQUIVALENT CIRCUIT MODEL PARAMETERS. This application is filed under serial number 60 / 200,307 (foreign agent management number 12-1114), filed on April 28, 2000, by: S-PARAMETER MICROSCOPY FOR SEMICONDUCTOR DEVICES for semiconductor devices; EMBEDDING PARASITIC MODEL FOR PI-FET LAYOUTS, for the π-FET layout of Roger No. 60 / 200,810 (International Agent Control No. 12-1116); SEC-PHYSICAL MODELING OF HEMT HIGH FREQUENCY NOISE EQUIVALENT CIRCUIT MODELS of the HEMT High Frequency Noise Equivalent Circuit Model of Roger No. 60 / 200,290 (International Agent Control No. 12-1119) ; Semi-Physical MODELING OF HEMT HIGH FREQUENCY SMALL-SIGNAL EQUIVALENT CIRCUIT of Roger No. 60 / 200,666 (International Agent Control No. 12-1120) for HEMT high frequency small signal equivalent circuit model MODELS); Hybrid semi-physical and data fitting HEMT modeling for large-signal and non-linear microwave / millimeter wave circuit CAD, serial number 60 / 200,622 (overseas agent control number 12-1127), by Roger Cai and Yaocheng Chen HYBRID SEMI-PHYSICAL AND DATA FITTING HEMT MODELING APPROACH FOR LARGE SIGNAL AND NON-LINEAR MICROWAVE / MILLIMETER WAVE CIRCUIT CAD; PM ² : PROCESS PERTURBATION TO MEASURE MODEL METHOD of Roger No. 60 / 200,302 (International Agent Control No. 12-1128), PM ² , for measuring model methods for semiconductor device technology modeling. FOR SEMICONDUCTOR DEVICE TECHNOLOGY MODELING).

The present invention relates to a method for modeling a semiconductor device, and more particularly, to an analytical thermal resistance model coupled to self-consistently solve the channel temperature and internal charge / field structure of a semiconductor device. A method of modeling thermal and electrical properties of a semiconductor device using a semi-physical device model.

1 illustrates a known finite element mesh for a HEMT device layout.

2 is a graph illustrating the semi-physical model DC I-V characteristics measured at ambient temperature at 200 ° C.

3 is a graph similar to FIG. 2 but with an ambient temperature of 25 ° C. FIG.

FIG. 4 is a graph illustrating the comparison of DC I-V characteristics and self-physically modeled DC I-V characteristics measured at an ambient temperature of 25 ° C. for a 600 μm gate peripheral device cell with large peripheral 8 fingers of self heating.

5 is a schematic diagram illustratively showing a small signal equivalent circuit model for a HEMT device.

6 is a cross-sectional view of an exemplary HEMT showing the approximate translation of the physical origin for each of the equivalent circuit elements illustrated in the small signal circuit model of FIG.

FIG. 7 is a HEMT cross-sectional view illustrating regions in the HEMT corresponding to various circuit elements in the small signal equivalent circuit model shown in FIG. 5; FIG.

FIG. 8 illustrates examples of measured and modeled I-V characteristics and relatively accurate, using self-physical modeling methods in accordance with an aspect of the present invention.

9 is a side view illustrating an epi stack for an exemplary HEMT.

10 is a cross-sectional view of HEMT for HEMT and an exemplary epi stack.

FIG. 11 is an enlarged view of a cross section parameter belonging to the T-gate geometry for the exemplary epi stack shown in FIG. 7. FIG.

12 illustrates an electrical conductance model used in a semi-physical example.

FIG. 13 is a Smith chart showing measured S-parameters vs. modeled S-parameters S11, S12, and S22 simulated according to the method according to the invention.

FIG. 14 illustrates measurements versus modeling values for S21 parameters. FIG.

FIG. 15 is similar to FIG. 14 but shows measured versus modeling values for S12 S-parameters. FIG.

FIG. 16 is a graph showing the fitting of a non-linear data-fitting model to semi-physically modeled I-V characteristics in accordance with the present invention. FIG.

17 illustrates an interior region and an exterior region of an exemplary HEMT device.

FIG. 18 is a view similar to FIG. 16 but showing an approximate location of model elements within the HEMT FET device shown in FIG. 16.

19 is a schematic diagram of a FET equivalent circuit model of a common source.

20 illustrates a particular application of the S-parameter microscope shown in FIG. 16. FIG.

FIG. 21 is similar to FIG. 16, illustrating that the electric field structure and internal charge of a semiconductor device cannot be accurately predicted with known systems;

22 is a top view of a 200 μm GaAs HEMT device with four fingers.

FIG. 23 is a graph showing measured drain-source current Ids as a function of drain-source voltage Vds in the sample FET device shown in FIG.

FIG. 24 is a graph showing drain-source current Ids and transconductance Gm as a function of gate-source voltage Vgs of the sample FET device shown in FIG.

FIG. 25 is a Smith chart showing S11, S12, and S22 parameters measured at a frequency of 0.05 to 40.05 GHz in the FET device shown in FIG. 22. FIG.

FIG. 26 is a graph showing magnitude as a function of angle of the S21 S-parameter for a frequency of 0.05-40 GHz in the example FET shown in FIG. 22.

FIG. 27 is a graph showing a charge control map and electric field distribution of charge in an on mesa source access region, denoted Rs, as a function of bias in accordance with the present invention.

FIG. 28 is a graph showing a charge control map and electric field distribution of charge in an on-mesa drain access region, denoted Rd, as a function of bias in accordance with the present invention;

FIG. 29 is a graph illustrating the charge control map for non-quasi static majority career transfer, denoted Ri as a function of bias in accordance with the present invention.

30 is a graph showing a charge control map for gate modulated charge and distribution under the gate, denoted as Cgs and Cgt as a function of bias in accordance with the present invention.

31 is a top view of an exemplary π-FET with two gate fingers.

32 is a top view of a π-FET with four gate fingers.

Figure 33 illustrates a π-FET parasitic model in accordance with the present invention.

34 illustrates an off-mesa parasitic model for π-FETs in accordance with the present invention.

FIG. 35 shows an interconnect and boundary parasitic model according to the present invention for a π-FET with four gate fingers as shown in FIG.

36 illustrates a cross-electrode parasitic model in accordance with the present invention.

FIG. 37 is a schematic representation of the inter-electrode parasitic model shown in FIG. 36.

FIG. 38 illustrates an on-mesa parasitic model in accordance with the present invention. FIG.

FIG. 39 is a schematic diagram of the on-mesa parasitic model shown in FIG. 38.

40 shows an eigenmodel according to the invention.

FIG. 41 is a schematic diagram of the eigenmodel shown in FIG. 40;

42A shows an exemplary device layout of a π-FET with four gate fingers.

FIG. 42B shows an equivalent circuit model for π-FET shown in FIG. 42A. FIG.

FIG. 43 illustrates a single finger unit device cell unique model in accordance with the present invention. FIG.

FIG. 44 is similar to FIG. 43 and illustrates a first embedding level in accordance with the present invention.

45 is a view similar to FIG. 43 and showing a second embedding level in accordance with the present invention.

FIG. 46 illustrates an equivalent circuit model of π-FET shown in FIG. 42A in accordance with the present invention. FIG.

FIG. 47 is similar to FIG. 45 and illustrates a third embedding level in accordance with the present invention.

FIG. 48 is similar to FIG. 45 and illustrates a fourth embedding level in accordance with the present invention.

FIG. 49 is similar to FIG. 45 and illustrates a fifth embedding level in accordance with the present invention.

50A and 50B are flowcharts of a parameter extraction modeling algorithm that forms part of the present invention.

51 and 52 illustrate an error metric in accordance with the present invention.

FIG. 53A is a Smith chart showing the solution versus initial model solution measured for S11, S12, and S22 S-parameters at a frequency of 0.05-40.05 GHz. FIG.

FIG. 53B is a graph showing angle versus magnitude for S-parameter S21 initially modeled at a frequency of 0.05-40 GHz. FIG.

FIG. 54A is a Smith chart showing S-parameters versus simulated S-parameters S11, S12, and S22 measured at a frequency of 0.05-40 GHz during a first extraction optimization cycle. FIG.

54B is a graph showing magnitude as a function of angle for measurement and first optimized model (S21) parameter at a frequency of 0.05 to 40 GHz during a first optimization cycle.

55A is a Smith chart showing measurements as a function of final model solution for S-parameters S11, S12, and S22 at a frequency of 0.05 to 40.05 GHz for the final solution.

55B is a graph showing magnitude as a function of angle for S-parameter S21 of the final model solution at frequencies from 0.05 to 40 GHz.

FIG. 56 is a graph showing semi-physically modeled small signal versus measured small signal (Gm). FIG.

FIG. 57 is a graph showing the semi-physically simulated bias dependency of small-signal output conductance Rds.

FIG. 58 is a graph showing semi-physically simulated bias dependence of small signal gate-source and gate-drain capacitances (Cgs and Cgd). FIG.

FIG. 59 is a graph showing the semi-physically simulated bias dependency of small signal gate source charge resistor Ri. FIG.

FIG. 60 is a graph showing the semi-physical bias dependence of small signal source and drain resistors Rs and Rd. FIG.

FIG. 61 is a graph showing bias dependent gain vs. modeled bias dependency gain measured at 23.5 GHz for a K-band MMIC amplifier. FIG.

62A and 62B are graphs showing parameters extracted from device I-V parameters measured for process control monitor testing.

FIG. 63 is a graph showing the process variation measured for Gmpk and Vgspk versus the anti-physically simulated process variation. FIG.

64 is a graph depicting measured process variation versus anti-physically simulated process variation for Idspk and Gmpk.

FIG. 65 is a graph depicting measured process variation versus anti-physically simulated process variation for Imax and Vpo. FIG.

FIG. 66 is a graph showing measured / extracted process variation versus anti-physically simulated process variation for small signal equivalent models Rds and Gm. FIG.

FIG. 67 is a graph depicting the measured / extracted process variation versus anti-physical simulation process variation for small signal equivalent models Cgs and Gm. FIG.

FIG. 68 is a graph showing measured physical dependence versus anti-physically simulated physical dependence for I max as a function of physical gate length. FIG.

FIG. 69 is a graph showing the physical dependence of the measured / extracted model versus the anti-physical simulation physical dependence on Rds as a function of physical recess undercut width.

In short, the present invention provides a semiconductor device that uses a semi-physical device model combined with an analytical thermal resistance model to self-consistently solve the channel temperature and internal charge / field structure of the semiconductor device. It relates to how to model. As such, the method according to the invention can realistically simulate the response of the electrical performance to the temperature of the semiconductor device and vice versa.

These and other advantages of the present invention will be readily understood with reference to the following detailed description and the accompanying drawings.

The model according to the invention uses a semi-physical device model coupled to an analytical thermal conductivity model as a means of simulating electrothermal performance characteristics of a semiconductor device. In particular, semi-physical models for HEMT devices have proven to be able to represent small signal, noise, non-linear and large signal characteristics relatively accurately. To merge the temperature dependence and also the layout dependence of thermal conductivity, the following procedure is used:

1) We derive a semi-physical device model that can replicate DC I-V characteristics and bias-dependent small signal characteristics measured at room temperature very accurately.

2) merge any known temperature dependence of the material parameters.

3) Measure DC I-V and bias-dependent small signal S-parameters over the desired range of temperatures.

4) Extract the small-signal equivalent circuit model for each of the S-parameter measurements versus temperature. S-parameter microscopy, which will be discussed later, can be used to develop a charge-control map solution.

5) Develop a temperature coefficient expression to apply to the intrinsic device model expression of the semi-physical model. These temperature coefficients need to be adjusted for the anti-physical device model's estimates to match the DC and small signal data measured at each temperature. More specifically:

a) I-V must match.

b) Minasian induction, as detailed in, for example, IEEE-MTT Vol. 38 , "BroadBand Determination of the FET Small-Signal Equivalent Circuit" by Berroth et al . If the conventional prior art small signal model derivation, such as algorithms (Minasian extraction algorighms) is performed, the relative change in CV (capacitance versus voltage) must match the semi-physical model estimate.

c) If S-parameter microscopy is performed, the absolute change in C-V must be matched to a semi-physical model.

6) Implement appropriate analytical thermal conductivity models.

7) Combine the semi-physical device model and the analytical thermal conductivity model by the following operations:

a) Replace "environmental temperature" with "channel temperature" operating at both temperature-dependent factors and temperature coefficients

b) Use the semi-physically modeled length of the saturated region, ie XSAT, as the length of the heat-generating region.

As will be discussed later, the semi-physical HEMT model can be extended to perform a full electrothermal device simulation. In accordance with the foregoing, the semi-physical model mentioned in step 1 will be discussed later. In step 2, the reported thermal properties of the material system used in the HEMT technique are incorporated into the appropriate material related equations of the semi-physical device model. These properties are S. J.Appl.Phys , 58, 3 (August 1985), a work of S. Adachi, “GaAs, AlAs and AlxGal-xAs material parameters and device applications (GaAs, AlAs and AlxGal-xAs Materials Parameters For Use and Research and Device Applications, which are incorporated by reference In step 3, the DC IV and bias dependent S-parameters are for example -25 ° C, 25 ° C, 125 ° C and Measured for a standard device layout over several substrate temperatures, such as 200 ° C. In step 4, S-parameter microscopy is used for each temperature dependent data set In step 5, the temperature compensation coefficient is It develops from the reported material heat dependency relations such as Equation 1 presented.

Equation 1

Once expressed, TCF is applied to the appropriate semi-physical charge and transport control equations, and the temperature dependent I-V and C-V characteristics are properly fitted. As shown, Equation 2 below illustrates how the key charge control and carrier transport relationship is enhanced to incorporate temperature dependence through the experimental temperature compensation factor presented below.

[Equation 2]

FIG. 3 now demonstrates an enhanced semi-physical device model capable of accurately simulating I-V characteristics at 200 ° C., while FIG. 4 demonstrates the accuracy of I-V simulations at 25 ° C. FIG. Thus, the semi-physical model that can be derived at room temperature can be modified through experimental temperature coefficients to incorporate the exact temperature dependence.

In step 6, the analytical heat conduction expression is H. "Precision Technique Finds FET Thermal Resistance" in H. Cooke's work " Microwaves and RF " (August 1986). Same as Finally, in step 7, the gate length considered as the length of the heat-generating region in the cook's expression is replaced by the equation 3, semi-physically modeled XSAT expression provided below.

[Equation 3]

In Cook's crude diagram, it is assumed that the heat-source in the FET can be estimated by an equivalent source for the length of the physical gate length. In fact, a more accurate expression for this heat source would have a length or XSAT equal to the length of the saturation region. Most of the drain voltage and hence most of the DC power dissipation drops across this area, making this dimension more suitable for describing heat sources.

The temperature compensation coefficient is changed to operate between the "ambient temperature" and the "channel temperature" generally presented by equation 4 provided below.

[Equation 4]

The difference between TCF and TCF 'is that TCF is a temperature coefficient determined through complete and even heating of the device sample. When "substrate" heating is used to heat a device sample, it can be assumed that the substrate temperature is approximately equal to the "channel temperature", or rather the temperature of the device is the same temperature as the ambient environment.

The implementation of Cook's method combined with a semi-physical device model results in equation 5 below.

[Equation 5]

When the device dissipates a lot of power and thus cannot effectively dissipate this heat due to finite heat conduction, the device enters a thermal state known as "self-heating". In the self-heating state, the area adjacent the heat source of the device, or generally the area under the gate, is heated to a higher temperature than the substrate. As a result, the device becomes hotter than its surroundings. In this state, the "channel temperature" should be used to measure how hot the intrinsic device is.

As an example of how accurately the formula models the self-heating effect, a 600 μm total gate peripheral device cell with a large peripheral 8-finger was tested for DC-IV and S-parameters at room temperature. This particular device layout dissipates too much DC power at high drain voltages or high drain currents that can be effectively removed by thermal conduction. As a result, the device undergoes extreme self-heating. As shown in FIG. 4, the electrothermal model of the semi-physical device model can relatively closely simulate the effect of self-heating channel temperature on the electrical performance of the device.

Semi-physical model (SEMI PHYSICAL MODEL)

Semi-physical device modeling represents both physical device characteristics and measured characteristics, which can be used to simulate RF performance through a physically based device model. A semi-physical model is an analytical model based on experimental expressions that model the physical properties of HEMT behavior, thus the term "semi-physical". The model merges actual process parameters such as gate length recess etch depth, recess undercut size, passivation nitrite thickness, and the like. Using empirical expressions, the semi-physical model can maintain relatively good accuracy of measurements versus modeling values while taking into account the effects of process variations on device performance.

The semi-physical model provides a model element for a standard small signal equivalent circuit model or the FET is illustrated in FIG. FIG. 6 roughly shifts the physical origin for each of the equivalent circuit elements in the small signal equivalent circuit model illustrated in FIG. 7 illustrates a cross section of an exemplary HEMT device structure. However, unlike conventional methods, model elements are derived from small signal excitation analysis of the internal charge and electric field in the device. As such, the simulated small signal model element represents a relatively accurate physical equivalent circuit description for the physical FET.

General methods for semi-physical modeling of intrinsic charge, electrical conductance, and electric field are as follows: first, conduction band offset, electrical permitivity for various materials in the epi stack, The relationship between the material composition is determined. These relationships can be performed analytically or by fitting simulated data from a physical simulator. Thereafter, the basic charge transfer properties of any of the bulkable materials applicable in the epi stack are determined. Once the electron transfer properties are determined, the depleted linear channel mobility is determined through characterization or physical simulation of the material. After that, the height value or expression of the Schottky barrier is determined. Once the height value of the Schottky barrier is determined, a semi-physical equation is constructed by modeling the following properties:

Fundamental-charge control physical characteristics for sheet charge in an active channel controlled by the gate terminal voltage.

Average center position of the sheet charge within the width of the active channel.

Location of charge partitioning boundaries as a function of gate, drain, and source terminal voltage.

Bias dependence of linear channel mobility within surface depleted regions.

Bias dependence of the velocity saturation field in the channel.

Saturated electron speed.

Electrical conductance in the linear region of the channel under the gate.

Electrical conductance in the source and drain access areas.

Once the semi-physical equations are determined, the experimental terms of the semi-physical modeling equations are adjusted to fit the model I-V (current / voltage) characteristics to the measured values. Thereafter, the experimental term is repeatedly readjusted to simultaneously fit the measured I-V (capacitance-voltage) and I-V characteristics. Finally, the experimental modeling term is fixed for future use.

By constructing a comprehensive set of semi-physical equations covering all of the physical phenomena as mentioned above, the mechanisms that physically operate within the HEMT device can be determined relatively accurately. 8 shows a set of relatively accurate measured I-V characteristics versus modeled I-V characteristics for HEMT using the semi-physical modeling discussed herein. In particular, FIG. 8 shows drain to source current Ids as a function of drain to source voltage Vds for various gate biases, for example, from 0.4V to −1.0V. As shown in FIG. 8, solid lines are used to represent the semi-physical model, while Xs is used to represent the measured value. As shown in FIG. 8, there is a close relationship between the measured value and the modeled parameter.

An example of semi-physical modeling of physical device operation in accordance with the present invention is provided below. An example uses an example device, as shown in FIGS. 9 and 10. Table 2 shows exemplary values for the physical cross-sectional parameters of the model. FIG. 11 relates to a blown up T-gate characteristic correlated with the parameters identified in Table 1. FIG.

Value for entering physical parameters into the device cross section Layout parameters unit value Gate length Lg [Μm] 0.150 Wing length Lgw [Μm] 0.520 Gate Mushroom Crown Length Lgmcl [Μm] 0.200 Total gate height Hg [Μm] 0.650 Gate stem height Hgstem [Μm] 0.300 Gate height Hgsag [Μm] 0.100 Gate cross section Gatearea [Μm ² ] 0.187 Cross-sectional area MaxArea [Μm ² ] 0.364 Total gate around Wg [Μm] 200.000 # Finger N [] 4.000 Source-Drain Interval Dsd [Μm] 1.800 Gate-source spacing Dsg [Μm] 0.700 Gate-drain spacing Dgd [Μm] 1.100 Gate-source recess RECsg [Μm] 0.160 Gate-drain recess RECgd [Μm] 0.240 Recess etch depth Hrec [A] 780.000 SiN thickness Hsln [A] 750.000 Gate feed to mesa spacing Dgfm [Μm] 2.000 Gate end-mesa overlap Dgem [Μm] 2.000 Finger-Finger Spacing Through-Drain Dffd [Μm] 16.500 Finger-Finger Spacing Through Source Dffs [Μm] 13.500 Insert Source Public Path? AB? [] P Insert Source Pathway Dsabin [Μm] 28.000 Source passage height Hsab [Μm] 3.500 Source-gate airway break Hgsab [Μm] 1.640 Source pad width Ws [Μm] 12.000 Drain pad width Wd [Μm] 14.000 Board thickness Hsub [Μm] 100.000

As mentioned above, the semi-physical modeling of the intrinsic charge and electric field in the HEMT device is initiated by determining the relationship between conduction band offset, electrical permittivity, and material composition for the various materials in the epi stack. The band offset and electrical permittivity relationship with respect to material composition has been described by Michael Shur, New Jersey, 1990, such as "Physics of Semiconductor Devices" (Prentis Hall, Inglewood Cliff). Obtained from the literature. For example, the basic electron transfer properties for the linear mobility of electron carriers in the bulk GaAs cap layer can be determined to be 1350 cm 2 / Vs, using from the above “physical properties of semiconductor devices”. . The linear mobility of the electron carriers in the depleted channel is assumed to be 5500 cm 2 / Vs. This value can be measured by the Hall effect of the sample with the epi stack grown equally on this stack in this example except for some differences in the GaAs cap layer. The height of the Schottky barrier is assumed to be 1.051 volts, representing platinum metal for AlGaAs material.

Equation 6 below shows a semi-physical analysis for modeling charge control and center positions in a sample.

[Equation 6]

As used herein, Ns represents the carrier concentration of the model sheet in the active channel. Ns' represents an ideal charge control law and is modeled as a semi-physical representation of the true density of state filling rate for energy states in channel-to-gate voltage. The gate-to-channel voltage (Vgt) used for charge control is a function of the height, conduction band offset, and doping of the Schottky barrier in the epi stack, as is known in the art.

Equation 7 below represents a semi-physical expression used to model the location of region-specific charge boundaries within a HEMT device. These expressions govern how the model charge is divided between the effects of the various terminals.

[Equation 7]

Equation 8 below shows a semi-physical expression used to model the bias dependence of linear channel mobility in the depletion region.

[Equation 8]

Equation 9 below is a semi-physical expression used to model the bias dependence of saturation field and saturation rate.

Equation 9

12 schematically illustrates how electrical conductance in the source and drain access regions is modeled in this example.

The following equation 10 describes a semi-physical model of the conductance of the source access region.

[Equation 10]

The following equation 11 describes the drain access:

Equation 11

Semi-Physical Determination of Small-Signal Equivalent Circuits

As shown in FIG. 5, small signal excitation analysis should be applied to the semi-physically modeled physical expressions to derive values for the familiar small signal equivalent circuit. Here's how to apply this analysis:

1) Gate terminal voltage excitation

a) Apply a small +/- voltage delta around the desired bias condition across the gate-source terminal.

b) Equivalent circuit element Gm = delta (Ids) / delta (Vgs '), where delta (Vgs') is mostly the delta of the applied voltage, but also as RsCont, RsundepCap, RsundepRec, ResdepRec, and RsBoundary in FIG. The voltage dropped across the gate source access region, shown, is subtracted.

c) Equivalent circuit elements Cgs and Cgd take the form of delta (Nsn) / delta (Vgs) * Lgn, where delta (Nsn) is an appropriate charge control equation and Lgn is the gate source or gate drain charge division boundary length. to be.

d) Equivalent circuit element Ri = Lgs / (Cgschannel * v _s ) where the Cgs channel is part of the gate source capacitance attributable only to that channel and v _s is the saturation electron velocity.

2) Drain Terminal Voltage Excitation

A small +/- voltage delta is applied around the same bias condition as in a), but this delta is applied across the drain source terminal.

b) equivalent circuit element Rds = 1 / {delta (Ids) / delta (Vds ')}, where Vds' is mostly an applied voltage delta, but also a voltage dropped across both the gate source access region and the gate drain access region Minus

c) The equivalent circuit element Cds can be taken as the sum of the appropriate fringe capacitance semi-physical models or in the form of delta (Nsd) / delta (Vds') * Xsat, where Nsd is the appropriate source charge boundary and drain charge The charge control equation for charge accumulation between boundaries, and Xsat is the length of the saturated region if it is saturated.

3) On-Mesa Parasitic Elements: Equivalent circuit elements Rs and Rd are represented by appropriate electrical conduction models of the source access region and the drain access region.

RF performance can be predicted at any bias point.

Table 3 shows a comparison of the values for the semi-physical modeling for the samples shown in Table 2 and the values for the high frequency equivalent circuit model derived from the extraction of the equivalent circuit model from this semi-physical modeling.

Comparison of Modeled Equivalent Circuit Results and Equivalent Circuit Model Extraction for Semi-Physical Modeling Methods Intrinsic equivalent circuit parameter Equivalent circuit model Semi-Physical Device Model Cgs 0.227745 pF 0.182 pF Rgs 64242Ω Infinity Cgd 0.017019 pF 0.020 pF Rgd 133450 yen Infinity CDs 0.047544pF 0.033pF Rds 160.1791Ω 178.1Ω Gm 135.7568mS 124mS Ri 3.034Ω 2.553Ω Tau 0.443867 pS 0.33 pS

The result of the semi-physical modeling method in this case produces a smaller signal equivalent circuit value that is relatively more accurate than a physical device simulator. Moreover, given the difference in parasitic embedding processing of the two approaches, the results given in Table 2 produce much closer results than the comparison of equivalent circuit values.

Table 3 lists the values of parasitic elements used to derive the model. An important difference between the extracted equivalent circuit model and the semi-physically derived circuit model is the use of Cpg and Cpd to model the effect of launch capacitance on the tested structure. This difference causes the results of the extracted model to deviate slightly from the optimal physically meaningful solution.

Comparison of modeled "parasitic" equivalent circuit results and equivalent circuit model extraction for a semi-physical modeling method Exogenous equivalent circuit parameters Equivalent circuit model Semi-Physical Device Model Rg 1.678 yen 1.7 Ω Lg 0.029314nH 0.03nH Rs 1.7 Ω 1.21Ω Ls 0.002104nH 0.003nH Rd 3.309899Ω 5.07Ω Ld 0.031671nH 0.02nH Cpg 0pF 0.02 pF Cpd 0pF 0.01 pF

As shown in FIGS. 13, 14, and 15, the modeled results simulated using a semi-physically derived equivalent circuit model replicate the measured high frequency S-parameter data very accurately. .

Equation 12 below shows the small-signal excitation derivation of Gm modeled as a small-signal equivalent circuit. 56 shows a semi-physically simulated bias equation of small signal Gm relative to the measured data.

Equation 12

Equation 13 below shows the small-signal excitation derivation of Rds. 57 shows the semi-physically simulated bias-dependency of small-signal Rds.

Equation 13

The following equation 14 can be used for small-signal excitation derivation of Cgs and Cgd. 58 shows the semi-physically simulated bias-dependency of small-signals Cgs and Cgd.

[Equation 14]

The following equation (15) involves the small-signal excitation derivation of Ri. 59, which follows, illustrates the semi-physically simulated bias-dependency of small-signal Ri.

[Equation 15]

Semi-Physical Models and Examples of Bias-Dependent Small-Signal Source and Drain Resistors (Rs and Rd)

FIG. 60 shows the semi-physically simulated bias-dependency of on-mesa parasitic access resistors Rs and Rd.

The following example verifies how a semi-physical small-signal device model can provide accurate projection of bias-dependent small-signal performance. In this example, the same semi-physical device model as used in the previous example was used because the MMIC circuit of the example was manufactured using the same HEMT device technology.

In this example, the bias-dependent small-signal gain and noise performance of a two-stage balanced K-band MMIC LNA amplifier is the small signal and noise generated by the semi-physical model. The equivalent circuit is replicated through microwave circuit simulation. The results of the measurement results and the modeling results are shown below in Table 4. As seen from these results, the semi-physical device model was able to accurately simulate the measured bias-dependent performance, even though the bias variation was quite wide.

Gain and NF measured at 23.5 GHz for K-band MMIC LNA under differential bias conditions and modeled gain and NF Bias condition Gain measured at 23.5 GHz Predicted Gain at 23.5 GHz NF measured at 23.5 GHz NF predicted at 23.5 GHz Vds = 0.5V112mA / mm 15.2 dB 15.8 dB 2.97 dB 2.77 dB Vds = 1.0V112mA / mm 20.6 dB 21.0 dB 2.29 dB 2.20 dB Vds = 2.0V112mA / mm 19.8 dB 20.2 dB 2.25 dB 2.15 dB Vds = 3.0V112mA / mm 18.9 dB 19.1 dB 2.30 dB 2.11 dB Vds = 3.5V112mA / mm 18.4 dB 18.5 dB 2.34 dB 2.18 dB Vds = 4.0V112mA / mm 18.0 dB 18.0 dB 2.37 dB 2.27 dB Vds = 2.0V56mA / mm 16.4 dB 18.0 dB 2.45 dB 2.21 dB Vds = 2.0V170mA / mm 21.4 dB 20.9 dB 2.38 dB 2.21 dB Vds = 2.0V225mA / mm 22.2 dB 21.0 dB 2.65 dB 2.6 dB Vds = 3.0V225mA / mm 21.4 dB 20.3 dB 2.71 dB 2.61 dB Vds = 3.0V170mA / mm 20.5 dB 20.0 dB 2.42 dB 2.22 dB Vds = 4.0V170mA / mm 19.6 dB 19.2 dB 2.50 dB 2.29 dB

A plot of the measured gain versus modeling gain for the values listed in Table 4 above is shown in FIG. 61.

The following example verifies how the semi-physical small-signal device model can provide accurate projection for the physically dependent small-signal performance. In this example, the same semi-physical device model as used in the previous example was used.

In this example, physical processor variations were input to the semi-physical device model in terms of statistical variations regarding known mean, cross correlation, and standard deviation. The purpose of this exercise was to replicate the measured DC and small-signal device variations. The exact degree of replication indicates the degree to which the anti-physical model is physically accurate.

Table 5 below lists the simulated known process variations that were used.

Statistical Process Variation Model parameter Nominal value Standard Deviation Gate length 0.15㎛ 0.01 μm Gate-source recess 0.16 μm 0.015 μm Gate-drain recess 0.24 μm 0.020 μm Etching depth 780A 25A Passivation Nitride Thickness 750 A 25A Gate-source spacing 0.7 μm 0.1 μm Source-Drain Interval 1.8㎛ 0.15㎛

In the microelectronic component manufacturing process, a sample device is tested in the process to obtain statistical process control monitor (PCM) data. 18 schematically shows the type of data extracted and recorded from the device I-V data measured during PCM testing.

Because the semi-physical device model can simulate I-V data, the device model could simulate variations in I-V data due to physical process variations. These I-V data were analyzed in the same way to extract the same parameters recorded for PCM testing. 63, 64, and 65 show how exactly the simulated results match the measured process variation. 63 shows how the semi-physically simulated Vgpk and Gmpk match the measurements of the actual product. 64 also shows how consistent the simulated Idpk and Gmpk are. Finally, Figure 65 shows how well the simulated Imax and Vpo also match.

Small-signal S-parameter measurements are also taken in the process for process control monitoring. These measurements are used to extract a simple equivalent circuit model that fits the measured S-parameters. Because the semi-physical device model can simulate these equivalent circuit models, the device model could simulate variations in model parameters due to physical process variations.

66 and 67 show how exactly the measured / extracted process variation and simulation results correspond to the small-signal model parameters. FIG. 66 shows how well the semi-physically simulated Rds and Gm coincide with the actual extracted model process variation.

More direct and robust evidence supporting the exact physical properties of the semi-physical model can be found by comparing the dependence of the actual physical variables with the simulated and measured performance. As shown in FIG. 68, the semi-physical model can very accurately reproduce the dependence of Imax on the gate length. In addition, the semi-physical model may replicate the physical dependence on the high-frequency small-signal equivalent circuit. This is shown in FIG. 69, which shows that it is possible to reproduce the dependency of Rds with the recess undercut width.

S-parameter microscopy

The S-parameter microscopy (SPM) method uses bias-dependent S-parameter measurements in the form of microscopy to provide qualitative analysis of the internal charge and electric field structure of semiconductor devices that have not been known so far. Pseudo images are collected in the form of S-parameter measurements extracted with a small signal model to form a charge control map. Finite element device simulations have been used to calculate the internal charge / field of semiconductor devices so far, but this method is known to be relatively inaccurate. S-parameter microscopy provides a relatively accurate method for determining the internal charge and electric field in a semiconductor device. Given the accurate modeling of the internal charge and the electric field, all of the external electrical characteristics of the semiconductor device can be modeled relatively accurately, including the high frequency performance of the device. Thus, the system is suitable for creating device technology models that enable the prediction and design of high frequency MMIC yield analysis for manufacturing analysis.

S-parameter microscopy is similar to other microscopy techniques in that the SPM uses measurements of the energy reflected from the sample and energy from the sample to derive information. More specifically, the SPM is based on the transmitted and reflected microwave and millimeter wave electromagnetic power, or S-parameters. As such, S-parameter microscopy is similar to the combined operation of scanning and transmission electron microscopy (SEM and TEM). The scattered RF energy is similar to the reflectance and transmittance of the electron beam in SEM and TEM. However, instead of using an electronic detector as in SEM and TEM, a reflectometer in the network analyzer is used in the S-parameter microscopy to measure the signal. S-parameter microscopy both use a measurement of scattering phenomena as data and include a mechanism for focusing the measurement for better resolution, and as detailed in Table 6 below It is similar to other microscopy techniques in that it includes a mechanism for contrasting the measured parts.

Common microscope S-parameter microscope Measurement of scattering energy Measurement of S-parameters Mechanism for " focus " Focuses by Extracting Unique Equivalent Circuit Models Mechanism for " contrast " Contrast using bias dependencies to finely distinguish the characteristics and location of charge / field

result : "Image" of the internal charge and electric field structure of the device

In conjunction with S-parameter microscopy, the image as discussed herein is not related to the actual image, but is used to provide insight and qualitative details about the internal operation of the device. More specifically, S-parameter microscopy does not provide a visual image, as is the case with traditional forms of microscopy. Rather, the S-parameter microscopy image is more similar to a map calculated based on a non-intuitive set of measurements.

16 shows a conceptual representation of an S-parameter microscope, generally identified by reference numeral 20. The S-parameter microscope 20 is similar to a microscope that combines the principles of SEM and TEM. The SEM measures the reflectance and the TEM measures the transmittance, while the two-port S-parameter microscope 20 measures both the reflected power and the transmitted power. As a result, the data derived from the two-port S-parameter microscope includes information about the intrinsic and extrinsic charge structures of the device. More specifically, as is known in the art, SEM provides a relatively detailed image of the sample plane through reflective electrons, while TEM provides an image of the internal structure through transmitted electrons. Reflected signals are used to form external details of the sample, while transmitted electrons provide information about the internal structure of the device. In accordance with an important aspect of the present invention, S-parameter microscopy uses a process to measure reflected and transmitted signals to provide a similar “image” of the charge structure of a semiconductor device. As used herein, the internal and external electrical structures of the semiconductor device are commonly referred to as intrinsic device regions 22 and exogenous parasitic access regions 24, as shown in FIG. Also contributing to the external electrical structure of the device are the parasitic components associated with the electrodes and their interconnections which are not shown. These are the so-called "layout parasitics" of the device.

Referring to Figure 16, ports 26 and 28 are emulated with S-parameter measurements. S-parameter measurements are generally processed in accordance with the present invention to provide a charge control map shown in a circle 32 similar to an image in other microscopy techniques for a particular semiconductor device identified generally by the reference numeral 30. As discussed in more detail below, these charge control maps 32 are represented in the form of equivalent circuit models. As shown in FIG. 18, linear circuit elements may be used in the model to represent the state and magnitude of the charge / field in semiconductor device 30 or the so-called internal electrical structure of the semiconductor device. The location of the circuit elements in the model topology is approximately close to the physical location in the device structure, so that the charge control map shows a diagram of the internal electrical structure of the device.

The interpretation of the exact position of the charge / field measured in the semiconductor device is used to represent the distribution structure of the charge / field in the actual device, for example, as shown in FIG. 19, with an equivalent circuit model having separate linear elements. It is known to be ambiguous. Although no precise method exists for separating physical boundaries between measured quantities, bias dependencies are used to clarify how S-parameters should be distinguished, separated, and collated. In particular, changing the bias condition is known to change the magnitude and movement boundary between the charge and the electric field in the device. The change is normally predictable and qualitatively well known in most techniques. As such, the charge control map can be readily used as a map showing the characterization of the physical changes in the magnitude, position, and separation of the electric charge and the electric field.

Similar to other forms of microscopy, the S-parameter microscope 20 according to the present invention emulates a lens identified by reference numeral 40 (FIG. 16). Lens 40 is simulated by a method for the extraction of a unique equivalent circuit model that also accurately simulates the measured S-parameters. More specifically, parameter extraction methods for equivalent circuit models that simulate S-parameters are relatively well known. However, its sole purpose is to have an infinite number of possible solutions for equivalent circuit parameter values when fitting the S-parameters to measure accurately. Thus, in accordance with an important aspect of the present invention, only one unique solution is extracted that accurately describes the physical charge control map of the device. The present method for unique extraction of equivalent circuit model parameters serves as a lens to focus the charge control map solution. As discussed and illustrated herein, lens 40 is subsequently simulated by a filter based on a clear layout parasitic embedding model. As discussed below, the layout parasitic embedding model consists of linear elements that simulate the effects of the electrodes and interconnections of the device on the external electrical properties of the device. The π-FET embedding model 42 is described below. This model acts as a filter to effectively remove the electrical structure of exogenous parasitic access contributions to the preliminary charge control map solution. The resulting filtered charge control map solution shows a sharper "image" showing only the electrical structure of the native device. This enhanced image is required to achieve the view of the internal charge / field as accurately as possible. Unlike conventional extraction techniques as shown in FIG. 21 which only extracts a non-unique equivalent circuit model and does not extract a unique charge control map, the S-parameter microscope 20 according to the present invention is a semiconductor device. The internal charge / field structure within can be modeled with relative accuracy.

Exemplary applications of S-parameter microscopes are shown in detail below. In this example, an exemplary GaAs HEMT device with four gate fingers and a total gate periphery of 200 μm formed in a π-FET layout as shown generally in FIG. 31 and identified by reference numeral 43 is shown. GaAS HEMT 43 is adapted to be embedded in a coplanar test structure with a 100 μm pitch to facilitate S-parameter measurements in water.

Initially, as shown in FIGS. 23 and 24, I-V characteristics for the device are measured. In particular, the drain source current Ids is shown as a function of drain to source voltage Vds at various gate voltages Vgs, as shown in FIG. FIG. 24 shows drain to source current Ids as a function of gate voltage Vgs and transconductance Gm (ie, derivative of Ids over Vgs) at various drain voltages Vds. These I-V characteristics represent HEMT devices and most semiconductor devices, which are one type of semiconductor device technology with three terminals.

Table 7 shows the bias conditions under which the S-parameters were measured. S-parameters were measured at 0.05-40 GHz under each bias condition. FIG. 25 shows a Smith chart showing S-parameters S11, S12, and S22 measured for frequencies of 0.05-40.0 GHz. FIG. 26 graphically shows magnitude as a function of angle for S-parameter S21 measured for frequencies of 0.05-40.0 GHz.

Measured S-Parameter Bias Conditions bias Vds = 0V Vds = 0.5V Vds = 1.0V Vds = 2.0V Vds = 4.0V Vds = 5.0V Vgs -1.6V Yes Yes Yes Yes Yes Yes -1.4V Yes Yes Yes Yes Yes Yes -1.2V Yes Yes Yes Yes Yes Yes -1 V Yes Yes Yes Yes Yes Yes -0.8V Yes Yes Yes Yes Yes Yes -0.6V Yes Yes Yes Yes Yes Yes -0.4V Yes Yes Yes Yes Yes Yes -0.2V Yes Yes Yes Yes Yes Yes 0 V Yes Yes Yes Yes Yes Yes 0.2V Yes Yes Yes Yes Yes Yes 0.4 V Yes Yes Yes Yes Yes Yes 0.6 V Yes Yes Yes Yes Yes Yes

Using the small signal model shown in FIG. 19, the extracted small signal equivalent circuit values are obtained as shown in Table 8 for each S-parameter under each bias condition, using the extraction method discussed below.

ㅣ ㅣ

The values in Table 8 represent solutions close to the charge control map and represent physically meaningful solutions of the electrical structure of the FETs. However, the values shown in Table 8 include the effects of external layout parasitics, subtracted using a model for embedding parasitics to obtain the most accurate charge control mapping to intrinsic device characteristics. In particular, the embedding model is applied to filter the extracted equivalent circuit model values and to obtain values that better represent the unique device. In particular, in the exemplary embodiment, the π-FET embedding parasitic model is used to subtract the capacitive contribution due to the intermediate electrode and off-mesa layout parasitic effects. This filter essentially subtracts a known amount formed of different parameters (Cgs, Cgd, and Cds) depending on the device layout involved. In this example, embedding of inductive parameters is not necessary because these amounts are exogenous and do not contribute to the charge control map of the inherent device.

As discussed above, a lens with a filter is used to generate a unique charge control map. In particular, FIGS. 27-30 show bias dependent charge control maps for parameters RS, RD, RI, CGS, and CGD as a function of bias. More specifically, FIG. 27 shows the charge control map and electric field distribution of charge in the on-mesa source access region shown by the source resistance Rs as a function of bias. FIG. 28 shows the charge control map and electric field distribution of charge in the on-mesa drain access region shown by the drain resistor Rd as a bias function. FIG. 29 shows the charge control map for non-quasistatic multi-carrier transfers shown by the intrinsic device charge resistance Ri as a function of gate bias for different drain bias points. 30 shows a charge control map for the gate modulated charge and distribution under the gate shown as gate capacitances CGS and CGD as a function of bias.

filter

As mentioned above, the S-parameter microscope 20 uses a filter to provide a clearer charge control map that models the internal charge / field of the semiconductor device. Although the filter is shown in conjunction with a? FET with multiple gate fingers as shown in Figures 31 and 32, the principles of the present invention are applicable to other semiconductor devices.

As shown in FIG. 31, π-FET is a device in which the edge and gate finger of the active region are similar to the Greek letter π, as shown. This π-FET layout facilitates the construction of a multi fingered large periphery device cell, for example, as shown in FIG. According to an important aspect of the present invention, semiconductor devices of multiple fingers are modeled as a combination of device cells of a single finger. The device cells of each single finger are represented by a hierarchy of four models, which are in turn assembled with each other using the model to interconnect to represent any multi-fingered device cells shown in FIG. 33. The four models are the same as offmesa or peripheral parasitic models, mutual electrode parasitic models, on-mesa parasitic models, and intrinsic models.

The off-mesa parasitic model is shown in FIG. 34. This model represents the parasitics present outside the active FET region for each gate finger. In this model, the fringing capacitance of each gate finger outside the active device region as well as the off mesa gate finger resistance is modeled.

The mutual electrode parasitic model and its equivalent circuit are shown in FIGS. 35-37. This model exhibits parasitics between metal electrodes along each gate finger. The following fringe capacitance parasitics, as shown generally in FIG. 36, are gate to source air bridges, drain to source air bridges, and gate to source ohms. Modeled for resistance, gate to drain ohmic resistance, and source to drain ohmic resistance.

The on-mesa parasitic model and its equivalent circuit are shown in FIGS. 38 and 39. This model represents the parasitics around the active FET region along each gate finger, which includes several capacitance fringe parasitics and resistive parasitics. In particular, gate to source side recesses, gate-drain-side recesses, gate source access charge / doped caps, and gate-drain access charge / doped cap capacitance fringe parasitics are modeled. Moreover, gate metallization and ohmic contact resistance parasitics are modeled.

The intrinsic model and its equivalent circuit are shown in FIGS. 40 and 41. Inherent models represent the physical characteristics that predominantly determine FET performance. In particular, the DC and current voltage responses are described by, for example, Hughes et al., "NONLINEAR CHARGE CONTROL IN AlGaAs / GaAs MODULATION-DOPED," for example, by Hughes et al. FETs) ", IEEE Bulletin, Electronic Devices (Vol. ED-34, No. 8), by means of analytical equations based on physical properties of the position and magnitude of intrinsic charges generally known in the art Can be determined. Small signal model performance is modeled by taking the derivative of the appropriate charge or current control equation to derive various conditions such as RI, RJ, RDS, RGS, RGD, GM, TAU, CGS, CDS, and CGD. Such control equations are generally known in the art and are described in detail in the aforementioned Hughes et al., Which are incorporated herein by reference. Noise performance is described by H. Statz et al., "Noise Characteristics of Gallium Arsenide Field-Effect Transistors," (IEEE-Bulletin, Electronic Devices, Vol. ED-21, No. 9, and by A. Van Der Ziel, March 1963, "Gate Noise in Field Effect Transistors at significantly higher frequencies. Moderately High Frequencies ”, (IEEE Publication, Vol. 51), September 1974, H. "Gate Noise in Field Effect Transistors at Quite High Frequencies" by Starts , ( IEEE Bulletin, Electronic Devices , Vol. ED-21, No. 9) and "Galium Arsenide," by Starts et al., 1974, September. Noise characteristics of field effect transistors ", (current IEEE voltage electronic device , Vol. ED-21, No. 9) or by voltage perturbation analysis.

Examples of parasitic models for use with the S-parameter microscopy discussed above are shown in FIGS. 42-49. Although certain embodiments of semiconductor devices are shown and described, the principles of the present invention are applicable to various semiconductor devices. Referring to Fig. 42A, π-FET is shown. As shown, the π-FET has four gate fingers. A four-fingered π-FET is modeled in FIG. 42B. In particular, FIG. 42B shows an equivalent circuit model for the π-FET shown in FIG. 42A, as implemented by a known CAD program of LIBRA 6.1, for example, manufactured by AGE Technologies. . As shown, the equivalent circuit model does not depict all of the network connections or equivalent circuit elements associated with implementing the parasitic embedding model, but rather illustrates the final product. Actual technical information regarding the configuration of the network and its equivalent circuit elements is typically provided in a schematic drawing. An important aspect of parasitic modeling relates to the modeling of a device with multiple gate fingers into a single gate finger device. As used herein, a single unit device cell refers to a device associated with a single gate finger. For example, as shown in FIG. 42A, a four-fingered π-FET is modeled into four unit device cells.

Initially, the four-fingered π-FETs shown in FIG. 42A are modeled as a single finger unit device cell 100 with a unique model 102, as shown in FIGS. 43 and 44. In particular, the π-FET native FET model 104 is replaced with block 102 defining the first embedding level. As shown in FIG. 44, the parameter values for the π-FET eigen model are added together with the parameter values for the unit device cell eigen model with a single finger. The unique device model 104 may be developed by S-parameter microscopy, as discussed above. Next, as shown in FIG. 45, the interconnect layout parasitics are equivalent by simply adding a model term to the value of the appropriate circuit element to form a single unit device cell defining the second embedding level. Is added to the model. Once a single unit device cell has been formulated, the device is used to construct a model for multiple fingered devices. In this case, the π-FET with four gate fingers is modeled into four single finger device unit cells as shown in FIG. Thereafter, the off-mesa layout parasitic element is connected to a plurality of fingered layouts that define a third embedding level, as shown in FIG. 47. These off-mesa layout parasitic elements, generally identified 108 and 110, are implemented as new circuit elements connected to major external nodes of the equivalent circuit structure. Subsequently, the fourth embedding level is implemented as shown generally in FIG. 48. In particular, the inductor model is connected to each source of the various unit device cells to represent a metal bridge interconnect, as generally shown in FIG. 48. Finally, as shown in FIG. 49, the fifth embedding level in which the feed electrode models 114 and 116 are modeled as a distribution element (ie, microstrip lines and junctions) as well as a mass of linear elements (capacitors, inductors). This is implemented to form the gate feed and drain connections shown in FIG. As shown, the distribution element is a distribution model for microstrip elements, as implemented in LIBRA 6.1.

Extraction Method for Unique Determination of FET Equivalent Circuit Model

As discussed above, a method of determining FET equivalent circuit parameters is shown in FIGS. 50-55. The method is based on an equivalent circuit model, such as the common source FET equivalent circuit model shown in FIG. Referring to FIG. 50A, a model is initially generated at step 122. According to an important aspect of this algorithm, the equivalent circuit parameters are based on the measured FET S-parameters. Measurement of S-parameters of semiconductor devices is well known in the art. 53A is a Smith chart showing S-parameters S11, S12, and S22 measured by example for frequencies between 0.05 and 40.05 GHz. 53B shows a magnitude angle chart for the S-parameter S21 measured from a frequency of 0.05-40 GHz. As disclosed in step 124 (FIG. 50A), after the S-parameter is measured, it is confirmed whether the measurement is suitable for step 126. This is done by manually checking the test results for anomalies or by algorithms that verify the test set. If the measurement is suitable, the S-parameter measurement is stored at step 128.

For example, as shown in Table 9, a space of experimental starting feedback impedance point values is selected. At this point, a direct model attraction algorithm, known as the Minasian algorithm, is used to generate a preliminary value for the equivalent circuit model parameter for each value of the starting feedback impedance. This extraction algorithm, e.g., 1990,, "FET small crystal of broadband small-signal equivalent circuit (Broadband Determination of the FET Small Small Signal Equivalent Circuit)" due to July, Kerberos (M. Berroth), (IEEE- As is disclosed in MTT , Vo. 38, No. 7), it is well known in the art. Model parameter values are determined for each of the starting impedance point values shown in Table 3. In particular, referring to FIG. 50A, each impedance point in Table 9 is processed by blocks 130, 132, etc. to develop model parameter values for each impedance point in order to develop an error metric. This error metric, in turn, is used to develop a unique small signal device model, as discussed below. The processing at each block 130, 132 is similar. Thus, only a single block 130 is discussed for the example impedance points shown in Table 9. In this example, a feedback impedance point 17 is used that correlates the source resistance RsΩ of 1.7Ω and the source inductance Ls of 0.0045 pH.

Test start feedback, impedance space point value Impedance point Resistance (Rs) Inductance (Ls) One 0.1Ω 0.0045pH 2 0.2Ω 0.0045pH 3 0.3 Ω 0.0045pH 4 0.4 Ω 0.0045pH 5 0.5 Ω 0.0045pH 6 0.6 Ω 0.0045pH 7 0.7Ω 0.0045pH 8 0.8 Ω 0.0045pH 9 0.9 Ω 0.0045pH 10 1.0Ω 0.0045pH 11 1.1Ω 0.0045pH 12 1.2Ω 0.0045pH 13 1.3Ω 0.0045pH 14 1.4Ω 0.0045pH 15 1.5 Ω 0.0045pH 16 1.6 Ω 0.0045pH 17 1.7 Ω 0.0045pH 18 1.8Ω 0.0045pH 19 1.9Ω 0.0045pH 20 2.0Ω 0.0045pH 21 2.1Ω 0.0045pH 22 2.2 Ω 0.0045pH 23 2.3 Ω 0.0045pH 24 2.4 Ω 0.0045pH 25 2.5 Ω 0.0045pH 26 2.6 Ω 0.0045pH 27 2.7 Ω 0.0045pH 28 2.8Ω 0.0045pH 29 2.9 Ω 0.0045pH 30 3.0Ω 0.0045pH

For the selected value Rs = 1.7 Ω, the initial intrinsic equivalent circuit parameters and the initial parasitic equivalent circuit parameters are determined, for example, by the Minasian algorithm mentioned above, and described in Table 10 and as described in steps 134 and 136. It is shown in Table 11. In step 138, the simulated circuit parameters are compared with the measured S-parameters, as shown, for example, in FIGS. 54A and 54B. Each of the processing blocks 130, 132, etc., passes through a number of completion cycles, in this example six completion cycles. As such, the system determines in step 140 whether six cycles have been completed.

Initial "Unique" Equivalent Circuit Parameters Intrinsic equivalent circuit parameter Initial solution Cgs 0.23595 pF Rgs 91826Ω Cgd 0.0177 pF Rgd 100000Ω CDs 0.04045 pF Rds 142.66Ω Gm 142.1025mS Tau 0.1 pS

Initial "parasitic" equivalent circuit parameters Intrinsic equivalent circuit parameter Initial solution Rg 3.0Ω Lg 0.014nH Rs 1.7 Ω Ls 0.0045nH Rd 2.5 Ω Ld 0.024nH

Each cycle of processing block 130 consists of a direct extraction followed by optimization with a certain number of optimization iterations, eg, 60 optimization iterations. By fixing the number of extraction optimization cycles along with the number of optimization iterations, the fixed "distance" or computational time at which the model solution should be derived is limited. As such, the algorithm achieves the lowest fitting error over a fixed computational time, allowing the "race" criteria to be implemented, thereby constructing an environment in which each experimental model solution competes with each other to determine the overall error metric. Implement the convergence rate requirement, where the "convergence rate" is implicitly calculated for each processing block 130, 132, and so on.

After the system determines whether racing has completed in step 140, the system proceeds to block 142 and optimizes the model parameters. Many commercial software programs are also available. For example, commercially available LIBRA 3.5 software, such as manufactured by HP-eesof, can also be used both for optimizing functions as well as for circuit simulation. In addition to fixing the feedback resistor Rs to a fixed value, optimization is performed according to the constraints described in Table 12.

Environment used for competitive solution strategy, as implemented in this example Implementation parameters Circuit Simulators and Optimizers Libra 3.5 Optimal algorithm Gradient Optimal error metrics Sizes and angles of S11, S21, S12 and S22 from 4 to 40 GHz Number of iterations 60 Number of extraction / optimization cycles 6

By fixing the value for Rs, this segment of the algorithm was limited to creating a test model solution only for the test feedback impedance point at which the test model solution begins. Table 13 shows intrinsic equivalent parameter values optimized using commercially available software, such as LIBRA 3.5. These values along with the optimized parasitic values, illustrated in Table 14, form the first optimized model solution for the first extraction-optimization cycle (ie, one of six). The optimized model parameters are then fed back to the function blocks 134 and 136 (FIG. 50A) used in the new initial model solution. These values are compared with the measured S-parameter values as shown in FIGS. 54A and 54B. The system repeats this cycle for six cycles in a similar manner as mentioned above. After six extraction-optimization cycles, the final test model solution for the test impedance point 17 is completed with the final fitting error for the measured data to form a new error metric 144. According to an important aspect, the extraction-optimization algorithm allows the final optimization fitting error for each point to have information about the measured error versus model fitting error and convergence rate. This algorithm does so by a fixed optimization time constraint that constitutes a competitive race between several test model solutions.

Optimized "Unique" Equivalent Circuit Parameters Intrinsic equivalent circuit parameter Initial solution Cgs 0.227785 pF Rgs 65247 yen Cgd 0.017016pF Rgd 130820Ω CDs 0.047521pF Rds 160.18 yen Gm 135.74mS Tau 0.446 pS

Optimized "parasitic" equivalent circuit parameters Intrinsic equivalent circuit parameter Initial solution Rg 4.715Ω Lg 0.02903 nH Rs ^* 1.7 Ω Ls 0.002102nH Rd 3.2893 yen Ld 0.0317nH

Implementation of the extraction optimization cycle allows the best and fastest solution to appear as the overall minimum value for the final fitting error at step 146 of both test impedance points, as generally shown in FIGS. 51 and 52. More specifically, referring to FIG. 51, the overall minimum solution using the new error metric is found around Rs = 1.7Ω. Tables 15 and 16 list the final model equivalent circuit parameters for this overall solution, including eigen and parasitic parameters, as disclosed in step 148 (FIG. 50B).

Universal solution for "unique" equivalent circuit parameters Intrinsic equivalent circuit parameter Initial solution Cgs 0.227745 pF Rgs 64242Ω Cgd 0.017019 pF Rgd 133450 yen CDs 0.047544pF Rds 160.1791Ω Gm 135.7568mS Tau 0.443867 pS

Universal solution of "parasitic" equivalent circuit parameters Exogenous equivalent circuit parameters Initial solution Rg 4.711895Ω Lg 0.029314nH Rs 1.7 Ω Ls 0.002104nH Rd 3.309899Ω Ld 0.031671nH

To test the accuracy of this solution, the final model for the solution is compared with the measured S-parameter values as shown in FIGS. 55A and 55B. As shown, there is a good correlation between the simulation model values and the measured S-parameter values, thus verifying that the simulated model values are relatively accurate and represent a unique small signal device model.

Obviously, many modifications and variations of the present invention will be possible from the above description. Accordingly, within the scope of the appended claims, the invention may be practiced otherwise than as specifically described above.

Claims to be made by the patent literature are as follows.

As described above, the present invention provides a method of modeling a semiconductor device using a semi-physical device model combined with an analytical thermal resistance model to self-consistently solve the channel temperature and internal charge / field structure of the semiconductor device. Used for

Claims (10)

(a) modeling the semiconductor device with a semi-physical model; (b) modeling the semiconductor device with an analytical thermal model; (c) combining the semi-physical model and the analytical thermal model, Semiconductor device modeling method comprising. The method of claim 1, further comprising: (d) determining an internal charge / field structure of the semiconductor device. The method of claim 1, wherein the semi-physical model is configured to replicate measured direct current (DC) current-voltage (I-V) characteristics. 4. The method of claim 3, wherein the semi-physical model is further configured to replicate bias dependent small signal characteristics. The method of claim 4, wherein the semi-physical model is configured to replicate the DC I-V and bias dependent characteristics. The method of claim 1, wherein step (b) comprises (e) measuring DC I-V characteristics and S-parameter small signal parameters over a predetermined temperature range. 7. The method of claim 6, further comprising: (f) deriving a small signal equivalent circuit model for each S-parameter measurement as a function of temperature. 8. The method of claim 7, further comprising: (g) developing temperature coefficients to adjust the semi-physical device model to match the measured DC and S-parameter measurements at each temperature. . The method of claim 1, wherein step (c) comprises (h) replacing the ambient temperature operating with any temperature dependent term and temperature coefficient with the channel temperature of the device. The method of claim 1, wherein step (c) comprises (i) using the length of the saturated region as the length of the heat generating region.