EP1285395A1 - Semi-physical modeling of hemt dc-to-high frequency electrothermal characteristics - Google Patents

Abstract

A method for modeling semiconductors which utilizes a semiphysical device model (figure 45) coupled with an analytical thermal resistance model to self consistently solve for the channel temperature and internal charge/electric field structure of the semiconductor device.

Description

SEMI-PHYSICAL MODELING OF HEMT DC-TO-HIGH FREQUENCY ELECTROTHERMAL CHARACTERISTICS

Cross-Reference to Related Applications

This application is a continuation-in-part and claims the priority of U.S. patent application no. 60/200,648, filed on April 28, 2000.

This application is related to the following commonly-owned co-pending patent application, Serial No. 09/680, 339, filed on October 5, 2000: METHOD FOR

UNIQUE DETERMINATION OF FET EQUIVALENT CIRCUIT MODEL PARAMETERS, by Roger Tsai. This application is also related to the following commonly-owned co-pending patent applications all filed on April 28, 2000, S- P ARAMETERMICROSCOPY FOR SEMICONDUCTOR DEVICES, by Roger Tsai, Serial No. 60/200,307, (Attorney Docket No. 12-1114); EMBEDDING PARASITIC

MODEL FOR PI-FET LAYOUTS, by Roger Tsai, Serial No. 60/200,810, (Attorney Docket No. 12-1116); SEMI-PHYSICAL MODELING OF HEMT HIGH FREQUENCYNOISE EQUIVALENT CIRCUIT MODELS, by Roger Tsai, SerialNo. 60/200,290, (Attorney Docket No. 12-1119); SEMI-PHYSICAL MODELING OF HEMT HIGH FREQUENCY SMALL-SIGNAL EQUIVALENT CIRCUIT MODELS, by Roger Tsai, Serial No. 60/200,666, (Attorney Docket No. 12-1120); HYBRID SEMI-PHYSICAL AND DATA FITTING HEMT MODELING APPROACH FOR LARGE SIGNAL AND NON-LLNEAR MICROWAVE/MILLIMETER WAVE CIRCUIT CAD, by Roger Tsai and Yaochung Chen, Serial No. 60/200,622, (Attorney DocketNo. 12-1127; andPM²: PROCESS PERTURBATION TO MEASURE MODEL

METHOD FOR SEMICONDUCTOR DEVICE TECHNOLOGY MODELING, by Roger Tsai, Serial No. 60/200,302, (Attorney Docket No. 12-1128). BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for modeling a semiconductor device and more particularly to a method of modeling the thermal and electrical characteristics of a semiconductor device which utilizes a semiphy scial device model coupled with an analytical thermal resistance model to self consistently solve for the channel temperature and internal charge/electrical field structure of the semiconductor device.

2. Description of the Prior Art HEMT technology provides RF components that have unparalleled, high performance characteristics at high frequencies (microwave to millimeter wave) and high power levels. As such, HEMTs are known to be used in various RF applications. Unfortunately, high power level applications also require high levels of DC power dissipation that elevates the HEMT components to high temperature levels. Currently, there are two predominant methods for modeling the electrothermal and thermal characteristics of HEMT device; finite element thermal simulation and physical device simulation

Finite element thermal simulations are used to simulate the lay out dependent thermal conducting characteristics of a semiconductor device. The simulation may be accomplished either by simulating the two dimensional cross section of the device lay out and then assuming semi-infinite thermal conditions in the orthogonal direction; so called quasi-three dimensional modeling; or fully simulating the three dimensional device layout. Because the full three dimensional approach requires much more computational power and sophisticated software, the quasi-three dimensional approach is known to be in more common use. A typical example of this approach is shown in

Fig. 1 which depicts a finite element mesh for a HEMT device layout. The device layout is typical of all HEMT devices.

Finite element thermal simulations are known to provide accurate estimations of a devices thermal conduction. However, the main draw back with this method is the inability to couple the calculated channel temperature of the device back to an electrical simulation in order adjust the electrical characteristics of the device. In addition, this approach assumes a heat source, typically DC power dissipated within the intrinsic device which remains constant. However, in reality the DC power dissipation also changes with temperature. Thus, for an accurate electrothermal simulation, the so- called self heating effect must be taken in account.

As mentioned above, the full electrothermal characteristics canbe simulated from so-called physical device simulators. Physical device simulators are known to utilize comprehensive knowledge about material characteristics and basic device physics to simulate the physical operation within the structure of the device. Usually simulators are based upon finite element or Monte Carlo approaches- although the finite element approach is usually employed for electrothermal simulations that also incorporate thermal conduction. Because these tools use the physical structure to simulate performance, the correspondence between the simulated electrothermal performance and the devices physical characteristics are relatively strong. However, the ability of device simulators to accurately model real, measured high frequency electrical characteristics is relatively inaccurate. Usually such simulation tools are able to achieve fairly useable modeling of DC characteristics but cannot be used for accurate high frequency simulations. Thus, there is a need for an electrothermal semiconductor device model which provides relatively accurate results at high frequencies.

SUMMARY OF THE INVENTION

Briefly the present invention relates to a method for modeling semiconductor devices which utilizes a semiphysical device model coupled with an analytical thermal resistance model to self consistently solve for the channel temperature and internal charge/electric field structure of the semiconductor device. As such the method in accordance with the present invention can realistically simulate the response of electrical performance to temperature and vice versa of a semiconductor device.

DESCRIPTION OF THE DRAWINGS These and other advantages of the present invention will be readily understood with reference to the following specification and attached drawings wherein: FIG. 1 illustrates a known finite element mesh for a HEMT device layout. FIG.2 is a graphical illustration illustrating the measured semi-physical modeled

DC-IV characteristics at an ambrent temperature of 200° C.

FIG. 3 is similar to FIG. 2 but at an ambient temperature of 25°C. FIG. 4 is a graphical illustration illustrating the measured vs semi-phyically modeled DC-IV characteristics at an ambient temperature of 25°C for a self heating large periphery 8 fingered 600μm gate periphery device cell.

FIG. 5 is schematic diagram of an exemplary small signal equivalent circuit model for a HEMT device.

FIG. 6 is a sectional view of an exemplary HEMT illustrating the rough translation of the physical origins for each of the equivalent circuit elements illustrated in the small signal circuit model in FIG. 1.

FIG. 7 is a cross-sectional view of a HEMT illustrating the regions in the HEMT which correspond to the various circuit elements in the small signal equivalent circuit model illustrated in FIG. 5.

FIG.8 is an example of a relatively accurate measured-to-model I-V characteristics using the semi-physical modeling method in accordance with one aspect of the present invention. FIG.9 is a elevational view illustrating an epi stack for an exemplary HEMT.

FIG. 10 is a cross-sectional view of a HEMT and an exemplary epi stack.

FIG. 11 is a blown up diagram of the cross-sectional parameters pertaining to the T-gate geometry for the exemplary epi stack illustrated in FIG. 7.

FIG. 12 is a diagram of an electric conductance model used in the semi-physical example.

FIG. 13 is a Smith chart illustrating the measured vs modeled S -parameters S 11 , S12 and S22 simulated in accordance with the method in accordance with the present invention.

FIG. 14 illustrates the measured vs modeled values for the S21 parameter. FIG. 15 is similar to FIG. 14 but for the S12 S-parameter.

FIG. 16 represents an exemplary S-parameter microscope in accordance with the present invention.

FIG. 17 illustrates the internal and external regions of an exemplary HEMT device. FIG. 18 is similar to FIG. 16 but illustrates the approximate locations of the model elements in the HEMT FET device illustrated is FIG. 16.

FIG. 19 is a schematic diagram of a common source FET equivalent circuit model. FIG. 20 is an illustration of specific application of the S-parameter microscope illustrated in FIG. 16.

FIG. 21 is similar to FIG. 16 which demonstrates the inability of known systems to accurately predict the internal charge and electrical field structure of a semiconductor device.

FIG. 22 is a plan view of a four-fingered, 200μm GaAs HEMT device. FIG.23 is a graphical illustration illustrating the measured drain-to-source current I_ds as a function of drain-to-source voltage Vds for the sample FET device illustrated in FIG. 22. FIG. 24 is a graphical illustration illustrating the drain-to-source current I_ds and transconductance G_m as a function of the gate-to-source voltage V_gs of the sample FET device illustrated in FIG. 22.

FIG. 25 is a Smith chart illustrating the measured SI 1, S 12 and S22 parameters from frequencies of 0.05 to 40.0 GHz for the FET device illustrated in FIG. 22. FIG. 26 is a graphical illustration of the magnitude as a function of angle for the

S21 S-parameter for frequencies of 0.05 to 40 GHz for the exemplary FET illustrated in FIG. 22.

FIG. 27 is a graphical illustration of a charge control map of the charge and electric field distribution in the on mesa source access region shown with R_s as a function bias in accordance with the present invention.

FIG. 28 is a graphical illustration of a charge control map of charge and electric field distribution in the on-mesa drain access region shown with R_d as a function of bias in accordance with the present invention.

FIG.29 is a graphical illustration of a charge control map for the non-quasi static majority carrier transport, shown with Rj as a function of bias in accordance with the present invention.

FIG. 30 is a graphical illustration of a charge control map for gate modulated charge and distribution under the gate, shown with Cgs and Cgt as function of bias in accordance with the present invention. FIG. 31 is a plan view of an exemplary π-FET with two gate fingers.

FIG. 32 is a plan view of a π-FET with four gate fingers. FIG. 33 is an illustration of a π-FET parasitic model in accordance with the present invention. FIG. 34 is an illustration of an off-mesa parasitic model for a π-FET in accordance with the present invention.

FIG. 35 is an illustration of an interconnect and boundary parasitic model in accordance with the present invention for the π-FET with four gate fingers as illustrated in FIG. 32.

FIG. 36 is an illustration of an inter-electrode parasitic model in accordance with the present invention.

FIG. 37 is a schematic diagram of the inter-electrode parasitic model illustrated in FIG. 36. FIG. 38 is an illustration of an on-mesa parasitic model in accordance with the present invention.

FIG. 39 is a schematic diagram of the on-mesa parasitic model illustrated in FIG. 41.

FIG. 40 is an illustration of an intrinsic model in accordance with the present invention.

FIG. 41 is a schematic diagram of the intrinsic model illustrated in FIG. 40.

FIG. 42 A is an exemplary device layout of a π-FET with four gate fingers.

FIG. 42B is an equivalent circuit model for the π-FET illustrated in FIG. 42A.

FIG. 43 is a single finger unit device cell intrinsic model in accordance with the present invention.

FIG. 44 is similar to FIG. 43 and illustrates the first level of embedding in accordance with the present invention.

FIG. 45 is similar to FIG. 43 and illustrates the second level of embedding in accordance with the present invention. FIG. 46 is an equivalent circuit model of the π-FET illustrated in FIG. 42A in accordance with the present invention.

FIG. 47 is similar to FIG. 45 and illustrates the third level of embedding in accordance with the present invention.

FIG. 48 is similar to FIG. 45 and illustrates the fourth level of embedding in accordance with the present invention.

FIG. 49 is similar to FIG. 45 and illustrates the fifth level of embedding in accordance with the present invention. FIG. 50A and 50B is a flow chart of a parameter extraction modeling algorithm that forms a part of the present invention.

FIGS. 51 and 52 represent the error metric in accordance with the present invention. FIG 53A is a Smith chart illustrating the measured versus the initial model solutions for the Sll, S12 and S22 S-parameters from frequencies from 0.05 to 40.0 GHz.

FIG. 53B is a graphical illustration of angle versus magnitude for the initially modeled S-parameter S21 from frequencies of 0.05 to 40 GHz. FIG. 54A is a Smith chart illustrating the measured versus simulated S- parameters Sll, S12 and S22 for frequencies 0.05 to 40 GHz for the first extraction optimization cycle.

FIG. 54B is a graphical illustration of magnitude as a function of angle for the measure and first optimized model S-21 parameter for frequencies 0.05 to 40 GHz for the first optimization cycle.

FIG. 55 A is a Smith chart illustrating the measure as a function of the final model solution for S-parameters Sll, S12 and S22 for frequencies 0.05 to 40 GHZ for the final solution.

FIG. 55B is a graphical illustrations of the magnitude as a function of an angle for S-parameter S21 for the final model solution from frequency 0.05 to 40 GHz.

FIG. 56 is a graphical illustration of the semi-physically modeled vs measured small signal Gm.

FIG. 57 is a graphical illustration of the semi-physically simulated bias dependence of the small-signal output conductance Rds. FIG. 58 is a graphical illustration of the semi-physically simulated bias dependence of the small signal gate-source and gate-drain capacitance Cgs and Cgd.

FIG. 59 is a graphical illustration of the semi-physically simulated bias dependence of the small signal gate source charging resistance Ri.

FIG. 60 is a graphical illustration of the semi-physically bias dependence of the small signal source and drain resistance Rs and Rd.

FIG.61 is a graphical illustration of the measured vs modeled bias dependent gain at 23.5 Ghz for a K-band MMIC amplifier. FIG 62A and 62B are graphical illustration of the extracted parameters from measured device I-V's for process control monitor testing.

FIG. 63 is a graphical illustration of the measured vs semi-physically simulated process variation for Gmpk and Vspk. Fig. 64 is a graphical illustration of the measured vs semi-physically simulated process variation for Idpk and Gmpk.

FIG. 65 is a graphical illustration of the measured vs semi-physically simulated process variation for frnax and Vpo.

FIG. 66 is a graphical illustration of the measured/extracted vs semi-physically simulated process variation for the small signal equivalent model Rds and Gm.

FIG. 67 is a graphical illustration of the measured/extracted vs semi-physically simulated process variation for the small signal equivalent model Cgs and Gm.

FIG. 68 is a graphical illustration of the measured vs semi-physically simulated physical dependence for Imax as a function of physical gate length. Fig. 69 is a graphical illustration of the measured/extracted model vs semi- physically simulated physical dependence for Rds as a function of physical recess undercut width.

DETAILED DESCRIPTION The model in accordance with the present invention utilizes a semi physical device model that is coupled to an analytical thermal conductance model as a means of simulating the electrothermal performance characteristics of a semiconductor device. In particular, a semiphysical model for HEMT devices is demonstrated that is able to relatively accurately represent small signal, noise, non-linear and large signal characteristics. In order to incorporate temperature dependence and also layout dependence of thermal conductivity, the following procedure is utilized:

1) Derive a Semi-Physical device model that is able to replicate measured DC I-V characteristics and bias-dependent small-signal characteristics very accurately at room temperature. 2) Incorporate any known temperature dependence of material parameters.

3) Measure DC-IV' s and bias-dependent small-signal S-parameters across the desired range of temperatures. 4) Extract small-signal equivalent circuit models for each of the S-parameter measurement vs temperature. S-parameter microscopy as discussed below may be used to develop charge-control map solutions.

5) Develop temperature coefficient expressions that apply to the intrinsic device model expressions of the semi-physical model. These temperature coefficients must adjust the predictions of the semi-physical device model to match the measured DC and small-signal data at each temperature. In particular: a) I-V's must be matched. b) If conventional, prior art small-signal model extraction is performed, for example, Minasian extraction algorithms, as discussed in detail in

"Broad Band Determination of the FET Small-Signal Equivalent Circuit", by Berroth, et al., IEEE-MTT. Vol. 38, No. 7, My 1990. relative changes in the C-V's (capacitance- VS-voltage) must be matched by the semi- physical model predictions. c) If S-parameter microscopy is performed, absolute changes in the C-V's must be matched to the semi-physical model.

6) Implement an appropriate analytical thermal conduction model.

7) Couple the semi-physical device model and the analytical thermal conduction model by: a) Substituting the "environmental temperature" that operates in all of the temperature-dependent terms and temperature coefficients with "channel temperature" b) Using the semi-physically modeled length of the saturated region, XSAT, as the length of the heat-generating region.

As will be discussed below, the semiphysical HEMT model may be extended to perform full electrothermal device simulations. In accordance with the above, a semiphysical model mentioned in step 1 is discussed below. In step 2, reported thermal properties of the material systems used for the HEMT technology are incorporated into an appropriate material related expression of the semiphysical device model. These properties may be obtained from "GaAs, ALAs and AlxGal-xAs Materials Parameters For Use and Research and Device Applications" by S. Adachi, J.Appl. Phys, vol. 58, No. 3, August 1985, hereby incorporated by reference. In step number 3, the DC I-V and bias dependent S-parameters are measured for a standard device lay out across several base plate temperatures; for example -25°C, 25°C, 125°C and 200°C. In step 4, S-parameter microscopy is employed for each set of temperature dependent data. In step 5, a temperature compensation co-efficient is developed from reported material thermal dependance relationships, for example, as shown below.

Ambient Temperature Coefficient TCamb [] = 1.247Λ^_pa∞ + 1.5ln_y- 0.4ln_y ² + (T_ani,- 300)(-3.95-1.15*^^*0.0001 Room Temperature Coefficient TCref [] = 1.247Al_xspace + 1.5ln_y- 0.4ln_y ² + (273 - 300)(-3.95-1.15*Al_xspacβ)*0.0001

Temperature Coefficient Factor TCF [] =10-^/10^

Once the expression, TCF is applied to the appropriate semiphysical charge and

10 transport control equations, temperature dependent I-V and C-V characteristics are accurately fit. As shown, the equations below illustrate how key charge control and carrier transport relationships are enhanced to incorporate temperature dependence through the empirical temperature compensation term set forth below: v ^vds ^πnmax

Maximum Channel Charge N_maχ [cm^" ] H_chan / H_chanREF) * TC_F

=(N_S' + N_s )*(<_, + Δ shKpar * V_gte / Parasitic Charge Accumulation in the Donor Layer N_sDonor [cm^' ] (dj + Δdj - TCi;)

Saturation Velocity V_s [cm/s] 1.47E+07*TC_F

15

FIG. 3 demonstrates the enhanced semiphysical device model now able to accurately simulate I-V characteristics at 200°C, while Figure 4 demonstrates the accuracy of the I-V simulation at 25°C. Thus, the semiphysical model, which can be

20 derived at room temperature can be modified with empirical temperature coefficients to incorporate accurate temperature dependence. In step 6, the analytical thermal conduction expression is as set forth in "Precise Technique Finds FET Thermal Resistance" by H. Cooke, "Microwaves and RF". August 1986. Lastly, in step 7, gate length, which is taken to be the length of the heat- generating region in Cooke's expressions, is replaced by a semiphyically modeled 5 XSAT expression provided below.

= Xsθ { Mχs [ 1/(1⁺(Vds Vsatπ)^m)^{(1 m)} - d,m ( _ΛW_βaln)^ { «_Λm[1+(V_Λ /_wtnn^l1ft,,M!H Position of the Boundary between Regions 1 and 2 Xg Iμ^m] ^v_s ^MX_SL ⁺ VgteMxs_K 1

= δ { 1 + [L_g ΔL_s-) -L_g+X_sa*_REF]/(2 _δX)

+ sqrt ( _δ ² + ([L_gerΔL_s-X_s-L_g+X_satREF]/(2 _δX) - 1 f Length of the Saturated Region, Region 2, under the Gate ^SAT ^^m^ ^

Length of the Linear Region, Region 1 L| Iμ l = L_geff- s_Aτ

= δ { 1 + [L_gs-L₁] (2 δX) Total Length of the Saturated Region, Region 2 ₂ E_μm] + sqrt ( §² + ([L_gs-L₁]/(2 _δX) - 1 f }

In Cooke's original derivation, it is assumed that the heat-source within the FET can be approximated by a uniform source for the length of the physical gate length. In 0 reality, a more accurate expression for this heat source would have a length equal to the saturation region's length, or XSAT. Most of the drain voltage, and hence most of the DC power dissipation is dropped across this region, thus making this dimension more suitable to describe the source of heat.

The temperature compensation coefficient is modified to operate between the 5 "channel temperature" rather the "ambient temperature" as generally shown by the equations provided below.

T Tcerrrrp∞siύhj ral>M*£iirdicβrtr&aritσrr T TTOP³ [ M] The distinction between TCF and TCF' is that the TCF is a temperature coefficient determined through complete, uniform heating of the device sample. When "base-plate" heating is used to heat the device sample, it can be assumed that base-plate temperatures are roughly equal to the "chamiel temperature", or rather the temperature of the device is the same as the surrounding environment.

The implementation of Cooke's method coupled with the semi-physical device model results in the equations below:

Channel Temperature T, CH [°C] = Θ Pc_HSAτ W_g/1000 + T_slnk - 273 N_f / { 2π[(N_r1)/ln(M)-(N_r2)/ln(P)] [ K_THW_g/1e7

Thermal Conductivity © [°C/mW] ] }

Power Dissipation over the Saturated Region P CHSAT [mW/mm] * 10^δ

= { 2 sqrt { cosh [π(d_M + X_SAT)/(4H_sub)] cosh [π(d_M - X_SAT)/(4H_sub)] } + 1 } /

{sqrt { cosh [π(d_ffd + X_SAT)/(4H_sub)]

Cooke's "M" parameter M π cosh rπ(d_m - X_SAT)/{4H_sub)] } - 1 }

2 sqrt {[1 + 1/cosh[π(d_ffd + X_SAT)/(4H_sub)]] /

Cooke's "P" parameter P π [1 - 1/cosh d_ffd - X_SAT)/(4H_sub)]] }

Thermal Resistance KTH [W/cm°C]

Drain Current / unit Gate Width ' dsW [A/μm] = 'ds/ W_a

When the device is dissipating a lot of power and thus unable to outflow this heat effectively because of finite thermal conductance, then the device enters a thermal regime known as "self-heating". In self-heating, areas adjacent to the device's heat sources, or that region approximately under the gate, are heated to higher temperatures than the base-plate. As a result, the device becomes hotter than its surrounding environment. In this regime, "channel temperature" must be used to gauge how hot the intrinsic device gets.

As an example of how the formulation accurately models self-heating effects, a large periphery 8-fingered 600μm total gate periphery device cell was tested for DC-IV and S-parameter at room temperature. This particular device layout dissipates too much DC power at high drain voltage or high drain current that could be effectively removed by thermal conduction. As a result, the device suffers from dramatic self-heating. As shown in Fig. 4, the electrothermal model in the semiphysical device model is able to relatively closely simulate the effect of the self-heating channel temperature upon the electrical performance of the device.

SEMI PHYSICAL MODEL Semi-physical device modeling represents both the physical device characteristics and measured characteristics, which can be used to simulate RF performance through physically-based device models. The semi-physical model is an analytical model based upon empirical expressions that model the physics of HEMT operation, hence the terminology "semi-physical". The model incorporates real process parameters, such as gate length recess etch depth, recess undercut dimensions, passivation nitrite thickness, and the like. By using empirical expressions, the semi-physical model is able to maintain relatively good measured to model accuracy while accounting for the effects of process variations on the device performance.

The semi-physical model provides model elements for the standard small signal equivalent circuit model or FET is illustrated in FIG. 5. FIG. 6 is a rough translation of the physical origins for each of the equivalent circuit elements in the small-signal equivalent circuit model illustrated in FIG. 5. FIG. 7 is a cross-sectional drawing of an exemplary HEMT device structure. However, unlike conventional methods, the model elements are derived from small signal excitation analysis of the intrinsic charge and electric fields within the device. As such, the simulated small signal model elements represent a relatively accurate physical equivalent circuit description of a physical FET.

The general methodology for the semi-physical modeling of intrinsic charge, electrical conductance and the electrical field are as set forth below. First, the relationships between the conduction band offsets, electrical permitivities and material composition for the various materials in the epi stack are determined. These relationships can be performed analytically or by fitting simulated data from physical simulators. Subsequently, the basic electron transport characteristics in any of the applicable bulk materials in the epi stack are determined. Once the electron transport characteristics are determined, the undeleted linear channel mobility is determined either through material characterization or physical simulation. Subsequently, the Schottky barrier height value or expressions are determined. Once the Schottky barrier height value is determined, the semi-physical equations are constructed modeling the following characteristics: Fundamental-charge control physics for sheet charge in the active channel as controlled by the gate terminal voltage.

Average centroid position of the sheet charge within the active channel width.

Position of charge partitioning boundaries as a function of gate, drain and source terminal voltages. Bias dependence of linear channel mobility and surface depleted region.

Bias dependence of the velocity saturating electric field in the channel.

Saturated electron velocity.

Electrical conductance within the linear region of the channel under the gate.

Electrical conductance within the source and drain access regions Once the semi-physical equations are determined, the empirical terms of the semi- physical modeling equations are adjusted to fit the model I-V (current-voltage) characteristics against measured values. Subsequently, the empirical terms are interactively readjusted to achieve a simultaneous fit of measured C-V (capacitance- voltage) and I-V characteristics. Lastly, the empirical modeling terms are fixed for future use.

By constructing a comprehensive set of semi-physical equations that cover all of the physical phenomenon as mentioned above, the physical operating mechanisms within a HEMT device can be relatively accurately determined. FIG. 8 illustrates a set of relatively accurate measured-to-modeled I-V characteristics for a HEMT using the semi-physical modeling discussed herein. In particular, FIG. 8 illustrates the drain-to- source current I_ds as a function of the drain-to-source voltage V_ds for various gate biases, for example, from 0.4V to -1.0V. As shown in FIG. 8, solid lines are used to represent the semi-physical model while the Xs are used to represent measured values. As shown in FIG. 8, a close relationship exists between the measured values and the modeled parameters. An example of semi-physical modeling for physical device operation in accordance with the present invention is provided below. The example utilizes an exemplary device as illustrated in FIGS .9 and 10. Table 2 represents exemplary values for the physical cross-section parameters in the model. FIG. 11 relates to a blown up T-gate characteristic which is correlated to the parameters identified in Table 1.

Table 1 Values for the Physical Dimension Parameters Input into Device Cross Section

Layout Parameter Units Value

Gate Length g [μm] 0.1 so

Wing Length Lgw [μm] 0.520

Gate Mushroom Crown Length Lgmcl [μm] 0.200

Total Gate Height Hg [μm] 0.650

Gate Stem Height Hgstem [μm] 0.300

Gate Sag Height Hgsag [μm] 0.100

Gate Cross-Sectional Area GateArea [μm²] 0.187

Max Cross-Sectional Area MaxArea [μm²] 0.364

Total Gate Periph Wg [μm] 200.000

# Fingers N [ ] 4.000

Source-Drain Spacing Dsd [μ ] 1.800

Gate-Source Spacing Dsg [μm] 0.700

Gate-Drain Spacing Dgd [μm] 1.100

Gate-Source Recess RECsg [μm] 0.160

Gate-Drain Recess RECgd [μm] 0.240

Recess Etch Depth Hrec [A] 780.000

SiN Thickness Hsin [A] 750.000

Gatefeed-Mesa Spacing Dgfm [μm] 2.000

Gateend-Mesa Overlap Dgem [μ ] 2.000

Finger-Finger Spacing Thru Drain Dffd [μm] 16.500

Finger-Finger Spacing Thru Source Dffs [μm] 13.500

Source Airbridge Inset? AB? [ ] P

Source Airbridge Inset Dsabin [μm] 28.000

Source Airbridge Height Hsab [μm] 3.500

Source-Gate Airbridge Clearance Hgsab [μm] 1.640

Source Pad Width Ws [μm] 12.000

Drain Pad Width Wd [μ ] 14.000

Substrate Thickness Hsub [μm] 100.000

As mentioned above, the semi-physical modeling of the intrinsic charge and electric field within the HEMT device is initiated by determining the relationships between the conduction band offset, electric permitivities and material composition for the various materials in the epi stack. Material composition related band offset and electric permitivity relationships may be obtained from various references, such as "Physics of Semiconductor Devices," by Michael Shur, Prentice Hall, Englewood Cliffs, New Jersey 1990. The basic electron transport characteristics, for example, for the linear mobility of electron carriers in the bulk GaAs cap layer may be determined to be 1350cm²/Vs, available from "Physics of Semiconductor Devices", supra. The linear mobility of electron carriers in the undeleted channels is assumed to be 5500cm s. This value may be measured by Hall effect samples which have epi stacks grown identically to the stack in the example, except for some differences in the GaAs cap layer. The Schottky barrier height is assumed to be 1.051 volts, which is typical of platinum metal on a AlGaAs material.

The following equations represent the semi-physical analytical expressions to model the charge control and centroid position in the sample.

= N.V

Empirical Charge Control Expression Ns [cm^"2] [1-KN_s N W

Ideal Charge Control with Filling Law N [cm-²] = 2 N₀ ln [1+exp(V (η V_tll))]

Ideal Charge Control No [cm^"2] =ε_l n _th / [2 q (d_l + Ad_l) 10000] =(N_maχo + N_maxLV_ds™^mal<

Maximum Channel Charge N ^■*max [cm-²]

Initial Gate-Channel Voltage ^v M =V_as - Φ„ - ΔE₀ -V_T0-σV_ds

Threshold Voltage τo M = Φ_b - ΛE_{0 -} V_τ

Doping Threshold Voltage = q N,_dθIta dδ 10000 ' ε, : {(Hspace + H_bar + H_(ltop_β + H_cap)-H_re /

Gate-to-Channel Spacing [m] (10¹⁰) note that the ι expression for di can be changed for different epl-stacks

⁼ "chan [ 1 " d|K*"gtaΗ_cha„_REF -

Movement of Sheet Carrier Centroid Δd, [m] d_IL.V_ds/H_{chan EF}]

Empirical Charge Control Shaping Parameter Y [ ]

Semi-Physical Subthreshold Populating Rate η []

Dielectric Permltivity of the Barrier Layer Si [F/m]

The thermal voltage v,_h [V] = ^KB^Tamb 3

Ambient Temperature T ■ amb [ ]

Fixed Emprical Maximum Sheet Charge N

"maxO [cm^"2]

Vds Dependent Emprical Maximum Sheet Charge N_maχL [cm"²]

Vds Dependent Emprical Nmax shaping term ⁿNmax [ ]

Channel Layer Thickness "chan [A]

Reference Channel Layer Thickness ^chanREF [A]

(Channel Thickness for the sample for which the model was first denved)

Schottky Barrier Height ΦB M Conduction Band Offset between Channel and Barrier ΔE_C M

Front Delta Doping S„delta [cm²] note that this expression can be modified for non-delta doped epi-stacks

Gate-to-Front Delta Doping Spacing dδ [m] = {(H_bar + H_fdope + H_cap)-H_rβc} / (10¹⁰)

Barrier Thickness between front doping and channel space [A]

Barrier Layer Thickness before front doping layer ^Hbar [A]

Front Doping layer thickness J fdope [A]

Cap layer thickness H ^■ "cap [A]

Empirical Drain-Induced Barrier-Lowering Term σ [ ]

Sheet Charge Position Gate Bias Factor d [AW]

Sheet Charge Position Drain Bias Factor _iL [AW]

= V_th [1+V_ot/2V_th +

Effective Gate Voltage "gte M sqrt(δ² + (V_gt 2V_{tn -} 1)²] Empirical Transition Width Parameter δ []

As used herein, Ns represents the model sheet carrier concentration within the active channel. Ns' represents the ideal charge control law and is modeled as a semi- physical representative of the actual density of state filling rate for energy states within the channel v. gate voltage. The gate-to-channel voltage used for the charge control, Vgt, is a function of the Schottky barrier height, conduction band offsets and doping in the epi stack as is known in the art.

The following equations represent the semi-physical expression used to model the position of regional charge boundaries within the HEMT device. These expressions govern how to partition the model charge between the influence of different terminals.

Effective Gate Length [μm] = L_α+_ΔL, + _ΔL_d

Gate-Source Control Region Lgs [_μm] =

Source-Side Effective Gate Length Extension ΔL_S [μm] = ΔL,o⁺ΔL_κ*V₀₁₀

Drain-Side Effective Gate Length Extension ΔL_d [μm] = ΔL_do + ΔL_K' ^ + ΛL_L'V^

Gate-Drain Control Region «d [μm] = (L_g2 + _ΔL_d)*{taπh[10(L₀/2-X_D,)]+1}/2

= Xo_{L d},M_ML/

{MχdκV₀,„*(Hr ,Λ,M_ML/

Bias Dependent Extension of the Saturated Transport Region XDI [μm] (Mχ_d«V( ₀/2+REC_I,,,))r}^,Λ" Empiπcal Drain-Saturated Transport Boundary Factor XDL [_μm] = L_gV_d,/{2[1₊(V_d,/V„,™rr"^l>

= X.„{Wl_x.[1/(1+(V_d.V,„_l„n""»'- Emplncal Effective Gate Length Extension Gate Bias Factor tμ 'V] Empiπcal Effective Gate Length Extension Dram Bias Factor Δ [μ<ϊl/V] Effective Drain-Source Voltage Control-2 v_dse- [V] = V_d!/[1+(V_dϊ/V„,„π"^m Rough, Intrinsic Saturation Voltage Vsatn m

= S_cw ₀,„/

Rough, Intrinsic Saturation Current Level 'sat [A] [1 + g_Λ,R, + sqrt(H-2g_cWR,₊(V₀,.V_L)²)]

Intπnsic Conductance of the Linear Region, Under the gate 9chl [S] =( N.μ,„Wg)/Lg

Rough Intrinsic Saturation Voltage Level v_L m = F.*L_g

Emplncal Knee Shaping Parameter m []

Emplncal Region 2 extension Drain Bias Factor MxdL []

Empiπcal Region 2 extension Gate Bias Factor MxdK []

Fine Intπnsic Saturation Voltage V_saten ro

= Brt|V„.V_L*[-V_L(A+g_d,,R,) + sqrt(V_L ²(A+g_cωR, + V feiΛV..)²)]

Fine Inlnnsic Saturation Current Level 1

' I,satcom [A] r ₀,_o ²(i-g_h,R,(v_uv_g„)²)]

Saturation Region Length Ratio A [] = Xa L,,,

Initial Starting position for Regionl & 2 Boundary X_so [_μm] = Lg/2

Reglonl & 2 Boundary Bias Factor Mxs []

Regionl & 2 Boundary Dram Bias Factor Mxs []

Regionl & 2 Boundary Dram Bias Factor []

The following equations represent is the semi-physical expression used to model the bias dependence of linear channel mobility in depleted regions. Depleted Channel Mobility μ_avβ IcrrftV's] = μ_dc|)an + μ_dκ.V_9te

Fixed Depleted Channel Mobility _μdchan [cm² V*s] Depleted Channel Mobility Gate Bias Factor μ_dκ [cm²Λ ²*s]

The following equations are the semi-physical expressions used to model the bias dependence of the saturating electric field and saturation velocity.

Saturating Electric Field Fs [V_/μm] [(μ_Sat ⁺ ^_atκV_gtβ) 10000]

Fixed Saturating Channel Mobility μsat [cnv7v*s]

Saturating Channel Mobility Gate Bias Factor μsatK [cm²/V²*s]

Saturation Velocity _s [cm/s]

FIG. 12 is a schematically illustrates how electrical conductance in the source and drain access regions are modeled in the example.

The following equations describe the semi-physical model for the source access region conductance:

Source Access Resistance Rs M = ( Rs. ,)/W„

Source Access Resistance Channel and Cap

Source Access Resistance Recess and Undepleted Cap

Source Access Resistance Crowding resistance due to conductance mismatch [Ω»μ"l]

Resistance of the Source Recess Access region at high on-state bias (V_on)

Resistance of the Undepleted Source Recess Access region [Ω*μm]

Uncapped, Fully Depleted Sheet Resistance [Ω/sq]

Capped, Undepleted Sheet Resistance [Ω/sq]

Uncapped, Undepleted Sheet Resistance [Ω/sq]

Cap Sheet Resistance

Surface Depletion Factor

High On-state bias Diode Turn-on voltage = Φ_b - ΔE, - ΔE,

Ohmic Contact Resistance [Ω*μm]

RF Ohmlc Contact Resistance Reduction Factor

Source Access Resistance Bias Modification Factor MR_S

Cf-Vds Bias Modification Factor MCn.

Rs-Vds Bias Modification Factor MR,,

Rs-Vgs Bias Modification Factor

Cf-Vgs Swith point to On-state

Cf-Vgs Bias Expansion Factor

Rs-Vgs Swith point to On-state

Rs-Vgs Swith point to Off-state VR-

Rs-Vds Swith point from Off-On transition

Rs-Vds Bias Expansion Factor

Rs-Vgs Bias Expansion Factor

Rs-Vds Bias Expansion Factor @ Rs Saturation KR„

Rs Bias Shaping Factor

The following equations describe the drain access.

^: ( ⁺ )

= ( R, , + Rn,

Drain Access Resistance, except for recess access fo]

= R_Dd„p_R. ™( N"VV_g, + 1) [ 1 -

Drain Access Resistance: Recess and Undepleted Cap RoAccess [Ω*μ^ml tanh{ KR_d„_dK * [ V„, - VR_d0n + V_d,* R_d„„_L ]} ] / 2

⁼ Rc nl/RFrconF ⁺ Dgd

Drain Access Resistance: Channel and Cap R _{D un}depCap -Ω*μ^m] - (REC_gd+L_g/2)] Resistance of the Undepleted Drain Recess Access region Roun β Rec [ *μ^m) ⁼ RsHundap ( REC_gd )

= MR_dSal*V_d, exp { -[ V_g,+V_d,'MR_dL+VR_dSaraff]²/ ( 2

Resistance of the Saturated Drain Recess Access region Rosatunite_d [Ω*μ ] VR_dSatα) } / { VR_ds._l[1+(V_d. VR_dSal)»^F"¹ "*^ } Resistance of the Drain Recess Access region at high on-state bias (V_on) R _{D dβp}Rec°^N tΩ*μ l ⁼ RsHdβp ( REG_gd )

= δVL ( 1 ⁺ ( " Rounder, V( ^_VL) + Sqit[ δ

R_DRec [Ω*μm]

Drain Access Resistance Bias Modification Factor MR_d []

Rd-Vds Access Bias Modification Factor "daccL I 1

Rd-Vgs Swith point to On-state VRdOn t '

Rd-Vgs Swith point at saturation VR_dSat [ 1

Rdaccess-Vgs Bias Expansion Factor ^KRdaccK I )

Rd-Vds Saturation Bias Modification Factor MR_dSat []

Rd-Vds Access Resistance Bias Modification Factor MR_dL []

Rd-Vgs Saturation Swith point to Off-state VRdSatOff t ]

Rd-Vgs Saturation Swith point VRdSat M

Rd-Vgs Saturation Swith point transition width VR_dSa._σ ti

Rd Bias Shaping Factor γ U

SEMI-PHYSICAL DETERMINATION OF SMALL-SIGNAL EQUIVALENT

CIRCUITS

To derive values for the familiar small signal equivalent circuit as shown in FIG. 5, a small signal excitation analysis must be applied to the semi-physically modeled physical expressions. The method of applying such an analysis is as follows:

1) Gate Terminal Voltage Excitation a) Apply a small-t-/- voltage delta around the desired bias condition, across the gate-source terminals. b) Equivalent circuit element Gm = delta(Ids)/delta (Vgs') where delta (Vgs') is mostly the applied voltage deltas, but also subtracting out that voltage which is dropped across the gate source access region, shown as RsCont, RsundepCap, RsundepRec, ResdepRec, and RsBoundary in FIG. 12, above. c) Equivalent circuit element Cgs and Cgd takes the form of delta(Nsn)/delta(Vgs)*Lgn, where delta (Nsn) is the appropriate charge control expression, and Lgn is the gate source or gate drain charge partitioning boundary length. d) Equivalent circuit element Ri=Lgs/(Cgschannel * vs) where Cgs channel is the portion of gate source capacitance attributed to the channel only, and vs is the saturated electron velocity.

2) Drain Terminal Voltage Excitation a) Apply a small +/- voltage delta around te same bias condition as in 1, but the delta is applied across drain source terminals. b) Equivalent circuit element Rds = l/{delta(Ids)/delta(Vds')} where Vds' is mostly the applied voltage deltas, but also subtracting out voltage which is dropped over both the gate source and gate drain access regions. c) Equivalent circuit element Cds is taken to be the sum of the appropriate fringing capacitance Semi-Physical models, or can take the form of delta(Nsd)/delta(Vds')*Xsat, were Nsd is the charge control expression for charge accumulation between the appropriate source and drain charge boundaries, and Xsat is the length of the saturated region, if in saturation.

3) On-mesa Parasitic Elements: The equivalent circuit elements, Rs and Rd are expressed by the appropriate electrical conduction models of the source and drain access regions. The RF performance can be predicted at an arbitrary bias point.

Table 3 represents a comparison of the values for a high frequency equivalent circuit model derived from equivalent circuit model extraction from and semi-physical modeling for the sample illustrated in Table 2.

Table 2

Comparison of Modeled Equivalent Circuit Results for Semi-physical

Modeling Method, and Equivalent Circuit Model Extraction

The results of the semi-physical modeling method produce a small-signal equivalent circuit values which are relatively more accurate than the physical device simulator in this case. Furthermore, given the differences in the parasitic embedding, treatment of the two approaches, the results given in Table 2 yield much closer results than a comparison of equivalent circuit values.

Table 3 lists the values of parasitic elements used in the model derivations. An important difference between the extracted equivalent circuit model and the semi- physically derived one is the use of Cpg and Cpd to model the effect of launch capacitance for the tested structure. This difference leads to the results of the extracted model results being slightly off from the optimum physically significant solution.

Table 3 Comparison of Modeled "Parasitic" Equivalent Circuit Results for Semi- physical Modeling Method, and Equivalent Circuit Model Extraction

As shown in FIGS. 13, 14 and 15, the modeled results that are simulated using the semi-physically derived equivalent circuit model very accurately replicate the measured high frequency, S-parameter data.

The following equations represent the small-signal excitation derivation of small- signal equivalent circuit modeled Gm. Figure 56 illustrates the semi-physically simulated bias equations of the small signal Gm compared to measured date.

=gct, V_ds (1+λV_ds) /

Semi-Physically Modeled Drain-Source Current Control I_rj_s [A] [1⁺(V_ds/Vsa.β)^m]^1/m

Small-Signal Deterimination of equiv. Circuit Gm value 9_mRF -S] = d"ds / rf( V_gs - V_sAcc )

⁼ 'dsW* ( "sUndβpCap ⁺ "sAccess ⁺ "i

Source-Access voltage drop V_SAcc [V] RR_np_mro_hb__βss//W„_g ) )

Fine Extrinsic Saturation Voltage V_s-te [V] 'satconv 9ch

9ch|/

Extrinsic Conductance of the Linear Region, Under the gate g_cn [S] [1+gchl (Rs+Rd)]

Intrinsic Conductance of the Linear Region, Under the gate S_cni JS] =(q N. μ„ _βW₃) / L

The following equations represent the small-signal excitation derivation of Rds. Figure 57 illustrates the semi-physically simulated bias-dependence of the small- signal Rds.

Small-Signal Deterimination of equiv. Circuit Rds value R_ds fr-1 = 1 / 9d_SRF

= { dl_ds / d ( V_ds - R_probeD . I_ds - V_sAcc-V_dAcc-V_dSat )

SdsRF [S] } "

Drain-Access voltage drop *DAcc [V] . ) Drain-Saturated Region voltage drop ^DSAT m

Q External Test probe or lead resistance R "^_pp_rr₀o_bbee_DD [Ω3

= (RFrdsF + D *

High Frequency conductance dispersion factor ^rdsF [] tanh( 10 * | V_ds - V_th | ) + 1 High Frequency conductance dispersion ^RFrdsF [1 The following equations may be used for illustrating small-signal excitation derivation of Cgs and Cgd. Figure 58 illustrates the Semi-Physically simulated bias-dependence of the small-signal Cgs and Cgd.

^_ _gsf* β C_gu_T,,_! L_gS.

Small-Signal Deterimination of equiv. Circuit Cgs value °_Bs [fF/μlϊl] {1-[(V₅„._n-V_d5a)/(₂*V_SI,_tβn-V_ds!,) } = C_g((f + β C_gcTo| L_gd *

^Cgd [fF/μm] {1-[V_sat0„/(2*V_M,_o„-V_d„)]²}

Parasitic Gate-Source Fringing Capacitance ^Cgsf [fF/μm] = Cg_sϋrf C_f._fotra1SiNF + Cgsf_Source + Cgsf_Pad

Parasitic Gate-Source Fringing Capacitance ^Cgrff [fF/μm] = Cff _surf C_t._fomι1SiNF + Cgdf_Cap + Cgdf_Pad

Total Specific Gate-Channel Capacitance — p +

C gcTot [fF/μm²]

= c_gc Msh_Kchan /

Specific Gate-Channel Capacitance ^Cgc [fF/μm²] {_[I N_sVf_No + _}

Effective Drain-Source Voltage Control v_dse m = V_d5/t1+(V_d5/V_salenn¹""

Specific Gate-Donor Layer Accumulation Capacitance c ** gcdonor [fF/μm²] = qdN_sDor,_ljr/dV_gs

Ideal Specific Gate-Channel Capacitance [fF/μm²] = qdN₅7 V_gs =(N_s ¹ ₊ N Δd_l)Msh_Kpar*V_gte/

Empirical Parasitic Donor Charge Control Expression N "sDonor [cm^"2] (d_{l +} Δd,) Fringing capacitance to surface of source-access region Cgsυrf [fF/μm]

Empirical Fringing capacitance-bias shaping expression '-'f-forml [] = { 1 - tanh[ KC_(K( V_gs - VC_(0n + V_dsMC_tL )] } /

Fringing capacitance to source-access region ^ gsfSource [fF/μm]

Fringing capacitance to source metal pads GgsfPad [fF/μm]

Fringing capacitance to drain-access Capped Region GgdfCap [fF/μm]

Fringing capacitance to drain metal pads CgdfPad [fF/μm]

Dielectric Coating Thickness Factor SiNF []

Specific Gate-Channel Capacitance Bias ModificationFactor ^Msh_Kcahn []

Donor Charge Bias ModificationFactor Msh_Kp-r []

Empirical Specific Charge Control Shaping Parameter []

The following equations are involved in the small-signal excitation derivation of Ri. Figure 59 which follows shows the Semi-Physically simulated bias- dependence of the small-signal Ri.

Gate-Source Non-quasistatic charging resistance = L_gs₂W_g/[C_BsChanW₀V_s]

"lCharge [Ω*μ^m] = ^Cgsf ⁺ β ^Ggc L_gs * Gate-Channel Source Capacitance ^v gsChαn [fF/μm] {1 -[(Vsa,an-V_ds,)/(2 _aten-V_dse)]²} EXAMPLE OF SEMI-PHYSICAL MODEL AND BIAS DEPENDENCE SMALL SIGNAL SOURCE AND DRAIN RESISTANCE. RS AND RD

FIG. 60 shows the semi-physically simulated bias dependence of the on-mesa parasitic access resistances Rs and Rd.

The following example verifies how the semi-physical small-signal device model is able to provide accurate projections for bias-dependent small-signal performance. In this example, the same semi-physical device model as used in the previous examples was used because the example MMIC circuit was fabricated utilizing the same HEMT device technology.

In this example, the bias-dependence small-signal gain and noise performance of a two-stage balanced K-band MMIC LNA amplifier is replicated through microwave circuit simulation using small signal and noise equivalent circuits that were generated by the semi-physical model. The results of the measured and modeled results are shown below in Table 4. As seen from these results, the Semi-Physical device model was able to accurately simulate the measured bias-dependent performance, even though the bias variation was quite wide.

Table 4 Measured vs Modeled NF and Gain @ 23.5 GHz for a K-band MMIC LNA at different bias conditions.

A plot of measured vs modeled gain for the values listed in Table 3 above is shown in Figure 61.

The following example verifies how the Semi-Physical small-signal device model is able to provide accurate projections for physically dependent small-signal performance, hi this example, the same Semi-Physical device model as used in the previous examples was used. hi this example, physical process variation was input into the Semi-Physical device model in terms of statistical variation about known averages, cross-correlation, and standard deviations. The goal of this exercise was to replicate the measured DC and small-signal device variation. The degree of accurate replication indicates the degree to which the Semi-Physical model is physically accurate.

Table 5 below lists the simulated, and known process variation that was used: TABLE S Statistical process variation model

Parameter Nominal Standard Dev.

Gate Length 0.15 um 0.01 urn

Gate-Source Recess 0.16 um 0.015 urn

Gate-Drain Recess 0.24 um 0.020 um

Etch Depth 780 A 25 A

Pass. Nitride Thickness 750 A 25 A

Gate-Source Spacing 0.7 um 0.1 um

Source-Drain Spacing 1.8 um 0.15 um

In the course of microelectronic component production, sample devices are tested in process in order to gain statistical process control monitor (PCM) data. Figure 18 shows schematically the kind of data that is extracted and recorded from measured device I-V's during PCM testing.

Since the Semi-Physical device model is able to simulate I-V's, it was able to simulate to variation of I-V's due to physical process variation. These I-V's were analyzed in the same fashion to extract the same parameters that are recorded for PCM testing. Figures 63, 64 AND 65 shows how accurately the simulated results match with measured process variation. Figure 63 shows how the Semi-Physically simulated Vgpk and Gmpk match with actual production measurements. Figure 64 shows how simulated Idpk and Gmpk match, also. Finally, Figure 65 shows how simulated Imax and Vpo also match very well. Small-signal S-parameter measurements are also taken in process for process control monitoring. These measurements are used to extract simple equivalent circuit models that fit the measured S-parameters. Since the Semi-Physical device model is able to simulate these equivalent circuit models, it was able to simulate the variation of model parameters due to physical process variation. Figures 66 and 67 show how accurately the simulated results match with measured/extracted process variation for the small-signal model parameters. Figure 66 shows how the Semi-Physically simulated Rds and Gm match very well with actual extracted model process variation.

More direct and convincing evidence supporting the accurate, physical nature of the Semi-Physical model can be shown be comparing the dependence of simulated and measured performance to real physical variable. As shown in Figure 68, the Semi-

Physical model is able to very accurately reproduce the dependence of Imax upon gate length. In addition, the Semi-Physical model is also able to replicate physical dependence for high-frequency small-signal equivalent circuits. This is shown in Figure 69, which shows that it is able to reproduce the dependence of Rds with Recess undercut width.

S-PARAMETER MICROSCOPY

The S-parameter (SPM) method utilizes bias dependent S-parameter measurements as a form of microscopy to provide qualitative analysis of the internal charge and electrical field structure of the semiconductor device heretofore unknown.

Pseudo images are gathered in the form of S-parameter measurements extracted as small signal models to form charge control maps. Although finite element device simulations have heretofore been used to calculate the internal charge/electric field of semiconductor devices, such methods are known to be relatively inaccurate. The S- parameter microscopy provides a relatively accurate method for determining the internal charge and electric field within a semiconductor device. With accurate modeling of the internal charge and electric field, all of the external electrical characteristics of semiconductor devices can be relatively accurately modeled including its high frequency performance. Thus, the system is suitable for making device technology models that enabled high frequency MMIC yield analysis forecasting and design for manufacturing analysis.

S-parameter microscopy is similar to other microscopy techniques in that SPM utilizes measurements of energy reflected to and from a sample to derive information. More particularly, SPM is based on transmitted and reflective microwave and millimeter wave electromagnetic power or S-parameters. As such, S-parameter microscopy is analogous to the combined operation of scanning and transmission electron microscopes (SEM and TEM). Scattered RF energy is analogous to the reflection and transmission of the electron beams in the SEM and TEMs. However, instead of using electron detectors as in the SEM and TEMs, reflectometers in a network analyzer are used in S-parameter microscopy to measure a signal. S- parameter microscopy is similar to other microscopy techniques in that both utilize; measurement of scattering phenomenon as data; include mechanisms to focus measurements for better resolution; and include mechanisms to contrast portions of the measurement to discriminate detail as shown in Table 6 below:

Table 6

RESULT: Detailed "images" of device's internal charge and electric field structure.

Images as discussed herein, in connection with S-parameter microscopy do not relate to real images, but are used provide insight and qualitative detail regarding the internal operation of a device. More specifically, S-parameter microscopy does not provide visual images as in the case of traditional forms of microscopy. Rather, S- parameter microscopy images are more like maps which are computed and based on a non-intuitive set of measurements.

FIG. 16 illustrates a conceptual representation of an S-parameter microscope, generally identified with the reference numeral 20. The S-parameter microscope 20 is analogous to a microscope which combines the principles of SEM and TEM. Whereas SEM measures reflections and TEM measures transmissions, the 2-port S- parameter microscope 20 measures both reflective and transmitted power. As a result, data derived from the 2-port S-parameter microscope contains information about the intrinsic and extrinsic charge structure of a device. More particularly, as in known in the art, SEM provides relatively detailed images of the surface of a sample through reflected electrons while TEM provides images of the internal structure through transmitted electrons. The reflective signals are used to form the external details of a sample while transmitted electrons provide information about the interior structure of a device. In accordance with an important aspect of the invention, S-parameter microscopy utilizes a process of measuring reflective and transmitted signals to provide similar "images" of the charge structure of a semiconductor device. As used herein the internal and external electrical structure of a semiconductor device are commonly referred to as intrinsic device region 22 and extrinsic parasitic access region 24 as shown in FIG. 17. Also contributing to the external electrical structure of the device are parasitic components associated with the electrodes and interconnects which are not shown. These are the so-called device "layout parasitics".

Referring to FIG. 16, the ports 26 and 28 are emulated by S-parameter measurements. The S-parameter measurements for a specific semiconductor device, generally identified with the reference number 30, are processed to provide charge control maps, shown within the circle 32, analogous to images in other microscopy techniques. These charge control maps 32, as will be discussed in more detail below, are expressed in the form of equivalent circuit models. As shown in FIG. 18, linear circuit elements are used in the models to represent the magnitude and state of charge/electric fields inside the semiconductor device 30 or its so-called internal electrical structure. The position of the circuit elements within the model topology is roughly approximate the physical location within the device structure, hence the charge control map represents a diagram of the device's internal electrical structure.

The interpretation of the exact location of measured charge/electric fields within the semiconductor device is known to be ambiguous since an equivalent circuit model, for example, as illustrated in FIG. 19 with discrete linear elements, is used to represent the distributed structure of the charge/electric fields in the actual device. Although there is no exact method for distinguishing the physical boundaries between measured quantities, bias dependence is used to clarify how the S-parameters should be discriminated, separated and contrasted. In particular, changing bias conditions is known to change the magnitude and shift boundaries between the charge and electric fields within the device. The changes are normally predictable and qualitatively well known in most technologies. As such, the charge control maps can readily be used as maps illustrating the characterization of physical changes in magnitude, location and separation of electric charge and electric fields.

Analogous to other forms of microscopy, the S-parameter microscope 20 in accordance with the present invention also emulates a lens, identified with the reference numeral 40 (FIG. 16). The lens 40 is simulated by a method for the extraction of a unique equivalent circuit model that also accurately simulates the measured S-parameter. More particularly, parameter extraction methods for equivalent circuit models that simulate S-parameters are relatively well known. However, when the only goal is accurately fitting measuring S-parameters, an infinite number of solutions exist for possible equivalent circuit parameter values. Thus, in accordance with an important aspect of the present invention, only a single unique solution is extracted which accurately describes the physical charge control map of the device. This method for unique extraction of equivalent circuit model parameters acts as a lens for focus the charge control map solution. As discussed and illustrated herein, the lens 40 is subsequently simulated by a filter that is based on an apparent layout parasitic embedding model. As discussed below, the layout parasitic embedding model consists of linear elements which simulate the effect of the device's electrodes and interconnects upon its external electrical characteristics. A Pi FET embedding model 42, is described below. This model effectively acts as a filter to remove the electrical structure of the extrinsic parasitic access contribution to the preliminary charge control map solution. The resultant, filtered charge control map solution represents a clearer "image", which shows only the electrical structure of the intrinsic device. This enhanced imaging is needed in order to achieve as accurate a view of the internal electric charge/field as possible. Unlike conventional extraction techniques as illustrated in FIG.21 , which can only extract equivalent non-unique circuit models and not the unique charge control map, the S-parameter microscope 20 in accordance with the present invention is able to relatively accurately model the internal electric charge/field structure within a semiconductor device.

An exemplary application of the S-parameter microscope is illustrated in detail below. In this example, an exemplary GaAs HEMT device with four gate fingers and 200μm total gate periphery formed in a Pi-FET layout as generally illustrated in FIG. 22 and identified with the reference numeral 43 is used. The GaAs HEMT 43 is adapted to be embedded in a 100-μm pitch coplanar test structure to facilitate on wafer S-parameter measurement.

Initially, as illustrated in FIGS. 23 and 24, the I-V characteristics for the device are measured. In particular, the drain source current Ids is plotted as a function of drain-to-source voltage Vds at various gate voltages Vgs as shown in FIG. 23. and FIG.24 illustrates the drain-to-source current Ids as a function of gate voltage Vgs and transconductance Gm (i.e. the derivative of Ids with respect to Vgs) at different drain voltages Vds. These I-V characteristics are typical of HEMT devices and most semiconductor devices, which are one type of three-terminal semiconductor device technology.

Table 7 shows the bias conditions in which S-parameters were measured. The S- parameters were measured from 0.05 to 40 GHz at each bias condition. F I G . 2 5 illustrates a Smith chart illustrating the measured S-parameters SI 1, S 12 and S22 for frequencies from 0.05 to 40.0 GHz. FIG. 26 is a graphical illustration of magnitude as a function of angles for the measured S-parameter S21 for frequencies from 40.05 to 40.0 GHz.

TABLE T Measured S-parameter Bias Conditions

Biases Vds = Vds = Vds = Vds = Vds = Vds =

Vgs | ov 0.5 V 1.0 V 2.0 V 4.0 V 5.0 V

-1.6 V | Yes Yes Yes Yes Yes Yes

-1.4 V | Yes Yes Yes Yes Yes Yes

-1.2 V | Yes Yes Yes Yes Yes Yes

Using the small signal model illustrated in FIG. 19, the extracted small signal equivalent circuit values are obtained as illustrated in Table 8 for each S-parameter at each bias condition, using the extraction method discussed below.

Table 8

Bias-dependent Small-signal Equivalent Circuit Models

Vd Vg Rg+Ri Rs Rd Lg Ls Ld Cgs Cdg Cds Gm Rds Ta Rgs Rgd

[V] [W] [W] [W] [nH] [nH] [nH] [pF] [PF] [pF] [mS [W] [pS [W] [W]

0 -2 4.32849 0.5125 4.2 0.0197 0 00001 0.0265 0.0415 0 0415 0 0432 0 1000000 0 904000000 90400000

0 -1.6 4.11231 0.52 4 0.028 0 0 0245 0.045 0.045 0.045 0 1000000 0 87000 87000

0 -1.4 3.01231 0.55 3.5389 0.0275 0.00001 0.0234 0.0501 0.0501 0.046 0 1000000 0 70000 70000

0 -1.2 3.97956 0.5857 3.9231 0.0274 0 00001 0 0245 0.0549 0 0549 0 0467 0 3532 954 0 59895 6 5989

0 -1 3 S7822 0 58 3 7 0 0263 0 00123 0 0253 0 0632 0 0632 0 047 0 200 0 60000 60000

0 -0.8 3.39996 0.58 3.6713 0.0262 0.00347 0.0259 0.0800 0.0800 0.0488 0 51.8679 0 60000 60000

0 -0.6 3.33401 0.5857 3.5031 0.0276 0 00353 0 0239 0.0923 0.0923 0 1597 0 7.84388 0 970000000 97000000

0 -0.4 3.31632 1.7677 3.3 0.0232 0 00356 0 0338 0.1002 0.1002 0 1805 0 6.65812 0 65565 93 65565.93

0 -0.2 3.09963 1.7677 3.3 0.0242 0 00347 0 0344 0.1044 0.1044 04210 0 4.75859 0 58682 78 58682.78

0 0 3.16448 1.4142 3.5 0.0156 0 00334 0 0314 0.1076 0.1076 0.4583 0 3.49009 0 55000 55000

0 0 2 2.45244 1 2803 3 3080 0.0266 0 00384 0.0281 0.1100 0.1100 1 6745 0 1.40002 0 16926 72 16926 72

0 0.6 2.48828 1.4142 2.6195 0.0266 0.00352 0.0284 0.1247 0.1247 2.0290 0 1.25101 0 3811.933 3811 933n 0 0.755 4.31968 1.5 2.3 0.0188 0.00320 0.0308 0.1417 0.1417 2 0 2.94325 0 478.3791 478.3791

¹ 0.5 -1.6 4.80961 0.5 ~ ~Tf,0337 ~~^~0Λ ^"~ 0.¥169 0,0472 . ϋ. m ~^~δofi@z~ ,22^{"^} 1.02E+08 0.1 ~ 0Q403 ^{~~ "~} 8.10E+0

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The values in Table 8 represent solutions that are close to the charge control map and represent physically significant solutions of the FET's electrical structure. However, the values represented in Table 8 contain the influence of external layout parasitics which are subtracted using a model for the embedding parasitics to obtain the most accurate charge control mapping to the intrinsic device characteristic. In particular, an embedding model is applied filter the extracted equivalent circuit model values and obtain values more representative of the intrinsic device. In particular, in the exemplary embodiment, a PiFET embedding parasitic model is used to subtract capacitive contributions due to interelectrode and off-mesa layout parasitic influences. This filter essentially subtracts known quantities formed from the parameters Cgs, Cgd and Cds depending on the device layout involved. In this example, embedding of the inductive parameters is not necessary because these quantities are extrinsic and do not contribute to the charge control map of the intrinsic device.

As discussed above, the lens with filter are used to generate unique charge control maps. In particular, FIGS.27-30 illustrate the bias dependent charge control maps for the parameters RS, RD, RI, CGS and CGD as a function of bias. More particularly, FIG. 27 illustrates a charge control map of the charge and electric field distribution in the on-mesa source access region illustrated by the source resistance R_s as a function of bias. FIG. 28 illustrates a charge control map of the charge and electric field distribution in the on-mesa drain access region illustrated by the drain resistance R_d as a function of bias. FIG. 29 illustrates a charge control map for a non-quasistatic majority carrier transport illustrated by the intrinsic device charging resistance R_; as a function of gate bias for different drain bias points. FIG. 30 illustrates a charge control map for gate modulated charge and distribution under the gate shown with the gate capacitance CGS and CGD as a function of bias. FILTER

As mentioned above, the S-parameter microscope 20 may utilize a filter to provide a clearer charge control map for modeling the internal electric charge/field of a semiconductor device. Although the filter is illustrated in connection with the PiFET with multiple gate fingers, as illustrated in FIGS. 31 and 32, the principles of the invention are applicable to other semiconductor devices.

As illustrated in FIG. 31, PiFETs are devices in which the gate fingers and the edge of the active region resemble the greek letter π, as illustrated. Such PiFET layouts facilitate construction of multi fingered large periphery device cells, for example, as illustrated in FIG 32. In accordance with an important aspect of the invention, the multi-finger semiconductor device is modeled as a combination of single finger device cells. Each single finger device cell is represented by a hierarchy of four models, which, in turn, are assembled together using models for interconnects to represent an arbitrary multifingered device cell, illustrated in Fig.33. The four models are as follows: off mesa or boundary parasitic model; interelectrode parasitic model; on-mesa parasitic model and intrinsic model.

The off-mesa parasitic model is illustrated in FIG. 34. This model represents the parasitics that exist outside the active FET region for each gate finger. In this model, the fringing capacitance of each gate finger off the active device region as well as the off-mesa gate finger resistance is modeled.

The interelectrode parasitic model and corresponding equivalent circuit are illustrated in FIGS. 35-37. This model represents parasitics between the metal electrodes along each gate finger. The following fringing capacitance parasitics are modeled for the gate-to-source air bridge; drain-to-source air bridge; gate-to-source ohmic; gate-to-drain ohmic and source-to-drain ohmic as generally illustrated in FIG.

36.

The on-mesa parasitic model and corresponding equivalent circuit are illustrated inFIGS.38 and39. This model represents that parasitics around the active FET region along each gate finger including various capacitance fringing parasitics and resistive parasitics. In particular, the gate-to-source side recess; gate-drain-side recess; gate- source access charge/doped cap; and gate-drain access charge/doped cap capacitance fringing parasitics are modeled. In addition, the gate metallization and ohmic contact resistive parasitics are modeled.

The intrinsic model and corresponding equivalent circuit are illustrated in FIGS. 40 and 41. The intrinsic model represents the physics that predominately determine the FET performance. In particular, the DC and current voltage response can be determined by physics based analytical equations for magnitude and location of intrinsic charge which are generally know in the art, for example, as disclosed in 'TSTonlinear Charge Control in AlGaAs/GaAs Modulation-Doped FETs", by Hughes, et al, IEEE Trans. Electron Devices. Vol. ED-34, No. 8, August 1987. The small signal model performance is modeled by taking a derivative of the appropriate charge or current control equations to derive various terms such as RI, RJ, RDS, RGS, RGD, GM, TAU, CGS, CDS and CGD. Such control equations are generally known in the art and disclosed in detail in the Hughes, et al. reference mentioned above, hereby incorporated by reference. The noise performance may be modeled by current or voltage perturbation analysis "Noise Characteristics of Gallium Arsenide Filed-Effect Transistors" by H. Statz, et al. IEEE-Trans. Electronic Devices, vol. ED-21, No. 9, September 1974 and "Gate Noise in Field Effect Transistors at moderately High Frequencies" by A. Van Der Ziel, Pro. IEEE, vol 51 , March 1963 "Gate Noise in Field Effect Transistors at Moderately High Frequencies", by H. Statz, IEEE Trans. Electron

Devices, vol. ED-21, No. 9, September 1974. "Noise Characteristics of Gallium Arsenoϊe Field Effect Transistors", by Statz et al, IEEE Trans. Electron Devices, vol. ED-21, No. 9, September 1974.

An example of a parasitic model for use with the S-parameter microscopy discussed above is illustrated in FIGS. 42-49. Although a specific embodiment of a semiconductor device is illustrated and described, the principles of the present invention are applicable to various semiconductors devices. Referring to FIG. 42A, a Pi-FET is illustrated. As shown, the PiFET has four gate fingers. The four fingered Pi-FET is modeled in FIG.42B . In particular, FIG 42B illustrates an equivalent circuit model for Pi-FET illustrated in FIG. 42A as implemented by a known CAD program, for example, LIBRA 6.1 as manufactured by Agilent Technologies. As shown, the equivalent circuit models does not illustrate all of the equivalent circuit elements or network connections involved with implementing the parasitic embedding models, but rather demonstrates a finished product. The actual technical information regarding the construction of the network and its equivalent circuit elements are normally provided in schematic view. An important aspect of parasitic modeling relates to modeling of multi-gate fingered devices as single gate finger devices. As used herein, a single unit device cell refers to a device associated with a single gate finger. For example, a four fingered Pi-FET as illustrated in FIG. 42A is modeled as four unit device cells.

Initially, the four finger Pi-FET illustrated in FIG. 42A, is modeled as a single finger unit device cell 100 with an intrinsic model 102, as shown in FIGS. 43 and 44. In particular, the Pi-FET intrinsic FET model 104 is substituted for the block 102 defining a first level of embedding. As shown in FIG.44, the parameter values for the Pi-FET intrinsic model are added together with the parameter values for the single fingered unit device cell intrinsic model. The intrinsic device model 104 may be developed by S-parameter microscopy as discussed above. Next, as illustrated in FIG. 45, the interconnect layout parasitic elements are added to the equivalent model by simply adding the model terms to the value of the appropriate circuit element to form a single unit device cell defining a second level of embedding. Once the single unit device cell is formulated, this device is used to construct models for multi-fingered devices. In this case, a Pi-FET with four gate fingers is modeled as four single finger device unit cells as shown in FIG. 46. Subsequently, the off-mesa layout parasitic elements are connected to the multi-fingered layout, defining a third level of embedding as illustrated in FIG. 47. These off-mesa layout parasitic elements, generally identified with the reference numerals 108 and 110, are implemented as new circuit elements connected at key outer nodes of the equivalent circuit structure. Subsequently, a fourth level of embedding is implemented as generally illustrated in FIG. 48. In particular, an inductor model is connected to the sources of each of the various unit device cells to represent the metallic bridge interconnection, as generally shown in FIG. 48. Lastly, as illustrated in FIG. 49, a fifth level of embedding is implemented in which the feed electrodes model 114 and 116 are modeled as lumped linear elements (i.e. capacitors inductors) as well as the distributive elements (i.e. microstrip lines and junctions) to form the gate feed and drain connections illustrated in FIG. 53. As shown, the distributive elements are distributed models for microstrip elements as implemented in LIBRA 6.1.

EXTRACTION METHOD FOR UNIQUE DETERMINATION OF FET EQUIVALENT CIRCUIT MODELS

The method for determining FET equivalent circuit parameters as discussed above is illustrated in FIGS. 50-55. This method is based on an equivalent circuit model, such as the common source FET equivalent circuit model illustrated in FIG. 5. Referring to FIG. 50 A, a model is initially generated in step 122. In accordance with an important aspect of the algorithm, the equivalent circuit parameters are based upon measured FET S-parameters. Measurement of S-parameters of semiconductor devices is well known in the art. FIG. 53A is a Smith chart illustrating exemplary measured S-parameters SI 1, S12 and S22 for frequencies between 0.05 to 40 GHz. FIG. 53B represents a magnitude angle chart for the measured S-parameter S21 from frequencies from 0.05 to 40 GHz. After the S-parameters are measured, as set forth in step 124

(FIG. 50A), it is ascertained whether the measurements are suitable in step 126. This is either done by manually inspecting the test result for anomalies, or by algorithms to validate the test set. If the measurements are suitable, the S-parameter measurements are stored in step 128. A space of trial starting feedback impedance point values, for example, as illustrated in Table 9 is chosen. Then, a direct model extraction algorithm, known as the Minasian algorithm, is used to generate preliminary values for the equivalent circuit model parameters, for each value of starting feedback impedance. Such extraction algorithms are well known in the art, for example, as disclosed "Broadband Determination of the FET Small Equivalent Small Signal Circuit" by M. Berroth, et al., IEEE - MTT. Vol. 38, No. 7, My 1990. Model parameter values are determined for each of the starting impedance point values illustrated in Table 3. In particular, referring to FIG. 50 A, each impedance point in Table 9 is processed by the blocks 130, 132, etc. to develop model parameter values for each of the impedance point in order to develop an error metric, winch, in turn, is used to develop a unique small signal device model, as will be discussed below. The processing in each of the blocks 130, 132 is similar. Thus, only a single block 130 will be discussed for an exemplary impedance point illustrated in Table 9. In this example, the feedback impedance point 17 which correlates to a source resistance R_s ohm of 1.7Ω and a source inductance L_s of0.0045pH is used.

TABLE 9 Trial Starting Feedback, Impedance Space Point Values

For the selected value, R. = 1.7 ohms, initial intrinsic equivalent circuit parameters and initial parasitic equivalent circuit parameter are determined, for example, by the Minasian algorithm discussed above and illustrated in Tables 10 and

11 as set forth in steps 134 and 136. In step 138, the simulated circuit parameters are compared with the measured S-parameters, for example, as illustrated in FIGS .54A and

54B. Each of the processing blocks 130 and 132 etc. goes through a fixed number of complete cycles, in this example, six complete cycles. As such, the system determines in step 140 whether the six cycles are complete.

TABLE 10 Initial "Intrinsic" Equivalent Circuit Parameters

TABLE 11 Initial "Parasitic" Equivalent Circuit Parameters

Each cycle of the processing block 130 consists of a direct extraction followed by an optimization with a fixed number of optimization iterations, for example 60. By fixing the number of extraction-optimization cycles along with the number of optimization iterations, a fixed "distance" or calculation time which the model solution must be derived is defined. As such, the algorithm implements a convergence speed requirement of the global error metric by setting up an environment where each trial model solution competes against each other by achieving the lowest fitting error over a fixed calculation time thus causing "race" criteria to be implemented where "convergence speed" is implicitly calculated for each processing block 130, 132 etc.

After the system determines whether the racing is done in step 140, the system proceeds to block 142 and optimizes model parameters. Various commercial software programs are available, for example, the commercially available, LIBRA 3.5 software as manufactured by HP-eesof may be used both for circuit simulation as well as optimizing functions. The optimization is performed in accordance with the restrictions set forth in Table 12 with the addition of fixing the feedback resistance R_s to a fixed value. TABLE 12 Environment Used for Competitive Solution Strategy, as Implemented in this

Example

By fixing the value for R_s this segment of the algorithm confined to creating a trial model solution for only the trial feedback impendence point with which it started. Table 13 illustrates the optimized intrinsic equivalent parameter values using commercially available software, such as LIBRA 3.5. These values along with the optimized parasitic values, illustrated in Table 14, form the first optimized model solution for the first extraction-optimization cycle (i.e. one of six). The optimized model parameters are then fed back to the function block 134 and 136 (FIG. 50A) and used for a new initial model solution. These values are compared with the measured S-parameter value as illustrated in FIGS. 54A and 54B. The system repeats this cycle for six cycles in a similar fashion as discussed above. After the six extraction- optimization cycle, the final trial model solution for the trial impendence point 17 is complete along with its final fitting error to the measured data to form the new error metric 144. In accordance with an important aspect, the extraction-optimization algorithm makes the final optimization fitting error for each point implicitly carry information about both the measured to model fitting error and the speed of convergence. It does so by the fixed optimization time constraint which sets up a competitive race between the various trial model solutions. TABLE 13 Optimized "Intrinsic" Equivalent Circuit Parameters

TABLE 14 Optimized "Parasitic" Equivalent Circuit Parameters

The implementation of the extraction optimization cycles makes the best and fastest solving solution appear as a global minima for the final fitting error in step 146 of all of the trial impedance points as generally shown in FIGS. 51 and 52. More specifically, referring to FIG. 51 the global minima solution using the new error metric is found around R_s=1.7 ohms. Tables 15 and 16 list the final model equivalent circuit parameters for this global solution, including the intrinsic and parasitic parameter as set forth in step 148 (FIG. 50B). TABLE 15 Global Solution for "Intrinsic" Equivalent Circuit Parameters

TABLE 16 Global Solution "Parasitic" Equivalent Circuit Parameters

In order to test the accuracy of the solution, the final model for solutions are compared with the measured S-parameter values as shown in FIGS. 55 A and 55B. As shown, there is good correlation between the simulated model values and the measured S-parameters values thus verifying that the simulated model values represent a relatively accurate and unique small signal device model.

Obviously, many modifications and variations of the present invention are possible in light of the above teachings. Thus, it is to be understood that, within the scope of the appended claims, the invention may be practiced otherwise than as specifically described above.

What is claimed and desired to be covered by a Letters Patent is as follows:

Claims

I CLAIM:

1. A method for modeling a semiconductor device comprising the steps of:

(a) modeling the semiconductor device with a semiphysical model;

(b) modeling the semiconductor device with an analytical thermal model; and

(c) coupling the semi-physical model and said analytical conduction model.

2. The method as recited in claim 1, further including step (d) determining the internal charge/electric field structure of the semiconductor device.

3. The method as recited in claim 1, wherein said semi-physical model is configured to replicate measured direct current (DC) current-voltage (I-V) characteristics.

4. The method as recited in claim 3, wherein said semi-physical model is also configured to replicate bias dependent small signal characteristics.

5. the method as recited in claim 4, wherein said semi-physical model is configured to replicate said DC I-V and bias dependent.

6. The method as recited in claim 1, wherein step (b) includes the step (e): measuring the DC-IV characteristics and the S-parameter small signal parameters across a predetermined range of temperatures.

7. The method as recited in claim 6, further including the step (f): extracting small signal equivalent circuit models for each S-parameter measurement as a function of temperature.

8. The method as recited in claim 7, further including step (g): developing temperature co-efficient which adjust the semi-physical device model to match the measured DC and S-parameter measurements at each temperature.

9. The method as recited in claim 1, wherein step (c) includes the step (h): substituting the environment temperature that operates in any temperature dependent terms and temperature co-efficient with the channel temperature of the device.

10. The method as recited in claim (a), wherein step (c) further includes step (i): using of the saturated region as the length of the heat generating region.